Daisuke Ogawa, D. Iguchi, Y. Wada, K. Hashimoto, Y. Taira, Nobutaka Hara, K. Otsuka
For over 20 GHz board level I/O interface circuits, the most serious problem is its high power consumption due to arrange adequate signal forming (pre-emphasis, adaptive equalizer, etc.) and timing adjust circuits that generally require 200 mW/lane for 28-56 Gbps interface. To reduce the power consumption, binary signal (Non Return to the Zero, NRZ) transmission system is fitted to eliminate easily above arrangements. Implementation with FR-4 printed circuit board (PCB) would be an only solution to tackle the problem of production cost of the transmission system. It is well known there are many technical challenges to realize over 200 mm transmission line for signal integrity even with 10 Gbps. With our simulation based analyses, we found that many studies have discussed signal integrity (SI) and power integrity (PI) issues only the range from MHz to 10 GHz of frequency. So it is necessary to consider the transmission parameters of the entire frequency range from direct current (DC) for high-speed I/O circuits especially in transistor level, because MOS devices need constant voltage for the switching operation. In this study, total I/O interface circuit, from CMOS driver through package interconnection to CMOS receiver, is examined mainly by simulation basis for 28 to 56 Gbps signaling. Three types of design were chosen as high speed differential driver / receiver device models, and the transmission characteristics were compared for the SI. One model is developed with TSMC's 65 nm IP, and other models are with 32 nm and 20 nm fin structure models of the Arizona State University's Predictive Technology Model (PTM). The PI parameters for the 40 mm and 200 mm wiring on PCBs, package with capacitors, and chip wiring including on-chip capacitor were studied to reach as possible as ideal voltage source by S-parameter simulation from DC to 100 GHz. We achieved the successful results of the target performance of 56 Gbps in some considered configuration. And the power consumption of our design can be achieved as low as 35 mW on this rate. The most significant aspect to realize our circuit design is the co-design among all I/O circuit parameters. The most effective parameters for our design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration. We made the configuration of the PDF (PDN) at resonance frequency as high as 6.5 GHz. The driver device models examined in this study exhibited no explicit differences in performance up to 56 Gbps.
{"title":"A 56 Gbps I/O Interface Design with Exact Power Source Simulation: Total I/O Circuit Design with over 28 GHz from Driver to Receiver Device Models","authors":"Daisuke Ogawa, D. Iguchi, Y. Wada, K. Hashimoto, Y. Taira, Nobutaka Hara, K. Otsuka","doi":"10.1109/ECTC.2018.00365","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00365","url":null,"abstract":"For over 20 GHz board level I/O interface circuits, the most serious problem is its high power consumption due to arrange adequate signal forming (pre-emphasis, adaptive equalizer, etc.) and timing adjust circuits that generally require 200 mW/lane for 28-56 Gbps interface. To reduce the power consumption, binary signal (Non Return to the Zero, NRZ) transmission system is fitted to eliminate easily above arrangements. Implementation with FR-4 printed circuit board (PCB) would be an only solution to tackle the problem of production cost of the transmission system. It is well known there are many technical challenges to realize over 200 mm transmission line for signal integrity even with 10 Gbps. With our simulation based analyses, we found that many studies have discussed signal integrity (SI) and power integrity (PI) issues only the range from MHz to 10 GHz of frequency. So it is necessary to consider the transmission parameters of the entire frequency range from direct current (DC) for high-speed I/O circuits especially in transistor level, because MOS devices need constant voltage for the switching operation. In this study, total I/O interface circuit, from CMOS driver through package interconnection to CMOS receiver, is examined mainly by simulation basis for 28 to 56 Gbps signaling. Three types of design were chosen as high speed differential driver / receiver device models, and the transmission characteristics were compared for the SI. One model is developed with TSMC's 65 nm IP, and other models are with 32 nm and 20 nm fin structure models of the Arizona State University's Predictive Technology Model (PTM). The PI parameters for the 40 mm and 200 mm wiring on PCBs, package with capacitors, and chip wiring including on-chip capacitor were studied to reach as possible as ideal voltage source by S-parameter simulation from DC to 100 GHz. We achieved the successful results of the target performance of 56 Gbps in some considered configuration. And the power consumption of our design can be achieved as low as 35 mW on this rate. The most significant aspect to realize our circuit design is the co-design among all I/O circuit parameters. The most effective parameters for our design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration. We made the configuration of the PDF (PDN) at resonance frequency as high as 6.5 GHz. The driver device models examined in this study exhibited no explicit differences in performance up to 56 Gbps.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2422-2430"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89756722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 3D package technology has been developed higher performance, higher functionality, smaller and thinner devices for mobile, wearable and IoTs in recent years. Among advanced packaging technologies, advantages of fan-out wafer level package (FOWLP) are its higher I/O density, higher electrical performance, ultra-thin and low power consumption. However, the FOWLP has some mechanical issues about the warpage caused by different coefficient of thermal expansion(CTE) between the various packaging material constituents. We investigated the warpage behavior of FOWLP component with various chip and EMC thickness. The FOWLP component was fabricated by the mold-first process. The 8 × 8 mm2 Si chips (chip thickness: 50, 75 and 100 ?m) were taken placed on the carrier wafer. After that, compression mold (EMC mold thickness: 300 and 460 ?m) was used to fabricate the molded wafer. Redistribution layer (RDL) was fabricated on the molded chip by photolithography. The warpage behavior of the FOWLP component was analyzed from room temperature to 260 °C using shadow moiré method. The environmental reliability of FOWLP component were evaluated by temperature-humidity bias test and thermal shock test. The warpage property depended on ratio of Si chip to EMC thickness. The warpage of FOWLP component with 300 ?m EMC mold and 100 ?m chip thickness whose ratio of Si chip to EMC thickness is 0.33 is about 100 ?m. However, the warpage of other FOWLP component, ratio of Si chip to mold thickness is less than 0.25, is more than 200 ?m. Electrical resistance of FOWLP component were 1.9~2.6 m? and 1.6~2.2 m? after temperature-humidity bias test and thermal shock test, respectively. The electrical resistance of FOWLP component at all sample increased by more than 1.2 times after temperature-humidity bias test and thermal shock test. Warpage was affected by the ratio of chip to EMC thickness.
{"title":"Thermomechanical Properties of Fan-Out Wafer Level Package with Various Chip and Mold Thickness","authors":"Haksan Jeong, W. Myung, K. Jung, Seung-Boo Jung","doi":"10.1109/ECTC.2018.00318","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00318","url":null,"abstract":"The 3D package technology has been developed higher performance, higher functionality, smaller and thinner devices for mobile, wearable and IoTs in recent years. Among advanced packaging technologies, advantages of fan-out wafer level package (FOWLP) are its higher I/O density, higher electrical performance, ultra-thin and low power consumption. However, the FOWLP has some mechanical issues about the warpage caused by different coefficient of thermal expansion(CTE) between the various packaging material constituents. We investigated the warpage behavior of FOWLP component with various chip and EMC thickness. The FOWLP component was fabricated by the mold-first process. The 8 × 8 mm2 Si chips (chip thickness: 50, 75 and 100 ?m) were taken placed on the carrier wafer. After that, compression mold (EMC mold thickness: 300 and 460 ?m) was used to fabricate the molded wafer. Redistribution layer (RDL) was fabricated on the molded chip by photolithography. The warpage behavior of the FOWLP component was analyzed from room temperature to 260 °C using shadow moiré method. The environmental reliability of FOWLP component were evaluated by temperature-humidity bias test and thermal shock test. The warpage property depended on ratio of Si chip to EMC thickness. The warpage of FOWLP component with 300 ?m EMC mold and 100 ?m chip thickness whose ratio of Si chip to EMC thickness is 0.33 is about 100 ?m. However, the warpage of other FOWLP component, ratio of Si chip to mold thickness is less than 0.25, is more than 200 ?m. Electrical resistance of FOWLP component were 1.9~2.6 m? and 1.6~2.2 m? after temperature-humidity bias test and thermal shock test, respectively. The electrical resistance of FOWLP component at all sample increased by more than 1.2 times after temperature-humidity bias test and thermal shock test. Warpage was affected by the ratio of chip to EMC thickness.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"2121-2126"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89409962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Tang, Kelly Chen, K. Tsai, Max Lu, Jensen Tsai, Yu-Po Wang
Biometric features, such as fingerprint, facial recognition, etc, are convenient personal identification methods in mobile electronics. Fingerprint recognition is one of mature technologies and is embedded in an increasing number of mobile devices. For fingerprint sensor packaging, wire bonding and over-molding Land Grid Array (LGA) is one of major package types. Inside the wire bond LGA package, the dielectric constant (Dk) of over-molding compounds is one dominant factor for the sensitivity of capacitive fingerprint sensors. Normal molding compounds contain epoxy base polymers and silica base fillers. Their Dk value is relative low (3~5 at 1 MHz). Those compounds are suitable for the general encapsulation purpose. But they have shielding effects on the sensing signal transmission in capacitive fingerprint sensor packages. This shielding effect needs to be reduced as much as possible, especially when thick glass is used on fingerprint module for the mechanical protection. Therefore, high Dk (7~40 at 1 MHz) molding compounds were developed for the sensor performance enhancement. High Dk property of molding compound can be achieved by using new type polymers and metal oxide fillers. With new type polymers and fillers, the major challenges of high Dk molding compounds come from the warpage and stress during the package assembly process. In order to diminish the warpage and stress, lots of experiments were conducted which including molding compound composition adjustment, post-mold cure process optimization and so on. In this paper, several types of high dielectric constant molding compounds were evaluated and compared. Stress simulations were performed to determine the package construction. Screen and corner DoEs of molding process parameters were conducted to come out the process window. Functional test and reliability test have been preformed as well. Two types of high Dk molding compounds have proven to be feasible and reliable materials for enhancing the performance of fingerprint sensors.
生物特征，如指纹、面部识别等，是移动电子中方便的个人识别方法。指纹识别是一项成熟的技术，越来越多的移动设备中嵌入了指纹识别技术。对于指纹传感器封装来说，线键合和覆盖成型的栅格阵列(LGA)是主要的封装类型之一。在线键合LGA封装中，过模化合物的介电常数(Dk)是影响电容式指纹传感器灵敏度的主要因素。普通成型化合物含有环氧基聚合物和硅基填料。它们的Dk值相对较低(1 MHz时为3~5)。这些化合物适用于一般包封用途。但它们对电容式指纹传感器封装中的传感信号传输有屏蔽作用。这种屏蔽效果需要尽可能的降低，特别是当指纹模块使用厚玻璃进行机械保护时。因此，为了提高传感器的性能，开发了高Dk (7~40 at 1 MHz)的成型化合物。采用新型聚合物和金属氧化物填料可获得高Dk性能的模塑复合材料。随着新型聚合物和填料的出现，高Dk成型化合物的主要挑战来自封装组装过程中的翘曲和应力。为了减少翘曲和应力，进行了大量的试验，包括模塑复合成分的调整，模后固化工艺的优化等。本文对几种高介电常数模塑化合物进行了评价和比较。通过应力模拟来确定包的结构。对成型工艺参数进行了筛角分析，得出了工艺窗口。并进行了功能试验和可靠性试验。两种高Dk模塑化合物已被证明是提高指纹传感器性能的可行和可靠的材料。
{"title":"High Dielectric Constant Molding Compounds for Fingerprint Sensor Packages","authors":"T. Tang, Kelly Chen, K. Tsai, Max Lu, Jensen Tsai, Yu-Po Wang","doi":"10.1109/ECTC.2018.00142","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00142","url":null,"abstract":"Biometric features, such as fingerprint, facial recognition, etc, are convenient personal identification methods in mobile electronics. Fingerprint recognition is one of mature technologies and is embedded in an increasing number of mobile devices. For fingerprint sensor packaging, wire bonding and over-molding Land Grid Array (LGA) is one of major package types. Inside the wire bond LGA package, the dielectric constant (Dk) of over-molding compounds is one dominant factor for the sensitivity of capacitive fingerprint sensors. Normal molding compounds contain epoxy base polymers and silica base fillers. Their Dk value is relative low (3~5 at 1 MHz). Those compounds are suitable for the general encapsulation purpose. But they have shielding effects on the sensing signal transmission in capacitive fingerprint sensor packages. This shielding effect needs to be reduced as much as possible, especially when thick glass is used on fingerprint module for the mechanical protection. Therefore, high Dk (7~40 at 1 MHz) molding compounds were developed for the sensor performance enhancement. High Dk property of molding compound can be achieved by using new type polymers and metal oxide fillers. With new type polymers and fillers, the major challenges of high Dk molding compounds come from the warpage and stress during the package assembly process. In order to diminish the warpage and stress, lots of experiments were conducted which including molding compound composition adjustment, post-mold cure process optimization and so on. In this paper, several types of high dielectric constant molding compounds were evaluated and compared. Stress simulations were performed to determine the package construction. Screen and corner DoEs of molding process parameters were conducted to come out the process window. Functional test and reliability test have been preformed as well. Two types of high Dk molding compounds have proven to be feasible and reliable materials for enhancing the performance of fingerprint sensors.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"926-931"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87209508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C.K. Yu, W. S. Chiang, P.S. Huang, M. Z. Lin, Y.H. Fang, M. J. Lin, C. Peng, B. Lin, Michael Huang
Driven by aggressive product roadmap of high performance and low power IC, the complexity of both design and interconnection has significantly increased for field requirements. Unlike single-die FCBGA area limitation (generally within 600 mm2), fan-out technology significantly extends the die scale far beyond and largely improves both SI and PI requirements. To name a few, networking product is one of the specific applications; wired-ASIC would be another. However, fan-out structure inherently exhibits weaker mechanical properties due to its substrate-less process. As a consequence, study on the high latent risk of chip-to-package interaction (CPI) becomes important for the success of this technology. In this work, the reliability of CPI was experimentally investigated at 16nm FinFET process node on a large scale die size (~860mm2) and FOBGA package size (67.5mm*67.5mm). The result shows no CPI induced defect was found owing to specific RDL pattern was designed. Also the heat spreader type (including ring, lid, and without spreader) were studied, and the result shows that the stiffener ring could help on reducing overall package warpage by 20% as compared with the one without ring. And the lid type heat spreader having highest stiffness performed the best warpage behavior. Furthermore, it was revealed that optimizing ring type spreader width effectively reduces the deformation variation in the temperature range from 25 °C to 150 °C. Moreover, the board level reliability, including temperature cycling and drop tests, for the FOBGA was evaluated experimentally with daisy-chain PCB. Despite the low risk exhibited by board-level mechanical stress tests, e.g. shock and monotonic bend tests, on die bump and fan-out RDL, the BGA ball lifetime seemed to be inevitably getting worse under thermal gradient stress (temperature cycling). This was majorly due to the warpage behavior induced by large package size. It has been well known that PCB design variation causes dynamic and fatigue failure discrepancies. In this paper, through-hole design (Cu plating or Cu paste filling) and core material were studied on the effects of PCB design variants on board level thermal stress. The result shows the PCB with high Tg core or with Cu-paste filled through hole, has much better temperature cycling reliability than the one with Cu-plated-through-hole PCB. And there was no failure which relevant to CPI issue was found even after 2500-cycle TCT. Moreover, the board level dropping results reveal that the large FOBGA passed the drop test.
{"title":"Reliability Study of Large Fan-Out BGA Solution on FinFET Process","authors":"C.K. Yu, W. S. Chiang, P.S. Huang, M. Z. Lin, Y.H. Fang, M. J. Lin, C. Peng, B. Lin, Michael Huang","doi":"10.1109/ECTC.2018.00245","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00245","url":null,"abstract":"Driven by aggressive product roadmap of high performance and low power IC, the complexity of both design and interconnection has significantly increased for field requirements. Unlike single-die FCBGA area limitation (generally within 600 mm2), fan-out technology significantly extends the die scale far beyond and largely improves both SI and PI requirements. To name a few, networking product is one of the specific applications; wired-ASIC would be another. However, fan-out structure inherently exhibits weaker mechanical properties due to its substrate-less process. As a consequence, study on the high latent risk of chip-to-package interaction (CPI) becomes important for the success of this technology. In this work, the reliability of CPI was experimentally investigated at 16nm FinFET process node on a large scale die size (~860mm2) and FOBGA package size (67.5mm*67.5mm). The result shows no CPI induced defect was found owing to specific RDL pattern was designed. Also the heat spreader type (including ring, lid, and without spreader) were studied, and the result shows that the stiffener ring could help on reducing overall package warpage by 20% as compared with the one without ring. And the lid type heat spreader having highest stiffness performed the best warpage behavior. Furthermore, it was revealed that optimizing ring type spreader width effectively reduces the deformation variation in the temperature range from 25 °C to 150 °C. Moreover, the board level reliability, including temperature cycling and drop tests, for the FOBGA was evaluated experimentally with daisy-chain PCB. Despite the low risk exhibited by board-level mechanical stress tests, e.g. shock and monotonic bend tests, on die bump and fan-out RDL, the BGA ball lifetime seemed to be inevitably getting worse under thermal gradient stress (temperature cycling). This was majorly due to the warpage behavior induced by large package size. It has been well known that PCB design variation causes dynamic and fatigue failure discrepancies. In this paper, through-hole design (Cu plating or Cu paste filling) and core material were studied on the effects of PCB design variants on board level thermal stress. The result shows the PCB with high Tg core or with Cu-paste filled through hole, has much better temperature cycling reliability than the one with Cu-plated-through-hole PCB. And there was no failure which relevant to CPI issue was found even after 2500-cycle TCT. Moreover, the board level dropping results reveal that the large FOBGA passed the drop test.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"1623-1627"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73513579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Van-Lai Pham, Yuling Niu, Jing Wang, Huayan Wang, Charandeep Singh, Seungbae Park, Cheng Zhong, S. Koh, Jifan Wang, Shuai Shao
The stacked 3D packaging is a trend in current electronic packaging field. The stacked dies are molded to insulate the functional chips from the moisture or the dust. To achieve electrical performance or cost benefits, potential 3D integration schemes that were developed vertically may cause cruel reliability issues, like warpage. For an 8 × 8 × 6 mm3 Wafer Level Package (WLP), the warpage behavior at the top surface cannot comprehensively represent the package deformation since the considerable height change between the PCB and the component's surface, To investigate the solder reliability one indirect way is to observe the relative height change from the edges or the corners of the top surface to the bottom PCB or substrate surface. In this case, the closer the two data points we select-one on the surface component and another on the substrate-the clearer situation it will illustrate. However, there is a gap between those points since the shadow and blind areas caused by the light source and camera angle. Hence, reducing the gap distance is a major concern. In this work, an experimental study on minimizing this gap between a wafer-level-chip-scale-package, (8mm× 8 mm with 6mm and 4 mm heights), and PCB were accomplished with the digital image correlation (DIC) technique. Key factors such as camera angle, white light source, sample orientation, and the subset size and step were studied and experimentally optimized to achieve accurate results. These optimal parameters were aimed to keep the gap distance less than 0.5mm during the extra tall packages measurement.
{"title":"Experimentally Minimizing the Gap Distance Between Extra Tall Packages and PCB Using the Digital Image Correlation (DIC) Method","authors":"Van-Lai Pham, Yuling Niu, Jing Wang, Huayan Wang, Charandeep Singh, Seungbae Park, Cheng Zhong, S. Koh, Jifan Wang, Shuai Shao","doi":"10.1109/ECTC.2018.00241","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00241","url":null,"abstract":"The stacked 3D packaging is a trend in current electronic packaging field. The stacked dies are molded to insulate the functional chips from the moisture or the dust. To achieve electrical performance or cost benefits, potential 3D integration schemes that were developed vertically may cause cruel reliability issues, like warpage. For an 8 × 8 × 6 mm3 Wafer Level Package (WLP), the warpage behavior at the top surface cannot comprehensively represent the package deformation since the considerable height change between the PCB and the component's surface, To investigate the solder reliability one indirect way is to observe the relative height change from the edges or the corners of the top surface to the bottom PCB or substrate surface. In this case, the closer the two data points we select-one on the surface component and another on the substrate-the clearer situation it will illustrate. However, there is a gap between those points since the shadow and blind areas caused by the light source and camera angle. Hence, reducing the gap distance is a major concern. In this work, an experimental study on minimizing this gap between a wafer-level-chip-scale-package, (8mm× 8 mm with 6mm and 4 mm heights), and PCB were accomplished with the digital image correlation (DIC) technique. Key factors such as camera angle, white light source, sample orientation, and the subset size and step were studied and experimentally optimized to achieve accurate results. These optimal parameters were aimed to keep the gap distance less than 0.5mm during the extra tall packages measurement.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"83 1","pages":"1593-1599"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78106302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cheng Chen, Teng Wang, Daquan Yu, Shuying Ma, Kai Zhu, Zhiyi Xiao, L. Wan
In this paper, ultra-thin eSiFO packages with body thickness of 150 µm were presented and the reliability were comprehensively studied, with an emphasis on temperature cycling (TC) and drop test reliability. The test vehicle was designed in two different sizes: a 3×3 mm package with a single 1.4×1.4 mm embedded die and a 9×9 mm package with a single 7×7 mm embedded die. Several electrical measurement structures, such as daisy chains, Kelvin test units and leakage current test units were built in the test vehicles. Manufacturing process of the ultra-thin test vehicles were described at the first, then the package level reliability and board level reliability were also studied. The possible failure modes were determined by electrical test and cross-section observation. Experimental results show that ultra-thin eSiFO packages have a stable manufacturing process, good package level reliability and board level drop reliability acceptable for mobile applications regardless of the package size. Temperature cycling on board experiments show that ultra-thin eSiFO package has a similar solder joint fatigue life to standard WLCSPs and typical eWLBs. The results of this work offer an important reference for reliability of embedded, fan-out packages and other ultra-thin WLCSPs.
{"title":"Reliability of Ultra-Thin Embedded Silicon Fan-Out (eSiFO) Package Directly Assembled on PCB for Mobile Applications","authors":"Cheng Chen, Teng Wang, Daquan Yu, Shuying Ma, Kai Zhu, Zhiyi Xiao, L. Wan","doi":"10.1109/ECTC.2018.00242","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00242","url":null,"abstract":"In this paper, ultra-thin eSiFO packages with body thickness of 150 µm were presented and the reliability were comprehensively studied, with an emphasis on temperature cycling (TC) and drop test reliability. The test vehicle was designed in two different sizes: a 3×3 mm package with a single 1.4×1.4 mm embedded die and a 9×9 mm package with a single 7×7 mm embedded die. Several electrical measurement structures, such as daisy chains, Kelvin test units and leakage current test units were built in the test vehicles. Manufacturing process of the ultra-thin test vehicles were described at the first, then the package level reliability and board level reliability were also studied. The possible failure modes were determined by electrical test and cross-section observation. Experimental results show that ultra-thin eSiFO packages have a stable manufacturing process, good package level reliability and board level drop reliability acceptable for mobile applications regardless of the package size. Temperature cycling on board experiments show that ultra-thin eSiFO package has a similar solder joint fatigue life to standard WLCSPs and typical eWLBs. The results of this work offer an important reference for reliability of embedded, fan-out packages and other ultra-thin WLCSPs.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1600-1606"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75242392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Uemura, K. Warabi, K. Ohira, Y. Kurita, H. Yoshida, H. Furuyama, Y. Sugizaki, H. Shibata
We propose a novel Si photonics module that overcomes the issues of conventional Si photonics modules such as package structure and electrical connection. The module incorporates an optical fiber socket fabricated by blind via socket (BVS) technology, which implements backside optical I/O in a photonic IC (PIC) by forming blind via holes on the backside. High-speed high-density electrical connection to both the PIC and an electrical IC (EIC) is also obtained in the module by fan-out wafer level packaging (FOWLP) technology. These technologies achieve a surface-mountable substrate-less fan-out optical module. It realizes a practicable integrated module of optoelectronic devices excellent in terms of electrical characteristics such as signal integrity (SI) and power integrity (PI), heat characteristics, and miniaturization. This paper presents a BVS module that enables optical coupling between a III-V/Si photodiode (PD) fabricated on a Si substrate and a multi-mode optical fiber by passive alignment of only insertion of the fiber into a blind via hole on the backside. High-speed optical signal transmission is also demonstrated with a fan-out optical module in which a BVS and an EIC are integrated by FOWLP and a vertical-cavity surface-emitting laser (VCSEL) or PD is mounted on the BVS.
{"title":"Backside Optical I/O Module for Si Photonics Integrated with Electrical ICs Using Fan-Out Wafer Level Packaging Technology","authors":"H. Uemura, K. Warabi, K. Ohira, Y. Kurita, H. Yoshida, H. Furuyama, Y. Sugizaki, H. Shibata","doi":"10.1109/ECTC.2018.00127","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00127","url":null,"abstract":"We propose a novel Si photonics module that overcomes the issues of conventional Si photonics modules such as package structure and electrical connection. The module incorporates an optical fiber socket fabricated by blind via socket (BVS) technology, which implements backside optical I/O in a photonic IC (PIC) by forming blind via holes on the backside. High-speed high-density electrical connection to both the PIC and an electrical IC (EIC) is also obtained in the module by fan-out wafer level packaging (FOWLP) technology. These technologies achieve a surface-mountable substrate-less fan-out optical module. It realizes a practicable integrated module of optoelectronic devices excellent in terms of electrical characteristics such as signal integrity (SI) and power integrity (PI), heat characteristics, and miniaturization. This paper presents a BVS module that enables optical coupling between a III-V/Si photodiode (PD) fabricated on a Si substrate and a multi-mode optical fiber by passive alignment of only insertion of the fiber into a blind via hole on the backside. High-speed optical signal transmission is also demonstrated with a fan-out optical module in which a BVS and an EIC are integrated by FOWLP and a vertical-cavity surface-emitting laser (VCSEL) or PD is mounted on the BVS.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"119 1","pages":"822-827"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77967137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mm-Wave bands defined as the new radio in the fifth generation (5G) mobile networks would decrease the dimension of the antenna into the scale of package level. In this study, a patch antenna array with stacked patches was designed for a wider operation frequency band than a typical patch. By considering a better electrical performance of the antenna in package (AiP), an unbalanced substrate of 4-layer metal stack-up within the processing capacity is proposed in this paper. The proposed unbalanced substrate structure is more elegant than the conventional substrate structure because of fewer substrate layers. The electrical and dimensional data are collected and analyzed. The designed patch antenna in this paper shows good correlations between simulations and measurements. The measured results show that the 1×4 patch array achieves a bandwidth of about 15.4 % with -10 dB return loss and gain of 10.8 dBi.
{"title":"Mm-Wave Antenna in Package (AiP) Design Applied to 5th Generation (5G) Cellular User Equipment Using Unbalanced Substrate","authors":"Y. Lu, Bo-Siang Fang, Hsuan-Hao Mi, Kuan-Ta Chen","doi":"10.1109/ECTC.2018.00040","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00040","url":null,"abstract":"The mm-Wave bands defined as the new radio in the fifth generation (5G) mobile networks would decrease the dimension of the antenna into the scale of package level. In this study, a patch antenna array with stacked patches was designed for a wider operation frequency band than a typical patch. By considering a better electrical performance of the antenna in package (AiP), an unbalanced substrate of 4-layer metal stack-up within the processing capacity is proposed in this paper. The proposed unbalanced substrate structure is more elegant than the conventional substrate structure because of fewer substrate layers. The electrical and dimensional data are collected and analyzed. The designed patch antenna in this paper shows good correlations between simulations and measurements. The measured results show that the 1×4 patch array achieves a bandwidth of about 15.4 % with -10 dB return loss and gain of 10.8 dBi.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"208-213"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76238531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Nobari, S. St-Laurent, Y. Thomas, Arslane Bouchemit, G. L’espérance
The continuing demand for smaller and lighter electronic products has driven the use of miniature components. The assembly of these miniature components requires fine solder joints; and, finer solder joints require advanced solder pastes with finer particle sizes. In general, there are four key characteristics for any powder: purity, particle size distribution, surface oxide, and morphology. However, a complete understanding of the effect of key solder powder characteristics on the paste properties is still not achieved. This understanding becomes much more important when new solder pastes with finer powder size (Type 5, 6, 7, and 8) are developed for advanced applications in semiconductor packaging. In this work, SAC305 (Sn-3Ag-0.5Cu) powders is produced with a proprietary atomizing technology, particularly effective in producing solder powder ranging from 1 to 25 µm. Powder characteristics considered are particle size distribution and powder oxidation. The surface oxide layer is characterized using Auger Electron Spectroscopy and Transmission Electron Microscopy and characterization of the surface oxide layer is presented for powders with various particle size distributions. The relation between surface oxide thickness and reflow performance is described. Finally, a powder treatment will be shown to be required to improve the robustness of solder paste in certain conditions. The influence of the powder treatment on the reflow performance of solder paste will be discussed. The results and knowledge obtained by the systematic study presented in this paper can be applied to design new and advanced solder pastes with fine powders.
{"title":"Performance of Fine and Ultra-Fine Lead-Free Powders for Solder Paste Applications","authors":"A. Nobari, S. St-Laurent, Y. Thomas, Arslane Bouchemit, G. L’espérance","doi":"10.1109/ECTC.2018.00291","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00291","url":null,"abstract":"The continuing demand for smaller and lighter electronic products has driven the use of miniature components. The assembly of these miniature components requires fine solder joints; and, finer solder joints require advanced solder pastes with finer particle sizes. In general, there are four key characteristics for any powder: purity, particle size distribution, surface oxide, and morphology. However, a complete understanding of the effect of key solder powder characteristics on the paste properties is still not achieved. This understanding becomes much more important when new solder pastes with finer powder size (Type 5, 6, 7, and 8) are developed for advanced applications in semiconductor packaging. In this work, SAC305 (Sn-3Ag-0.5Cu) powders is produced with a proprietary atomizing technology, particularly effective in producing solder powder ranging from 1 to 25 µm. Powder characteristics considered are particle size distribution and powder oxidation. The surface oxide layer is characterized using Auger Electron Spectroscopy and Transmission Electron Microscopy and characterization of the surface oxide layer is presented for powders with various particle size distributions. The relation between surface oxide thickness and reflow performance is described. Finally, a powder treatment will be shown to be required to improve the robustness of solder paste in certain conditions. The influence of the powder treatment on the reflow performance of solder paste will be discussed. The results and knowledge obtained by the systematic study presented in this paper can be applied to design new and advanced solder pastes with fine powders.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"58 1","pages":"1942-1950"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72739912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lee, Cheng-Chih Chen, Lane Brown, Esme Mehretu, T. Obrien, Feng Lu
In the study, a proprietary strain-controllable dynamic bending method was adopted to verify the memory package effects on the solder joint reliability in the PoP package, instead of electrical resistance monitoring in the JESD22-B111 using mechanical shock testing of package on board at a single shock pulse for handheld electronic device dropping simulation. Two test vehicles were designed for comparison. One is flip chip BGA as bottom package with memory package stacked on the top, another one is same flip chip BGA package. The PoP package with SnAgCu based interconnection on the bottom and top package underperformed same bottom flip chip BGA package in terms of solder joint life between package and PCB in the dynamic bending test, which illustrated the top memory package will affect adversely the solder joint reliability of bottom package.
{"title":"A Dynamic Bending Method for PoP Package Board Level Reliability Validation","authors":"J. Lee, Cheng-Chih Chen, Lane Brown, Esme Mehretu, T. Obrien, Feng Lu","doi":"10.1109/ECTC.2018.00334","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00334","url":null,"abstract":"In the study, a proprietary strain-controllable dynamic bending method was adopted to verify the memory package effects on the solder joint reliability in the PoP package, instead of electrical resistance monitoring in the JESD22-B111 using mechanical shock testing of package on board at a single shock pulse for handheld electronic device dropping simulation. Two test vehicles were designed for comparison. One is flip chip BGA as bottom package with memory package stacked on the top, another one is same flip chip BGA package. The PoP package with SnAgCu based interconnection on the bottom and top package underperformed same bottom flip chip BGA package in terms of solder joint life between package and PCB in the dynamic bending test, which illustrated the top memory package will affect adversely the solder joint reliability of bottom package.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"40 2","pages":"2223-2229"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72604917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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