Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937867
Kumar Mp, Praveen C Ramamnurthy
Transparent conducting electrode for the organic optoelectronic devices are gathering a tremendous amount of interest. Most of the conducting electrodes like Indium Tin Oxide (ITO) are fabricated at high temperature. In recent years, flexible transparent electrodes fabricated with silver nanowires (AgNWs) extensively studied. This is a promising alternative to ITO film in an optoelectronic application. ITO may present good conductivity and transparency for the optoelectronic device but, due to its mechanical non-robust nature, it is hard to fabricate, process and use on flexible substrates like poly (ethylene terephthalate) (PET) and epoxy. These solution process methods are also important due to ease of process and large area coating without losing its electronic property. In this work alternative conducting electrodes are prepared by solution process and effect of the silver nanowire on sheet resistance has been studied. Optical and mechanical properties correlated to electronic properties are also evaluated.
{"title":"Alternative transparent conducting electrode for flexible optoelectronics","authors":"Kumar Mp, Praveen C Ramamnurthy","doi":"10.1109/icee44586.2018.8937867","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937867","url":null,"abstract":"Transparent conducting electrode for the organic optoelectronic devices are gathering a tremendous amount of interest. Most of the conducting electrodes like Indium Tin Oxide (ITO) are fabricated at high temperature. In recent years, flexible transparent electrodes fabricated with silver nanowires (AgNWs) extensively studied. This is a promising alternative to ITO film in an optoelectronic application. ITO may present good conductivity and transparency for the optoelectronic device but, due to its mechanical non-robust nature, it is hard to fabricate, process and use on flexible substrates like poly (ethylene terephthalate) (PET) and epoxy. These solution process methods are also important due to ease of process and large area coating without losing its electronic property. In this work alternative conducting electrodes are prepared by solution process and effect of the silver nanowire on sheet resistance has been studied. Optical and mechanical properties correlated to electronic properties are also evaluated.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"34 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81775539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937973
Haobijam Johnson Singh, Ambarish Ghosh
We report a novel way of fabricating a large area dielectric metasurface on a flexible substrate using template stripped technique. The dielectric metasurface which consisted of high index Si nanoparticle arrays, exhibits strong narrow optical resonances in near IR (~ 830 nm) with a Q-factor as large as 100. The dielectric material platform is low loss and CMOS compatible which together could be promising for applications in the field of integrated flexible opto-electronics and adaptive photonic systems.
{"title":"Fabrication of Large Area Flexible Dielectric Metasurafces","authors":"Haobijam Johnson Singh, Ambarish Ghosh","doi":"10.1109/icee44586.2018.8937973","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937973","url":null,"abstract":"We report a novel way of fabricating a large area dielectric metasurface on a flexible substrate using template stripped technique. The dielectric metasurface which consisted of high index Si nanoparticle arrays, exhibits strong narrow optical resonances in near IR (~ 830 nm) with a Q-factor as large as 100. The dielectric material platform is low loss and CMOS compatible which together could be promising for applications in the field of integrated flexible opto-electronics and adaptive photonic systems.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"97 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85940397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937901
Ishan Varun, Deepak Bharti, A. Mahato, Vivek Raghuwanshi, S. P. Tiwari
A PMMA based Ag/PMMA/Ti/Glass RRAM devices are reported for their resistive switching behavior. Switching performance was tested on three samples fabricated at different PMMA annealing temperatures. The switching voltages have shown a down trend with increasing annealing temperature. The Current on/off ratio and retention time also degrades with annealing temperature. The devices exhibited significantly low switching voltages (<1 V) and retention time upto 103 s. Annealing of PMMA at higher temperatures may result in softening of films resulting in lower switching voltages due to defects generation and easy charge migration. The conduction mechanism has been investigated by double log plot of I-V characteristics of device suggesting ohmic conduction at lower voltages in in HRS and in LRS. At higher voltages in HRS, space charge limited conduction dominates the conduction mechanism.
{"title":"Effect of Annealing on Resistive Switching Behavior of PMMA Based RRAM","authors":"Ishan Varun, Deepak Bharti, A. Mahato, Vivek Raghuwanshi, S. P. Tiwari","doi":"10.1109/icee44586.2018.8937901","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937901","url":null,"abstract":"A PMMA based Ag/PMMA/Ti/Glass RRAM devices are reported for their resistive switching behavior. Switching performance was tested on three samples fabricated at different PMMA annealing temperatures. The switching voltages have shown a down trend with increasing annealing temperature. The Current on/off ratio and retention time also degrades with annealing temperature. The devices exhibited significantly low switching voltages (<1 V) and retention time upto 103 s. Annealing of PMMA at higher temperatures may result in softening of films resulting in lower switching voltages due to defects generation and easy charge migration. The conduction mechanism has been investigated by double log plot of I-V characteristics of device suggesting ohmic conduction at lower voltages in in HRS and in LRS. At higher voltages in HRS, space charge limited conduction dominates the conduction mechanism.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"99 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80994268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8938007
Roopa Prakash, V. Balaswamy, Vishal Choudhury, V. Supradeepa
A narrow-band, fixed-wavelength cascaded Raman resonator can be effectively used only for a given input wavelength. The efficiency of wavelength conversion of a cascaded Raman resonator decreases sharply when a non-resonant pump is used. Designing and fabricating new grating sets for the resonator for different pump sources isn’t a feasible option as it compromises the simplicity and cost-effectiveness of this approach. We identified that by seeding the cascaded Raman conversion suitably, a substantial improvement in efficiency can be achieved. This is demonstrated using a coupler-based broadband reflector to significantly improve the performance of CRR for a non-resonant pump source. Remarkable improvement in efficiency is obtained with $sim 70$% of the output power at 1480nm Stokes wavelength when the CRR is pumped by a 16W Ytterbium doped fiber laser at 1057nm.
{"title":"Increasing the efficiency of a fixed-wavelength cascaded Raman resonator for a non-resonant pump by using a reflector","authors":"Roopa Prakash, V. Balaswamy, Vishal Choudhury, V. Supradeepa","doi":"10.1109/icee44586.2018.8938007","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8938007","url":null,"abstract":"A narrow-band, fixed-wavelength cascaded Raman resonator can be effectively used only for a given input wavelength. The efficiency of wavelength conversion of a cascaded Raman resonator decreases sharply when a non-resonant pump is used. Designing and fabricating new grating sets for the resonator for different pump sources isn’t a feasible option as it compromises the simplicity and cost-effectiveness of this approach. We identified that by seeding the cascaded Raman conversion suitably, a substantial improvement in efficiency can be achieved. This is demonstrated using a coupler-based broadband reflector to significantly improve the performance of CRR for a non-resonant pump source. Remarkable improvement in efficiency is obtained with $sim 70$% of the output power at 1480nm Stokes wavelength when the CRR is pumped by a 16W Ytterbium doped fiber laser at 1057nm.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"48 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77346311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937902
V. Adiga, A. D. Rao, Shishir V. Kumar, S. Raghavan, Praveen C Ramamurthy
Flexible and transparent moisture barrier films have been climacteric importance for the further development of the polymer solar cells (PSCs). Herein, a monolayer graphene (2D atomic crystal) embedded in a flexible polymer (GEPs) was used to encapsulate the solar cells. The improvement of long-term stability of PSCs still needs to be overcome for their commercialization to be feasible.Degradation mechanisms studied in ITO/ZnO/PTB7:PC70 BM/MoO3/Ag inverted PSCs by Capacitance-voltage, Capacitance-frequency and light intensity dependent measurements is reported here. Measurements was performed on encapsulated and nonencapsulated (controlled and ambient environment) cells under AM1.5 illumination. However, the degradation studies performed with the ISOS D1 protocol suggested the increased lifetimes of the PSCs encapsulated with GEPs barrier films. A promising lifetime of more than 20000 hours was demonstrated with less than 22 % degradation for encapsulated devices.
{"title":"Long term aging studies of Graphene/Surlyn encapsulated organic photovoltaic devices","authors":"V. Adiga, A. D. Rao, Shishir V. Kumar, S. Raghavan, Praveen C Ramamurthy","doi":"10.1109/icee44586.2018.8937902","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937902","url":null,"abstract":"Flexible and transparent moisture barrier films have been climacteric importance for the further development of the polymer solar cells (PSCs). Herein, a monolayer graphene (2D atomic crystal) embedded in a flexible polymer (GEPs) was used to encapsulate the solar cells. The improvement of long-term stability of PSCs still needs to be overcome for their commercialization to be feasible.Degradation mechanisms studied in ITO/ZnO/PTB7:PC70 BM/MoO3/Ag inverted PSCs by Capacitance-voltage, Capacitance-frequency and light intensity dependent measurements is reported here. Measurements was performed on encapsulated and nonencapsulated (controlled and ambient environment) cells under AM1.5 illumination. However, the degradation studies performed with the ISOS D1 protocol suggested the increased lifetimes of the PSCs encapsulated with GEPs barrier films. A promising lifetime of more than 20000 hours was demonstrated with less than 22 % degradation for encapsulated devices.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87897725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937978
S. Kothari, J. Rathore, Krista R. Khiangte, S. Mahapatra, S. Lodha
This work reports a comparative study of different interlayers (ILs) in low thermal budget gate stacks on GeSn substrates with 8.5% and 11% of Sn concentration. It is shown through electrical capacitance-voltage $(C-V)$ and xray photoelectron spectroscopy (XPS) characterization that aluminum-based ILs help in reducing the density of interface traps $(mathrm{D}_{it})$ by suppressing Sn-O formation during HfO2 high k dielectric deposition. Pre-oxidation before IL deposition was found to be essential to reduce the C–V stretch-out indicating reduction in $mathrm{D}_{it}$. XPS data also suggests that AlN is likely to perform better than Al2O3 as an IL for further reduction of $mathrm{D}_{it}$ at the GeSn gate stack interface.
{"title":"Interlayer Engineering in GeSn Gate Stacks for Advanced CMOS","authors":"S. Kothari, J. Rathore, Krista R. Khiangte, S. Mahapatra, S. Lodha","doi":"10.1109/icee44586.2018.8937978","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937978","url":null,"abstract":"This work reports a comparative study of different interlayers (ILs) in low thermal budget gate stacks on GeSn substrates with 8.5% and 11% of Sn concentration. It is shown through electrical capacitance-voltage $(C-V)$ and xray photoelectron spectroscopy (XPS) characterization that aluminum-based ILs help in reducing the density of interface traps $(mathrm{D}_{it})$ by suppressing Sn-O formation during HfO2 high k dielectric deposition. Pre-oxidation before IL deposition was found to be essential to reduce the C–V stretch-out indicating reduction in $mathrm{D}_{it}$. XPS data also suggests that AlN is likely to perform better than Al2O3 as an IL for further reduction of $mathrm{D}_{it}$ at the GeSn gate stack interface.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90964168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937951
Shubham Jadhav, Babu R. Singh, S. Chandorkar, R. Pratap
In this work, Plackett-Burman design is used to optimize platinum thin film sputtering parameters. The effect of different deposition parameters on Pt (111) rocking curve FWHM, residual stress and roughness of Pt film was studied. These substrate parameters are known to influence the quality of AlN deposited on it. It was concluded that most critical parameters deciding platinum film quality are power, annealing temperature, and deposition pressure. By identifying the most critical parameters, we narrowed our subsequent two-level factorial optimization domain by a factor of 16. Furthermore, based on the Plackett-Burman screening, the optimal values of non-critical process parameters can be set by a judicious choice that would yield best results for one of the features of film quality without adversely affecting the other features.
{"title":"Optimization of platinum thin film as a bottom electrode for aluminum nitride thin films using Plackett-Burman statistical approach","authors":"Shubham Jadhav, Babu R. Singh, S. Chandorkar, R. Pratap","doi":"10.1109/icee44586.2018.8937951","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937951","url":null,"abstract":"In this work, Plackett-Burman design is used to optimize platinum thin film sputtering parameters. The effect of different deposition parameters on Pt (111) rocking curve FWHM, residual stress and roughness of Pt film was studied. These substrate parameters are known to influence the quality of AlN deposited on it. It was concluded that most critical parameters deciding platinum film quality are power, annealing temperature, and deposition pressure. By identifying the most critical parameters, we narrowed our subsequent two-level factorial optimization domain by a factor of 16. Furthermore, based on the Plackett-Burman screening, the optimal values of non-critical process parameters can be set by a judicious choice that would yield best results for one of the features of film quality without adversely affecting the other features.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90950606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937928
Ishan C. Ghosekar, G. C. Patil
The developments in the organic photovoltaics technology are mainly focused on increasing the power conversion efficiency (PCE), cost effective manufacturing and longer lifetime of the device. In this paper, effect of inserting the additional polymer layer between the hole transporting layer (HTL) and blended polymer: fullerene photoactive layer in conventional organic solar cell (OSC) has been demonstrated. The poly 3-hexylthiophene (P3HT) buffer layer inserted between HTL and P3HT:PCBM offers pure donor phase at the HTL interface which ultimately reduces the effect of vertical phase separation in conventional OSC. The experimental results shows that proposed buffered layer architecture has shown the improved power conversion efficiency (PCE) of OSC by $sim$35% over the conventional OSC structure. This improvement are mainly due to increase in photon absorption and improved charge collection at the HTL interface. In addition to this, the annealing dependent study on proposed buffered layer OSCs and conventional OSCs has been carried out. It has been found that annealing the active layer for longer duration has substantially reduced the PCE of the both the OSC architecture. The reason for this drop in PCE is mainly because of increase in donor-acceptor phase segregation and vertical phase separation in P3HT:PCBM. Although, in comparison to the conventional OSCs the PCE of proposed buffered layer OSCs has not plunges drastically which indicates the reduced impact of vertical phase separation in case of novel buffer layer architecture.
{"title":"Optimizing device efficiency of P3HT/P3HT:PCBM interlayer organic solar cell: Annealing dependent study","authors":"Ishan C. Ghosekar, G. C. Patil","doi":"10.1109/icee44586.2018.8937928","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937928","url":null,"abstract":"The developments in the organic photovoltaics technology are mainly focused on increasing the power conversion efficiency (PCE), cost effective manufacturing and longer lifetime of the device. In this paper, effect of inserting the additional polymer layer between the hole transporting layer (HTL) and blended polymer: fullerene photoactive layer in conventional organic solar cell (OSC) has been demonstrated. The poly 3-hexylthiophene (P3HT) buffer layer inserted between HTL and P3HT:PCBM offers pure donor phase at the HTL interface which ultimately reduces the effect of vertical phase separation in conventional OSC. The experimental results shows that proposed buffered layer architecture has shown the improved power conversion efficiency (PCE) of OSC by $sim$35% over the conventional OSC structure. This improvement are mainly due to increase in photon absorption and improved charge collection at the HTL interface. In addition to this, the annealing dependent study on proposed buffered layer OSCs and conventional OSCs has been carried out. It has been found that annealing the active layer for longer duration has substantially reduced the PCE of the both the OSC architecture. The reason for this drop in PCE is mainly because of increase in donor-acceptor phase segregation and vertical phase separation in P3HT:PCBM. Although, in comparison to the conventional OSCs the PCE of proposed buffered layer OSCs has not plunges drastically which indicates the reduced impact of vertical phase separation in case of novel buffer layer architecture.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"92 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76370287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937941
Vivek Raghuwanshi, Deepak Bharti, A. Mahato, Ishan Varun, S. P. Tiwari
We report the effect of varying the semiconductor:polymer blend ratio on the electrical performance and bias-stress stability of the organic field effect transistors (OFETs) with TIPS-Pentacene and polystyrene as semiconductor and polymer combination. Device performance was found to improve with increasing polymer content in the solution. Devices with 1:3 TIPS-Pentacene:polystyrene blend outperformed the other counterparts with high performance, and demonstrated least performance variation with regular 100 transfer measurement cycles. In addition, 1:3 blend devices have shown the least normalized drain current decay of $sim$ 8.5 % with the bias stress condition of VDS = VGS = -30 V for 2 h, as compared to the 1:1, 3:1 and neat devices with the decay of 15 %, 37 % and 71 % respectively. Additionally, a better recovery of electrical characteristics was observed in blend devices with larger polymer fractions from the deteriorating effects of gate bias stress.
{"title":"Effect of TIPS-Pentacene:Polystyrene Blend Ratio on Electrical Performance and Stability of Solution Processed Organic Field-Effect Transistors","authors":"Vivek Raghuwanshi, Deepak Bharti, A. Mahato, Ishan Varun, S. P. Tiwari","doi":"10.1109/icee44586.2018.8937941","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937941","url":null,"abstract":"We report the effect of varying the semiconductor:polymer blend ratio on the electrical performance and bias-stress stability of the organic field effect transistors (OFETs) with TIPS-Pentacene and polystyrene as semiconductor and polymer combination. Device performance was found to improve with increasing polymer content in the solution. Devices with 1:3 TIPS-Pentacene:polystyrene blend outperformed the other counterparts with high performance, and demonstrated least performance variation with regular 100 transfer measurement cycles. In addition, 1:3 blend devices have shown the least normalized drain current decay of $sim$ 8.5 % with the bias stress condition of VDS = VGS = -30 V for 2 h, as compared to the 1:1, 3:1 and neat devices with the decay of 15 %, 37 % and 71 % respectively. Additionally, a better recovery of electrical characteristics was observed in blend devices with larger polymer fractions from the deteriorating effects of gate bias stress.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"114 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76681010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937997
A. Debnath, Sreenidhi Turuvekre, N. Dasgupta, A. DasGupta
The gate leakage mechanism in AlGaN/GaN high electron mobility transistors (HEMT) is studied analytically using a charge-based model over a wide range of bias and temperature. Three distinct current mechanisms, Poole-Frenkel (PF), Defect assisted tunneling (DAT) and Thermionic emission (TE) are modeled. PF is the significant mechanism in reverse bias, while TE and DAT are the two dominant mechanisms in forward and low reverse bias respectively. This model is implemented in Verilog-A and rigorously validated with experimental data.
{"title":"Charge Based Compact Modeling of Gate Leakage Mechanism in AlGaN/GaN HEMTs","authors":"A. Debnath, Sreenidhi Turuvekre, N. Dasgupta, A. DasGupta","doi":"10.1109/icee44586.2018.8937997","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937997","url":null,"abstract":"The gate leakage mechanism in AlGaN/GaN high electron mobility transistors (HEMT) is studied analytically using a charge-based model over a wide range of bias and temperature. Three distinct current mechanisms, Poole-Frenkel (PF), Defect assisted tunneling (DAT) and Thermionic emission (TE) are modeled. PF is the significant mechanism in reverse bias, while TE and DAT are the two dominant mechanisms in forward and low reverse bias respectively. This model is implemented in Verilog-A and rigorously validated with experimental data.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"175 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75936046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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