Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937921
D. Singh, A. Dasgupta, A. Agarwal, Y. Chauhan
An incident flux based Monte Carlo particle simulation methodology has been developed which can be used to simulate any MOSFET. Incident flux Monte Carlo is a robust and intuitive method of device simulation because it can mimic the carrier transport in a physical device. The complete implementation has been done in an open source programming language called PYTHON. The simulations results are in good agreement with the existing results in the industry. The usability and advantage of our program have been shown by estimating backscattering coefficient, ballistic ratio and channel resistance of Silicon and GaAs quasi-ballistic devices. All the results that we have obtained can be used for better modeling of the electrical behavior of a quasi-ballistic device.
{"title":"Incident Flux Based Monte Carlo Simulation of Silicon and GaAs FETs in Quasi-Ballistic regime","authors":"D. Singh, A. Dasgupta, A. Agarwal, Y. Chauhan","doi":"10.1109/icee44586.2018.8937921","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937921","url":null,"abstract":"An incident flux based Monte Carlo particle simulation methodology has been developed which can be used to simulate any MOSFET. Incident flux Monte Carlo is a robust and intuitive method of device simulation because it can mimic the carrier transport in a physical device. The complete implementation has been done in an open source programming language called PYTHON. The simulations results are in good agreement with the existing results in the industry. The usability and advantage of our program have been shown by estimating backscattering coefficient, ballistic ratio and channel resistance of Silicon and GaAs quasi-ballistic devices. All the results that we have obtained can be used for better modeling of the electrical behavior of a quasi-ballistic device.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"72 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86312990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937922
Sumit Kumar, E. Abraham, S. Talukder, Praveen Kumar, R. Pratap
The recently developed technique of micro-nano pattern drawing by electrolithography process necessitates controlled probe-tip movement on a predefined path. Here we report development of a specific micropositioner system for drawing patterns at micrometer scale. Effect of different parameters on the patterns is studied. Probe-tip velocity and tip force are found to have major impact on the pattern-dimension.
{"title":"Micro Electrolithography System Development","authors":"Sumit Kumar, E. Abraham, S. Talukder, Praveen Kumar, R. Pratap","doi":"10.1109/icee44586.2018.8937922","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937922","url":null,"abstract":"The recently developed technique of micro-nano pattern drawing by electrolithography process necessitates controlled probe-tip movement on a predefined path. Here we report development of a specific micropositioner system for drawing patterns at micrometer scale. Effect of different parameters on the patterns is studied. Probe-tip velocity and tip force are found to have major impact on the pattern-dimension.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87808386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937877
B. Vikram, Roopa Prakash, K. Nagarjun, S. Selvaraja, V. Supradeepa
Increasing bandwidth demands necessitate the use of several carriers in wavelength division multiplexing. Conventionally, carrier wavelengths were generated by individual lasers which suffer from large area and power requirements with scaling of number of carriers. We demonstrate simultaneous generation of over 316 wavelengths in S, C and L bands from two lasers spaced 4 nm apart in the C-band. Electro-optic modulators initially scale each laser to 9 lines (in 20 dB bandwidth). The electro-optic frequency combs are power scaled to $sim 800$ mW and undergo cascaded four-wave mixing in highly nonlinear fiber to generate wavelengths in the three bands. The number of lines in 20 dB bandwidth in S, C and L bands are 88, 160 and 68 respectively. This system can also be used for RF arbitrary waveform generation.
{"title":"Simultaneous generation of laser sources in S, C and L bands through four-wave mixing of electro-optic frequency combs","authors":"B. Vikram, Roopa Prakash, K. Nagarjun, S. Selvaraja, V. Supradeepa","doi":"10.1109/icee44586.2018.8937877","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937877","url":null,"abstract":"Increasing bandwidth demands necessitate the use of several carriers in wavelength division multiplexing. Conventionally, carrier wavelengths were generated by individual lasers which suffer from large area and power requirements with scaling of number of carriers. We demonstrate simultaneous generation of over 316 wavelengths in S, C and L bands from two lasers spaced 4 nm apart in the C-band. Electro-optic modulators initially scale each laser to 9 lines (in 20 dB bandwidth). The electro-optic frequency combs are power scaled to $sim 800$ mW and undergo cascaded four-wave mixing in highly nonlinear fiber to generate wavelengths in the three bands. The number of lines in 20 dB bandwidth in S, C and L bands are 88, 160 and 68 respectively. This system can also be used for RF arbitrary waveform generation.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83657938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937900
S. Sadana, M. Gupta, R. Shankar, S. Singla, H. S. Jatana, U. Ganguly
Embedded non-volatile memory demand has increased manifolds in the recent time because it offers increased functionality and security for the systems. Microcontrollers, secure microprocessor need both advanced logic and NVM on the same die. Flash memory is the most mature memory used as Multi-Time Programmable Non-Volatile Memory (NVM). Traditionally Floating gate flash memory is the most commonly used flash technology where the charge is stored on the conducting floating gate. Floating gate memory is difficult to integrate in the logic process due to complex process integration and need 8-9 extra masks in the logic process to integrate flash technology. In this paper, we demonstrate Si3 N44 Charge Trap Flash (CTF) technology in 180nm CMOS fab. CTF is relatively easy to integrate and require few masks. The initial results show millisecond Program/Erase(P/E) speed, memory window of more than 1V after 1000 cycles and excellent retention with no bit flip after $250^{circ}mathrm{C}$ bake for 6 hours.
{"title":"Demonstration of Charge Trap Flash Bit-Cell in 180nm CMOS Logic Foundry","authors":"S. Sadana, M. Gupta, R. Shankar, S. Singla, H. S. Jatana, U. Ganguly","doi":"10.1109/icee44586.2018.8937900","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937900","url":null,"abstract":"Embedded non-volatile memory demand has increased manifolds in the recent time because it offers increased functionality and security for the systems. Microcontrollers, secure microprocessor need both advanced logic and NVM on the same die. Flash memory is the most mature memory used as Multi-Time Programmable Non-Volatile Memory (NVM). Traditionally Floating gate flash memory is the most commonly used flash technology where the charge is stored on the conducting floating gate. Floating gate memory is difficult to integrate in the logic process due to complex process integration and need 8-9 extra masks in the logic process to integrate flash technology. In this paper, we demonstrate Si3 N44 Charge Trap Flash (CTF) technology in 180nm CMOS fab. CTF is relatively easy to integrate and require few masks. The initial results show millisecond Program/Erase(P/E) speed, memory window of more than 1V after 1000 cycles and excellent retention with no bit flip after $250^{circ}mathrm{C}$ bake for 6 hours.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"59 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86963253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937967
S. M. H. Rizvi, B. Mazhari
This paper presents a simple methodology to incorporate the effects of diffusion into conventional space-charge-limited current (SCLC) of a zero built-in potential device. The resultant model is simple and a comparison between theoretical and experimental results are satisfactory.
{"title":"An Analytical Approach to Model the Effects of Diffusion in Space-Charge-Limited Current in Organic Semiconductor Films","authors":"S. M. H. Rizvi, B. Mazhari","doi":"10.1109/icee44586.2018.8937967","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937967","url":null,"abstract":"This paper presents a simple methodology to incorporate the effects of diffusion into conventional space-charge-limited current (SCLC) of a zero built-in potential device. The resultant model is simple and a comparison between theoretical and experimental results are satisfactory.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"113 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74892983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937969
K. Aditya, Rohit Saini, Manoj Kumar, Ramendra Singh, A. Dixit
In this paper, we have evaluated the single event upset (SEU) sensitivity of an embedded-DRAM (eDRAM) in presence of heavy-ion irradiation using 3-D TCAD simulations. The eDRAM with an access time of $sim 1$ ns is simulated using a calibrated 10.2 fF deep trench (DT) capacitor appended to a 14nm SOI-FinFET using mixed mode TCAD simulations. We have evaluated the impact of direction and position of the incident heavy-ion with linear energy transfer (LET) of 10 MeV-cm2/mg on the calibrated 14nm SOI-FinFET. The worst-case direction and position of heavy-ion are then used for evaluation of the SEU performance of eDRAM under heavy-ion irradiation. Our analysis is the first of its kind in analyzing the effect of heavy-ion irradiation on SEU sensitivity of eDRAM. We report that the critical LET for SEU to occur in the eDRAM is 500 MeV-cm2/mg which is 5 times better than the critical LET reported for SRAMs.
{"title":"SEU Sensitivity of a 14-nm SOI FinFET eDRAM Cell under Heavy-ion Irradiation","authors":"K. Aditya, Rohit Saini, Manoj Kumar, Ramendra Singh, A. Dixit","doi":"10.1109/icee44586.2018.8937969","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937969","url":null,"abstract":"In this paper, we have evaluated the single event upset (SEU) sensitivity of an embedded-DRAM (eDRAM) in presence of heavy-ion irradiation using 3-D TCAD simulations. The eDRAM with an access time of $sim 1$ ns is simulated using a calibrated 10.2 fF deep trench (DT) capacitor appended to a 14nm SOI-FinFET using mixed mode TCAD simulations. We have evaluated the impact of direction and position of the incident heavy-ion with linear energy transfer (LET) of 10 MeV-cm2/mg on the calibrated 14nm SOI-FinFET. The worst-case direction and position of heavy-ion are then used for evaluation of the SEU performance of eDRAM under heavy-ion irradiation. Our analysis is the first of its kind in analyzing the effect of heavy-ion irradiation on SEU sensitivity of eDRAM. We report that the critical LET for SEU to occur in the eDRAM is 500 MeV-cm2/mg which is 5 times better than the critical LET reported for SRAMs.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"148 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76701325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937910
Shalini Tomar, P. Rastogi, B. Bhadoria, S. Bhowmick, A. Agarwal, Y. Chauhan
The promising thermoelectric properties of two-dimensional (2D) materials, owing to their appropriate combination of electrical and thermal transport properties has broaden their application in thermoelectric devices. Recently, the successful exfoliation of monolayer chromium tri-iodide CrI3, having robust intrinsic magnetism, has motivated us to investigate its thermoelectric properties in ferromagnetic (FM) and anti-ferromagnetic (AFM) states. Using density functional theory in addition with Boltzmann transport theory, we have calculated the band-structure, density of states, electrical and thermal conductivities, Seebeck coefficient and power factor for monolayer CrI3 in FM and AFM states. We show that in both magnetic states, CrI3 has an electrical conductivity $(sigma /tau approx 10^{19}, Omega^{-1}m^{-1}s^{-1})$ comparable to graphene. For both magnetic states, no variation is observed in electrical and thermal conductivity for temperature less than 500 K. However, both conductivities is observed to increase significantly with further increase in temperature till 800 K. Interestingly, both conductivities in FM state are 10 times higher than AFM state, while the power factor for FM state is higher over AFM state, and hence indicates a good thermoelectric performance in FM state of CrI3 monolayer.
{"title":"Thermoelectric Properties of CrI3 Monolayer","authors":"Shalini Tomar, P. Rastogi, B. Bhadoria, S. Bhowmick, A. Agarwal, Y. Chauhan","doi":"10.1109/icee44586.2018.8937910","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937910","url":null,"abstract":"The promising thermoelectric properties of two-dimensional (2D) materials, owing to their appropriate combination of electrical and thermal transport properties has broaden their application in thermoelectric devices. Recently, the successful exfoliation of monolayer chromium tri-iodide CrI3, having robust intrinsic magnetism, has motivated us to investigate its thermoelectric properties in ferromagnetic (FM) and anti-ferromagnetic (AFM) states. Using density functional theory in addition with Boltzmann transport theory, we have calculated the band-structure, density of states, electrical and thermal conductivities, Seebeck coefficient and power factor for monolayer CrI3 in FM and AFM states. We show that in both magnetic states, CrI3 has an electrical conductivity $(sigma /tau approx 10^{19}, Omega^{-1}m^{-1}s^{-1})$ comparable to graphene. For both magnetic states, no variation is observed in electrical and thermal conductivity for temperature less than 500 K. However, both conductivities is observed to increase significantly with further increase in temperature till 800 K. Interestingly, both conductivities in FM state are 10 times higher than AFM state, while the power factor for FM state is higher over AFM state, and hence indicates a good thermoelectric performance in FM state of CrI3 monolayer.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"17 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73155947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937939
Pankaj Kumar, Jithin M. Arvind, S. Mohan, S. Avasthi
Here we report experimentally determined diffusivity of Fe in TiN diffusion barrier layer. TiN films were deposited on mild steel substrates at room temperature. The samples were annealed at high temperatures in view of processes requiring high temperature such as GaAs thin film solar cells. SIMS was used to extract the diffusion coefficient for bulk diffusion and grain boundary diffusion. At 700°C, the effective diffusion coefficient was found to be 1.7 nm2/sec.
{"title":"SIMS characterization of TiN diffusion barrier layer on steel substrate","authors":"Pankaj Kumar, Jithin M. Arvind, S. Mohan, S. Avasthi","doi":"10.1109/icee44586.2018.8937939","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937939","url":null,"abstract":"Here we report experimentally determined diffusivity of Fe in TiN diffusion barrier layer. TiN films were deposited on mild steel substrates at room temperature. The samples were annealed at high temperatures in view of processes requiring high temperature such as GaAs thin film solar cells. SIMS was used to extract the diffusion coefficient for bulk diffusion and grain boundary diffusion. At 700°C, the effective diffusion coefficient was found to be 1.7 nm2/sec.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73692431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937888
R. Yadav, Suren Patwardhan, Ranjana J. Shourie, M. Aslam, Balasubramaniam Kavaipatti, D. Kabra, A. Antony
Inorganic materials for the charge transport layer in solar cells are increasingly being investigated. Non-stoichiometric nickel oxide (NiOX), owing to its larger band gap and stability is a promising hole transport material. In this work, we critically examine the electronic structure and hole-selectivity of NiOX films at various oxygen partial pressure (pO2) values during radio frequency (RF) sputtering. At pO2 of 0.25, a maximum in the Ni3+/Ni2+ ratio (7.09) is obtained. At this ratio, the band alignment of NiOX with that of methyl-ammonium lead iodide (MAPI) is observed to be most suitable. There is no misalignment of the valence band edges while conduction band edges separated by about 1 eV. Initial results of the MAPI perovskite solar cell with this optimized NiOX as hole transport layer showed 7.7% efficiency. This result is promising to take the work further for enhancement of efficiency as well as for in-depth engineering of the energy bands of NiOX.
{"title":"Tuning the band structure of nickel oxide for efficient hole extraction in perovskite solar cells","authors":"R. Yadav, Suren Patwardhan, Ranjana J. Shourie, M. Aslam, Balasubramaniam Kavaipatti, D. Kabra, A. Antony","doi":"10.1109/icee44586.2018.8937888","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937888","url":null,"abstract":"Inorganic materials for the charge transport layer in solar cells are increasingly being investigated. Non-stoichiometric nickel oxide (NiOX), owing to its larger band gap and stability is a promising hole transport material. In this work, we critically examine the electronic structure and hole-selectivity of NiOX films at various oxygen partial pressure (pO2) values during radio frequency (RF) sputtering. At pO2 of 0.25, a maximum in the Ni3+/Ni2+ ratio (7.09) is obtained. At this ratio, the band alignment of NiOX with that of methyl-ammonium lead iodide (MAPI) is observed to be most suitable. There is no misalignment of the valence band edges while conduction band edges separated by about 1 eV. Initial results of the MAPI perovskite solar cell with this optimized NiOX as hole transport layer showed 7.7% efficiency. This result is promising to take the work further for enhancement of efficiency as well as for in-depth engineering of the energy bands of NiOX.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"16 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81142172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/icee44586.2018.8937923
A. Gaidhane, G. Pahwa, A. Verma, Y. Chauhan
A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper. We propose an explicit continuous formulation of the drain current in terms of an intermediate parameter which is solved using a compact modeling approach. The proposed model captures a wide range of ferroelectric material parameter variations of a DG-NCFET in the non-hysteretic regime of operation. We implement our compact model in Verilog-A code and validate extensively with TCAD simulation results. We test the transient capability of the proposed model by simulating NCFET based 15-stage ring oscillator in a commercial circuit simulator.
{"title":"Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor","authors":"A. Gaidhane, G. Pahwa, A. Verma, Y. Chauhan","doi":"10.1109/icee44586.2018.8937923","DOIUrl":"https://doi.org/10.1109/icee44586.2018.8937923","url":null,"abstract":"A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper. We propose an explicit continuous formulation of the drain current in terms of an intermediate parameter which is solved using a compact modeling approach. The proposed model captures a wide range of ferroelectric material parameter variations of a DG-NCFET in the non-hysteretic regime of operation. We implement our compact model in Verilog-A code and validate extensively with TCAD simulation results. We test the transient capability of the proposed model by simulating NCFET based 15-stage ring oscillator in a commercial circuit simulator.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"69 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84230882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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