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Technology challenges and enablers to extend Cu metallization to beyond 7 nm node 将铜金属化扩展到7nm以上节点的技术挑战和推动因素
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776573
T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran
Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.
采用pvd回流通过co自形成势垒(tCoSFB)的铜互连的电迁移(EM)和TDDB可靠性达到了7纳米BEOL的要求规格。由此产生的Cu EM寿命比具有标准鳞片屏障/润湿层的Cu互连长2000倍。这种tCoSFB Cu EM和TDDB的可靠性性能相当于纯钴金属互连,但即使在30nm间距尺寸下,线路电阻也降低了50%。然而,提高电磁可靠性的pvd -回流铜籽的退火工艺导致铜在双damascene线端过孔处聚集,导致过孔链产率较差。解决这种几何敏感的过孔填充问题被认为是将铜的可制造性扩展到7纳米及以上的关键。我们提出并展示了通过预填充的CVD Co作为潜在解决方案的Cu/tCoSFB金属化的初步数据。
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引用次数: 1
Inference of Long-Short Term Memory networks at software-equivalent accuracy using 2.5M analog Phase Change Memory devices 使用2.5M模拟相变存储器器件在软件等效精度下推断长短期记忆网络
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776519
H. Tsai, S. Ambrogio, C. Mackin, P. Narayanan, R. Shelby, K. Rocki, A. Chen, G. Burr
We report accuracy for forward inference of long-short-term-memory (LSTM) networks using weights programmed into the conductances of $> 2.5text{M}$ phase-change memory (PCM) devices. We demonstrate strategies for software weight-mapping and programming of hardware analog conductances that provide accurate weight programming despite significant device variability. Inference accuracy very close to software-model baselines is achieved on several language modeling tasks.
我们报告了长短期记忆(LSTM)网络前向推理的准确性,使用将权重编程到$> 2.5text{M}$相变记忆(PCM)器件的电导中。我们演示了硬件模拟电导的软件权重映射和编程策略,这些策略可以在显著的器件可变性下提供准确的权重编程。在几个语言建模任务上,实现了非常接近软件模型基线的推理精度。
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引用次数: 26
Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications 分栅ffet (sg - ffet)与动态记忆窗调制非易失性记忆和神经形态应用
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776555
V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(text{A}_{text{FE}}/text{A}_{text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $text{A}_{text{FE}}/text{A}_{text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(text{V}_{text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $text{V}_{text{Write}}(=1.85text{V})$ and 59.5% reduction in write energy at fixed $text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $text{I}_{text{Read}_{-}text{1}/text{I}_{text{Read}_{-}0}}(=8.6text{E}6)$ at fixed $text{V}_{text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $text{V}_{text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.
在这项工作中,我们提出了一种新型的分栅ffet (SG-FeFET),具有两个独立的外部栅极,可以动态调制非易失性存储器和神经形态应用的记忆窗口(MW)。在读取过程中,只打开一个栅极,降低了铁电层与绝缘子层的面积比$(text{A}_{text{FE}}/text{A}_{text{IL}})$,增加了MW和读取电流比$(text{I}_{text{read}_{-}1}/text{I}_{text{read}_{-}0})$。在写操作(程序/擦除)过程中,两个门都打开以增加$text{A}_{text{FE}}/text{A}_{text{IL}}$,从而降低MW,从而导致较低的写电压$(text{V}_{text{write}})$。与FeFET相比,SG-FeFET(1)显示$text{V}_{text{Write}}(=1.85text{V})$和固定$text{I}_{text{Read}_{-}1}/text{Read}}{-}0} $的写入能量降低了59.5%;(2)$显示较低的读取能量(-11.3%)和较高的$text{I}_{text{Read}} {-}1}/text{I}} {text{Read}} {-}0}}(=8.6text{E}6)$在固定$text{V}} {text{Write}} $允许随机访问,消除半选择干扰;(4)由于低$text{V}_{text{Write}}$和电荷捕获,保持更高的续航时间。sg - ffet作为突触器件,在增强和抑制过程中也表现出良好的对称性和线性性。
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引用次数: 15
Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash 超薄体(Tsi~3nm)器件的优势提升3D NAND闪存的存储窗口
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776483
H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.
采用极薄体(ETB, Tsi=3nm)器件的优势已在3D NAND闪存测试芯片中得到验证。对于使用ETB多晶硅的器件,观察到净P/E存储器窗口增益为>1.3V。这种可观的增益可以用“量子约束”来解释,它提高了有效的Si带隙,从而降低了隧道势垒的高度。仿真结果表明,当Tsi=3nm时,电子和空穴的等效势垒高度分别降低了~0.16eV和0.07eV。同时,极薄的多晶硅通道可以将S.S.提高到接近250mV/dec,接近体块2D Flash器件。然而,当Tsi=3nm时,由于更大的有效质量或更高的接触电阻,Idsat仅退化到160nA。降低的Idsat可以通过较低的Isense<30nA进行页面缓冲电路调优。超薄的机身显著降低了随机电报噪声(RTN),并且在MLC/TLC操作中显示出更紧密的程序验证(PV)分布。
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引用次数: 6
1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS 碳纳米管FET CMOS中的1kbit 6T SRAM阵列
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776563
P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker
We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.
我们实验展示了基于碳纳米管场效应晶体管(cnfet)的第一个静态随机存取存储器(SRAM)阵列。我们展示了用CNFET CMOS(共6,144个p型和n型CNFET)制造的全1 Kbit 6晶体管(6T) SRAM阵列,所有1,024个单元都能正常工作,无需任何单个定制。我们通过向Kbit阵列写入和读取多个模式来展示稳健的操作,并表征单细胞SRAM可变性(写入和读取边距)和细胞的重复循环。由于低温beol兼容处理,CNFET SRAM为数字系统带来了新的机会,因为:(1)CNFET SRAM可以直接在计算逻辑上制造,(2)埋地电源轨(即,正如我们的演示中,电源轨在FET下面制造)可以实现更小面积的SRAM布局。
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引用次数: 11
Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network 极紧凑的STT-MRAM神经元:通往全自旋人工深度神经网络的途径
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776569
Ming-Hung Wu, Ming-Chun Hong, Chih-Cheng Chang, P. Sahu, Jeng-Hua Wei, Heng-Yuan Lee, Shyh-Shyuan Shcu, T. Hou
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
基于磁隧道结的回跳振荡,开发了迄今为止报道的最紧凑的模拟积分-放电神经元。这种新颖的设备是独一无二的,因为它同时执行许多基本的神经功能,包括电流集成、电压尖峰产生、状态复位和4位精度。该装置本身也是一个随机二元突触,从而简化了紧凑的全自旋神经网络的实现,具有高精度的在线训练。
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引用次数: 13
7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability 7nm移动SoC和5G平台技术与设计共同开发,用于PPA和可制造性
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776511
M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram
We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10text{Gbps}$ connectivity.
我们报告高通骁龙SDM855移动SoC和全球首个商用5G平台,采用业界领先的7nm FINFET技术。由于采用双多间距工艺集成的新设计架构,SDM855的CPU性能比上一代提高了30 %。通过工艺和设计的共同开发,实现了低电压运行和功耗的紧密分布,为移动和人工智能应用提供了高性能和低功耗的解决方案。通过两年的工艺改进,扩展7nm技术可以在不改变设计规则的情况下降低高达50mV的CPU Vmin,这为具有> 10text{Gbps}$连接的集成5G移动平台铺平了道路。
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引用次数: 3
Device-, Circuit- & Block-level evaluation of CFET in a 4 track library 器件级、电路级和块级的四磁道库中CFET的评估
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776513
P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta
The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5text{e}-10Omega.text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.
互补FET (cet)的结构是NMOS堆叠在PMOS之上,固有地产生标准单元和SRAM单元,其布局面积比FinFET小25%,引脚密度高25%,布线灵活性高2倍,但总体有源占地面积相同。此外,基于先进的建模,我们的工作表明,4磁道CFET可以匹配甚至优于5磁道FinFET;无需将S/D接触电阻率降低到$5text{e}-10Omega。text{cm}^{2}$或将通道应力提高到2GPa。电路级功率性能区域的所有增益都保持在块级,使4磁道CFET成为N3和N2技术的合适候选人。关键词:CFET,缩放,S/D工程,pi栅极
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引用次数: 21
GaN HEMTs with Breakdown Voltage of 2200 V Realized on a 200 mm GaN-on-Insulator(GNOI)-on-Si Wafer 在200 mm的绝缘体上氮化镓硅片上实现了击穿电压为2200 V的氮化镓hemt
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776522
Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald
GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO2/Si substrate. HEMTs were fabricated with measured $BV_{text{off}}$ much larger than those on GaN-on-Si. Record high $BV text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {mu m}$.
GaN-on- si已显示出其在下一代电力电子应用中的巨大潜力,然而,由于大尺寸晶圆上GaN涂层厚度的限制,在提高击穿电压(BV_{text{off}})方面仍然存在挑战。在这项工作中,我们提出了一种GaN-on-Insulator (GNOI)-on-Si结构来解决这个问题。通过去除GaN-on-Si晶片的原始Si衬底并粘合到新的SiO2/Si衬底上,制备了200 mm的gni -on-Si晶片。测量到的$BV_{text{off}}$要比GaN-on-Si上的hemt大得多。在200 mm的gni -on- si晶片上,具有3.2 { μ m}$的薄GaN涂层的hemt实现了创纪录的高达2200 V的$BV text{off}$和高达1.87 GW/cm2的高品质因数(FOM) $BV_{off^2}/R_{text{on, sp}}$。
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引用次数: 1
Monolithic 3D+ -IC based Reconfigurable Compute-in-Memory SRAM Macro 基于单片3D+ ic的可重构内存计算SRAM宏
Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776506
S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan
This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $text{V}_{text{dd}min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.
本文提出了第一个单片3D双层可重构SRAM宏,能够执行多个内存中计算(CiM)任务作为数据读出的一部分。SRAM采用低成本的基于FinFET的3D+-IC制造,提供从两层读取并发数据和从第二层写入数据的速度为0.4V $text{V}_{text{dd}min}$与连续布尔运算的近内存计算相比,计算延迟提高了12.8倍。
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引用次数: 9
期刊
2019 Symposium on VLSI Technology
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