Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776573
T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran
Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.
采用pvd回流通过co自形成势垒(tCoSFB)的铜互连的电迁移(EM)和TDDB可靠性达到了7纳米BEOL的要求规格。由此产生的Cu EM寿命比具有标准鳞片屏障/润湿层的Cu互连长2000倍。这种tCoSFB Cu EM和TDDB的可靠性性能相当于纯钴金属互连，但即使在30nm间距尺寸下，线路电阻也降低了50%。然而，提高电磁可靠性的pvd -回流铜籽的退火工艺导致铜在双damascene线端过孔处聚集，导致过孔链产率较差。解决这种几何敏感的过孔填充问题被认为是将铜的可制造性扩展到7纳米及以上的关键。我们提出并展示了通过预填充的CVD Co作为潜在解决方案的Cu/tCoSFB金属化的初步数据。
{"title":"Technology challenges and enablers to extend Cu metallization to beyond 7 nm node","authors":"T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran","doi":"10.23919/VLSIT.2019.8776573","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776573","url":null,"abstract":"Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"51 1","pages":"T18-T19"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73962392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776555
V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(text{A}_{text{FE}}/text{A}_{text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $text{A}_{text{FE}}/text{A}_{text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(text{V}_{text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $text{V}_{text{Write}}(=1.85text{V})$ and 59.5% reduction in write energy at fixed $text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $text{I}_{text{Read}_{-}text{1}/text{I}_{text{Read}_{-}0}}(=8.6text{E}6)$ at fixed $text{V}_{text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $text{V}_{text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.
{"title":"Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications","authors":"V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su","doi":"10.23919/VLSIT.2019.8776555","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776555","url":null,"abstract":"In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(text{A}_{text{FE}}/text{A}_{text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $text{A}_{text{FE}}/text{A}_{text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(text{V}_{text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $text{V}_{text{Write}}(=1.85text{V})$ and 59.5% reduction in write energy at fixed $text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $text{I}_{text{Read}_{-}text{1}/text{I}_{text{Read}_{-}0}}(=8.6text{E}6)$ at fixed $text{V}_{text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $text{V}_{text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"68 1","pages":"T134-T135"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82492259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776519
H. Tsai, S. Ambrogio, C. Mackin, P. Narayanan, R. Shelby, K. Rocki, A. Chen, G. Burr
We report accuracy for forward inference of long-short-term-memory (LSTM) networks using weights programmed into the conductances of $> 2.5text{M}$ phase-change memory (PCM) devices. We demonstrate strategies for software weight-mapping and programming of hardware analog conductances that provide accurate weight programming despite significant device variability. Inference accuracy very close to software-model baselines is achieved on several language modeling tasks.
{"title":"Inference of Long-Short Term Memory networks at software-equivalent accuracy using 2.5M analog Phase Change Memory devices","authors":"H. Tsai, S. Ambrogio, C. Mackin, P. Narayanan, R. Shelby, K. Rocki, A. Chen, G. Burr","doi":"10.23919/VLSIT.2019.8776519","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776519","url":null,"abstract":"We report accuracy for forward inference of long-short-term-memory (LSTM) networks using weights programmed into the conductances of $> 2.5text{M}$ phase-change memory (PCM) devices. We demonstrate strategies for software weight-mapping and programming of hardware analog conductances that provide accurate weight programming despite significant device variability. Inference accuracy very close to software-model baselines is achieved on several language modeling tasks.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"47 31 1","pages":"T82-T83"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80623357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776483
H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.
{"title":"Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash","authors":"H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.23919/VLSIT.2019.8776483","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776483","url":null,"abstract":"The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"31 1","pages":"T210-T211"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82525364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776511
M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram
We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10text{Gbps}$ connectivity.
{"title":"7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability","authors":"M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram","doi":"10.23919/VLSIT.2019.8776511","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776511","url":null,"abstract":"We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10text{Gbps}$ connectivity.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"40 1","pages":"T104-T105"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74797451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776569
Ming-Hung Wu, Ming-Chun Hong, Chih-Cheng Chang, P. Sahu, Jeng-Hua Wei, Heng-Yuan Lee, Shyh-Shyuan Shcu, T. Hou
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
{"title":"Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network","authors":"Ming-Hung Wu, Ming-Chun Hong, Chih-Cheng Chang, P. Sahu, Jeng-Hua Wei, Heng-Yuan Lee, Shyh-Shyuan Shcu, T. Hou","doi":"10.23919/VLSIT.2019.8776569","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776569","url":null,"abstract":"This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"15 1","pages":"T34-T35"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77614543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776563
P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker
We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.
{"title":"1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS","authors":"P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker","doi":"10.23919/VLSIT.2019.8776563","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776563","url":null,"abstract":"We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T54-T55"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77582839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776539
Kaizhen Han, Ying Wu, Y. Huang, Shengqiang Xu, Annie Kumar, E. Kong, Yuye Kang, Jishen Zhang, Chengkuan Wang, Haiwen Xu, Chen Sun, X. Gong
For the first time, complementary FinFETs and complementary tunneling FinFETs (TFFETs), with fin width $(W_{Fin})$ of 20 nm and fin height $(H_{{fin}})$ of 50 nm, were co-integrated on the same substrate, enabled by the formation of high-quality GeSn-on-insulator (GeSnOI) substrate with 200 mm wafer size. Decent electrical characteristics were realized for both GeSn n-and p-channel FinFETs and TFFETs. We also performed simulation studies to show the promise of the GeSnOI platform, which is not only able to suppress the off-state leakage current and improve the $I_{on}/I_{off}$ ratio of tunneling FETs, but can also provide the powerful flexibility of using a back bias to achieve superior electrical characteristics beyond the benefits of incorporating Sn into Ge.
通过形成200 mm晶圆尺寸的高质量GeSnOI衬底，首次将翅片宽度$(W_{fin})$为20 nm，翅片高度$(H_{{fin}})$为50 nm的互补finfet和互补隧道finfet (tffet)在同一衬底上共集成。GeSn n沟道和p沟道finfet以及tffet均实现了良好的电特性。我们还进行了仿真研究，以显示GeSnOI平台的前景，该平台不仅能够抑制关态泄漏电流，提高隧道fet的$ i {on}/ $ i {off}}比值，而且还可以提供强大的灵活性，使用反偏置来实现超越将Sn加入Ge的好处的优越电气特性。
{"title":"First Demonstration of Complementary FinFETs and Tunneling FinFETs Co-Integrated on a 200 mm GeSnOI Substrate: A Pathway towards Future Hybrid Nano-electronics Systems","authors":"Kaizhen Han, Ying Wu, Y. Huang, Shengqiang Xu, Annie Kumar, E. Kong, Yuye Kang, Jishen Zhang, Chengkuan Wang, Haiwen Xu, Chen Sun, X. Gong","doi":"10.23919/VLSIT.2019.8776539","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776539","url":null,"abstract":"For the first time, complementary FinFETs and complementary tunneling FinFETs (TFFETs), with fin width $(W_{Fin})$ of 20 nm and fin height $(H_{{fin}})$ of 50 nm, were co-integrated on the same substrate, enabled by the formation of high-quality GeSn-on-insulator (GeSnOI) substrate with 200 mm wafer size. Decent electrical characteristics were realized for both GeSn n-and p-channel FinFETs and TFFETs. We also performed simulation studies to show the promise of the GeSnOI platform, which is not only able to suppress the off-state leakage current and improve the $I_{on}/I_{off}$ ratio of tunneling FETs, but can also provide the powerful flexibility of using a back bias to achieve superior electrical characteristics beyond the benefits of incorporating Sn into Ge.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"74 1","pages":"T182-T183"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86916863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776500
R. Berdan, T. Marukame, S. Kabuyanagi, K. Ota, M. Saitoh, S. Fujii, J. Deguchi, Y. Nishi
Building compact and efficient reinforcement learning (RL) systems for mobile deployment requires departure from the von-Neumann computing architecture and embracing novel in-memory computing, and local learning paradigms. We exploit nano-scale ferroelectric tunnel junction (FTJ) memristors with inherent analogue stochastic switching arranged in selector-less crossbars to demonstrate an analogue in-memory RL system, which, via a hardware-friendly algorithm, is capable of learning behavior policies. We show that commonly undesirable stochastic conductance switching is actually, in moderation, a beneficial property which promotes policy finding via a process akin to random search. We experimentally demonstrate path-finding based on reinforcement, and solve a standard control problem of balancing a pole on a cart via simulation, outperforming similar deterministic RL systems.
{"title":"In-memory Reinforcement Learning with Moderately-Stochastic Conductance Switching of Ferroelectric Tunnel Junctions","authors":"R. Berdan, T. Marukame, S. Kabuyanagi, K. Ota, M. Saitoh, S. Fujii, J. Deguchi, Y. Nishi","doi":"10.23919/VLSIT.2019.8776500","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776500","url":null,"abstract":"Building compact and efficient reinforcement learning (RL) systems for mobile deployment requires departure from the von-Neumann computing architecture and embracing novel in-memory computing, and local learning paradigms. We exploit nano-scale ferroelectric tunnel junction (FTJ) memristors with inherent analogue stochastic switching arranged in selector-less crossbars to demonstrate an analogue in-memory RL system, which, via a hardware-friendly algorithm, is capable of learning behavior policies. We show that commonly undesirable stochastic conductance switching is actually, in moderation, a beneficial property which promotes policy finding via a process akin to random search. We experimentally demonstrate path-finding based on reinforcement, and solve a standard control problem of balancing a pole on a cart via simulation, outperforming similar deterministic RL systems.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"35 1","pages":"T22-T23"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84221163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776572
C. Fu, H. Lue, T. Hsu, Wei-Chen Chen, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
For the first time, we've fabricated a confined nitride (SiN) trapping layer device for 3D NAND Flash and demonstrated excellent post-cycling retention performances. The key process step is to develop a uniform sidewall lateral recess in the 3D stack, followed by a SiN pull back process to isolate the SiN trapping layer in a self-aligned way. Excellent retention with only ~600mV shift of charge loss (out of initial 7V window) after 125C 1-week high-temp baking for a post 1K cycled device was obtained. It is far superior to the control sample without confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass> 100 years at 60C, and is even longer at room temperature. The device has potential to meet the low-cost long-retention archive memory applications.
{"title":"A Novel Confined Nitride-Trapping Layer Device for 3D NAND Flash with Robust Retention Performances","authors":"C. Fu, H. Lue, T. Hsu, Wei-Chen Chen, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.23919/VLSIT.2019.8776572","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776572","url":null,"abstract":"For the first time, we've fabricated a confined nitride (SiN) trapping layer device for 3D NAND Flash and demonstrated excellent post-cycling retention performances. The key process step is to develop a uniform sidewall lateral recess in the 3D stack, followed by a SiN pull back process to isolate the SiN trapping layer in a self-aligned way. Excellent retention with only ~600mV shift of charge loss (out of initial 7V window) after 125C 1-week high-temp baking for a post 1K cycled device was obtained. It is far superior to the control sample without confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass> 100 years at 60C, and is even longer at room temperature. The device has potential to meet the low-cost long-retention archive memory applications.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"29 1","pages":"T212-T213"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78854618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：