Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531857
Jamal Alotaibi, Lubna K. Alazzawi
The Internet of Vehicles (IoV) is a decentralized network that enables data sharing between connected vehicles and vehicular ad hoc networks (VANETs). However, since different IoV applications have varied Quality-of-Service (QoS) requirements, creating an effective solution to cope with big data in IoV is challenging. Fog computing addresses the inherent flaw of centralized data processing in cloud computing by offloading computationally-intensive tasks to closely located fog nodes. Also, with an increasing number of vehicles under the IoV architecture, new challenges and requirements are emerging such as scalability, efficient resource usage, and secure communication. In this paper, we address the problems of load-balancing and secure communication in SDN-enabled and fog-based IoV networks. Our methodology (SaFIoV) efficiently distributes tasks in the fog-to-fog and vehicles-to-fog layers using reinforcement learning (RL) methods. Moreover, powered by Blockchain technology, our method provides secure communication. The result of our experimental study shows that SaFIoV can efficiently utilize the available resources while avoiding congestion and minimizing latency in the IoV network.
{"title":"SaFIoV: A Secure and Fast Communication in Fog-based Internet-of-Vehicles using SDN and Blockchain","authors":"Jamal Alotaibi, Lubna K. Alazzawi","doi":"10.1109/MWSCAS47672.2021.9531857","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531857","url":null,"abstract":"The Internet of Vehicles (IoV) is a decentralized network that enables data sharing between connected vehicles and vehicular ad hoc networks (VANETs). However, since different IoV applications have varied Quality-of-Service (QoS) requirements, creating an effective solution to cope with big data in IoV is challenging. Fog computing addresses the inherent flaw of centralized data processing in cloud computing by offloading computationally-intensive tasks to closely located fog nodes. Also, with an increasing number of vehicles under the IoV architecture, new challenges and requirements are emerging such as scalability, efficient resource usage, and secure communication. In this paper, we address the problems of load-balancing and secure communication in SDN-enabled and fog-based IoV networks. Our methodology (SaFIoV) efficiently distributes tasks in the fog-to-fog and vehicles-to-fog layers using reinforcement learning (RL) methods. Moreover, powered by Blockchain technology, our method provides secure communication. The result of our experimental study shows that SaFIoV can efficiently utilize the available resources while avoiding congestion and minimizing latency in the IoV network.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"107 12","pages":"334-339"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72628585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531796
Jingbo Zhou, Xinmiao Zhang
Logic locking is necessary for protecting intellectual property. Although logic-locking schemes have been proposed to resist the powerful satisfiability (SAT)-based attack, many of them are subject to removal attacks, which identify the logic- locking block and replace its output by the correct signal, so the circuit would function correctly without the right key. In order to prevent removal attacks, the stripped functional logic locking-Hamming distance (SFLL-HD) scheme and its variations corrupt the original circuit and add a logic-locking block to correct the errors. The high-complexity HD checker can be also replaced by the Cascaded(CAS)-lock block. This paper proposes a new low-complexity logic-locking scheme inspired by the Generalized(G)-Anti-SAT block. By relaxing the constraint of the G-Anti-SAT design in the SFLL setting, our new logic-locking scheme reduces the logic complexity by around 37% compared to the M-CAS block with similar resistance to the SAT and removal attacks. Additionally, unlike the SFLL-HD and Mirrored (M)- CAS schemes, the proposed logic-locking block can use a large variation of functions. This makes existing or potential attacks utilizing properties of the logic function impossible.
{"title":"A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks","authors":"Jingbo Zhou, Xinmiao Zhang","doi":"10.1109/MWSCAS47672.2021.9531796","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531796","url":null,"abstract":"Logic locking is necessary for protecting intellectual property. Although logic-locking schemes have been proposed to resist the powerful satisfiability (SAT)-based attack, many of them are subject to removal attacks, which identify the logic- locking block and replace its output by the correct signal, so the circuit would function correctly without the right key. In order to prevent removal attacks, the stripped functional logic locking-Hamming distance (SFLL-HD) scheme and its variations corrupt the original circuit and add a logic-locking block to correct the errors. The high-complexity HD checker can be also replaced by the Cascaded(CAS)-lock block. This paper proposes a new low-complexity logic-locking scheme inspired by the Generalized(G)-Anti-SAT block. By relaxing the constraint of the G-Anti-SAT design in the SFLL setting, our new logic-locking scheme reduces the logic complexity by around 37% compared to the M-CAS block with similar resistance to the SAT and removal attacks. Additionally, unlike the SFLL-HD and Mirrored (M)- CAS schemes, the proposed logic-locking block can use a large variation of functions. This makes existing or potential attacks utilizing properties of the logic function impossible.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"869-873"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75584405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531824
Rajath Bindiganavile, A. Tajalli
A differential ring Voltage Controlled Oscillator (VCO) with a controllable KVCO is introduced. The capability to control KVCO enables post-fabrication calibration of VCO gain, in order to reduce its vulnerability to Process, Voltage, and Temperature (PVT) variations. Performance of the proposed circuit topology, and its application in design of Phase-Locked Loops (PLLs), are analyzed. The gain of the proposed VCO can be tuned over ±20% of its nominal value. Simulations show that phase noise of the proposed circuit varies by less than 2 dBc/Hz compared to the conventional topology, at an offset frequency of 10 MHz, over its entire KVCO tuning range.
{"title":"A Controllable KVCO Ring VCO Topology","authors":"Rajath Bindiganavile, A. Tajalli","doi":"10.1109/MWSCAS47672.2021.9531824","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531824","url":null,"abstract":"A differential ring Voltage Controlled Oscillator (VCO) with a controllable KVCO is introduced. The capability to control KVCO enables post-fabrication calibration of VCO gain, in order to reduce its vulnerability to Process, Voltage, and Temperature (PVT) variations. Performance of the proposed circuit topology, and its application in design of Phase-Locked Loops (PLLs), are analyzed. The gain of the proposed VCO can be tuned over ±20% of its nominal value. Simulations show that phase noise of the proposed circuit varies by less than 2 dBc/Hz compared to the conventional topology, at an offset frequency of 10 MHz, over its entire KVCO tuning range.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"210 1","pages":"732-736"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73224908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531682
Muhammad Hataba, Ahmed B. T. Sherif, Reem Elkhouly
Cars are becoming smarter every day. They are being equipped with sensors, communications interfaces, and more powerful processing capabilities. The primary purpose was to enable these cars to drive themselves without any human interventions and become so-called Autonomous Vehicles (AVs). But why stop there, why not harness all that computing power for a greater collective purpose. That’s how the idea of Autonomous Vehicular Cloud Computing (AVCC) was born. Nonetheless, this is not a trivial task, the mobile and dynamic nature of vehicles poses a significant challenge in the formation and management of this cloud computing model and yet a more substantial challenge in terms of security and privacy of all the parties involved in this system. In this paper, we focus on protecting software running on AVCC. We use dynamic obfuscated compilation to complicate programs’ execution paths and hinder information leakage via side channels attacks. Relying on compilers offers advantages, such as the independence of architecture and support for a variety high-level programming languages and application simplicity with minimal set-up cost. Here, we introduce our system in the realm of ARM processor, which power AVCC. Then, we present execution statistics for simple standard programs. The results show tangible timing variations in diversified code versions for the same program, which may disrupt side-channel attacks.
{"title":"A Proposed Software Protection Mechanism for Autonomous Vehicular Cloud Computing","authors":"Muhammad Hataba, Ahmed B. T. Sherif, Reem Elkhouly","doi":"10.1109/MWSCAS47672.2021.9531682","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531682","url":null,"abstract":"Cars are becoming smarter every day. They are being equipped with sensors, communications interfaces, and more powerful processing capabilities. The primary purpose was to enable these cars to drive themselves without any human interventions and become so-called Autonomous Vehicles (AVs). But why stop there, why not harness all that computing power for a greater collective purpose. That’s how the idea of Autonomous Vehicular Cloud Computing (AVCC) was born. Nonetheless, this is not a trivial task, the mobile and dynamic nature of vehicles poses a significant challenge in the formation and management of this cloud computing model and yet a more substantial challenge in terms of security and privacy of all the parties involved in this system. In this paper, we focus on protecting software running on AVCC. We use dynamic obfuscated compilation to complicate programs’ execution paths and hinder information leakage via side channels attacks. Relying on compilers offers advantages, such as the independence of architecture and support for a variety high-level programming languages and application simplicity with minimal set-up cost. Here, we introduce our system in the realm of ARM processor, which power AVCC. Then, we present execution statistics for simple standard programs. The results show tangible timing variations in diversified code versions for the same program, which may disrupt side-channel attacks.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"60 1","pages":"878-881"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84519506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531668
Bibhudutta Satapathy, Amandeep Kaur
A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.
{"title":"A low kickback noise and low power dynamic comparator","authors":"Bibhudutta Satapathy, Amandeep Kaur","doi":"10.1109/MWSCAS47672.2021.9531668","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531668","url":null,"abstract":"A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"146-149"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72953801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531803
S. Mahran, O. Liboiron-Ladouceur, G. Cowan
This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.
{"title":"20 Gb/s Dual-Mode SST VCSEL Driver","authors":"S. Mahran, O. Liboiron-Ladouceur, G. Cowan","doi":"10.1109/MWSCAS47672.2021.9531803","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531803","url":null,"abstract":"This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"124 1","pages":"428-431"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88626427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531861
Dibyajyoti Mukherjee, D. Mallick
This work presents the design and analysis of magnetoelectric (ME) transducer based wireless power transfer (WPT) system incorporating a suitable interface power management circuit (PMC). ME transducers provide effective means to design high-efficiency power transfer to medical implantable devices at low frequencies addressing the trade-off between size miniaturization, lower skin attenuation and higher power transfer. A tri-layered ME laminated transducer operating at 50kHz is designed and fabricated to study the source characteristics. The proposed ME WPT device produces 2.4V output voltage and 1.75mW output power across a load of 3kΩ when the input magnetic field is 2.5mT. A novel PMC design based on Dickson Charge Pump followed by peak detector, buck regulator, and synchronous electric charge extraction (SECE) switching technique is considered which is implemented using low-cost, off-the-shelf components on PCB. The proposed circuit is characterized by very low current consumption and is specifically designed for operating at an input voltage ranging between 350mV to 15V, which provides a significant flexibility in terms of transducer design specifically towards high efficiency WPT systems.
{"title":"Magnetoelectric Wireless Power Transfer System for Biomedical Implants","authors":"Dibyajyoti Mukherjee, D. Mallick","doi":"10.1109/MWSCAS47672.2021.9531861","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531861","url":null,"abstract":"This work presents the design and analysis of magnetoelectric (ME) transducer based wireless power transfer (WPT) system incorporating a suitable interface power management circuit (PMC). ME transducers provide effective means to design high-efficiency power transfer to medical implantable devices at low frequencies addressing the trade-off between size miniaturization, lower skin attenuation and higher power transfer. A tri-layered ME laminated transducer operating at 50kHz is designed and fabricated to study the source characteristics. The proposed ME WPT device produces 2.4V output voltage and 1.75mW output power across a load of 3kΩ when the input magnetic field is 2.5mT. A novel PMC design based on Dickson Charge Pump followed by peak detector, buck regulator, and synchronous electric charge extraction (SECE) switching technique is considered which is implemented using low-cost, off-the-shelf components on PCB. The proposed circuit is characterized by very low current consumption and is specifically designed for operating at an input voltage ranging between 350mV to 15V, which provides a significant flexibility in terms of transducer design specifically towards high efficiency WPT systems.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"91 1","pages":"356-359"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84904652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531734
K. Ochs, Bakr Al Beattie, S. Jenderny
A promising approach for efficiently solving NP-hard optimization problems is based on mapping the problems onto Ising machines. Oscillator-based Ising machines can be implemented by utilizing sub-harmonic injection locking, which enables binary phase shifts between the oscillators and leads to an improved reliability of Ising machines. Based on a modified Kuramoto model with sub-harmonic injection locking, we synthesize an ideal electrical circuit displaying the phase dynamics of an Ising machine. The ideal circuit can be utilized to specifically take non-ideal effects into account, serving as a starting point for designing Ising machines with increased performance when considering existing electrical components. We furthermore derive a corresponding wave digital model, which is utilized for emulating the synthesized electrical circuit. The emulation results show that the synthesized circuit indeed models the phase dynamics of an Ising machine capable of solving Max-Cut problems with an accuracy of 88% for a 5-node problem and weights between 0 and 31.
{"title":"An Ising Machine Solving Max-Cut Problems based on the Circuit Synthesis of the Phase Dynamics of a Modified Kuramoto Model","authors":"K. Ochs, Bakr Al Beattie, S. Jenderny","doi":"10.1109/MWSCAS47672.2021.9531734","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531734","url":null,"abstract":"A promising approach for efficiently solving NP-hard optimization problems is based on mapping the problems onto Ising machines. Oscillator-based Ising machines can be implemented by utilizing sub-harmonic injection locking, which enables binary phase shifts between the oscillators and leads to an improved reliability of Ising machines. Based on a modified Kuramoto model with sub-harmonic injection locking, we synthesize an ideal electrical circuit displaying the phase dynamics of an Ising machine. The ideal circuit can be utilized to specifically take non-ideal effects into account, serving as a starting point for designing Ising machines with increased performance when considering existing electrical components. We furthermore derive a corresponding wave digital model, which is utilized for emulating the synthesized electrical circuit. The emulation results show that the synthesized circuit indeed models the phase dynamics of an Ising machine capable of solving Max-Cut problems with an accuracy of 88% for a 5-node problem and weights between 0 and 31.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"11 1","pages":"982-985"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85028742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531704
Haixiang Zhao, R. Sarpeshkar, S. Mandal
This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and auto-correlation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the IHP 0.25 µm BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.01 mm2 and typically consumes 100 µA, which are 10× and 8× better, respectively, than prior implementations.
{"title":"A Compact and Power-Efficient Noise Generator for Stochastic Simulations","authors":"Haixiang Zhao, R. Sarpeshkar, S. Mandal","doi":"10.1109/MWSCAS47672.2021.9531704","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531704","url":null,"abstract":"This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and auto-correlation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the IHP 0.25 µm BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.01 mm2 and typically consumes 100 µA, which are 10× and 8× better, respectively, than prior implementations.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"212 1","pages":"806-811"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77767673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531701
W. Jenkins, Magni Hussain
Previous research results have demonstrated that the bio-inspired Lévy Flight Firefly Algorithm (LFFA) can be effectively used in IIR adaptive filters, non-linear adaptive filters, IIR coupled form adaptive filters, and IIR lattice-ladder adaptive filters. It has recently been shown that the LFFA can be applied to adaptive 2-D McClellan "unconstrained" Transform filters so the adaptivity can approximate the frequency domain contours. This paper demonstrates how a special block length modification to the LFFA algorithm produces a 2-D Modified LFFA (2-D MLFFA) that enhances the adaptive convergence rate and lowers the MSE as the 2D-MLFFA converges toward the global minimum MSE.
{"title":"Modification Comparisons of the Particle Swarm and Levy Flight Firefly Adaptive DSP Algorithms","authors":"W. Jenkins, Magni Hussain","doi":"10.1109/MWSCAS47672.2021.9531701","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531701","url":null,"abstract":"Previous research results have demonstrated that the bio-inspired Lévy Flight Firefly Algorithm (LFFA) can be effectively used in IIR adaptive filters, non-linear adaptive filters, IIR coupled form adaptive filters, and IIR lattice-ladder adaptive filters. It has recently been shown that the LFFA can be applied to adaptive 2-D McClellan \"unconstrained\" Transform filters so the adaptivity can approximate the frequency domain contours. This paper demonstrates how a special block length modification to the LFFA algorithm produces a 2-D Modified LFFA (2-D MLFFA) that enhances the adaptive convergence rate and lowers the MSE as the 2D-MLFFA converges toward the global minimum MSE.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82960884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：