Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531776
S. Gardner, M. Haider, L. Moradi, V. Vantsevich
Image classification is typically performed with highly trained feed-forward machine learning algorithms like deep neural networks and support vector machines. The image can be treated as a time-series input when applied to the network multiple times, opening the way for recurrent neural networks to perform tasks like image classification, semantic segmentation and auto-encoding. With this approach, ultra-fast training, network optimization, and short-term memory effects allows for dynamic, low-volume datasets to be quickly learned without heavy image pre-processing or feature extraction; the main limitation being that input images need labeled output images for training, as is also true of most standard approaches. In this work, the MNIST handwritten digit dataset is used as a benchmark to evaluate metrics of a modified Echo State Network for static image classification. The image array is passed through a noise filter multiple times as the Echo State Network converges to a classification. This highly dynamic approach easily adapts to sequential image (video) tasks like object tracking and is effective with small datasets. Classification rates reach 95.3% with sample size of 10000 handwritten digits and training time of approximately 5 minutes. Progression of this research enables discrete image and time-series classification under a single algorithm, with low computing power and memory requirements.
{"title":"A Modified Echo State Network for Time Independent Image Classification","authors":"S. Gardner, M. Haider, L. Moradi, V. Vantsevich","doi":"10.1109/MWSCAS47672.2021.9531776","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531776","url":null,"abstract":"Image classification is typically performed with highly trained feed-forward machine learning algorithms like deep neural networks and support vector machines. The image can be treated as a time-series input when applied to the network multiple times, opening the way for recurrent neural networks to perform tasks like image classification, semantic segmentation and auto-encoding. With this approach, ultra-fast training, network optimization, and short-term memory effects allows for dynamic, low-volume datasets to be quickly learned without heavy image pre-processing or feature extraction; the main limitation being that input images need labeled output images for training, as is also true of most standard approaches. In this work, the MNIST handwritten digit dataset is used as a benchmark to evaluate metrics of a modified Echo State Network for static image classification. The image array is passed through a noise filter multiple times as the Echo State Network converges to a classification. This highly dynamic approach easily adapts to sequential image (video) tasks like object tracking and is effective with small datasets. Classification rates reach 95.3% with sample size of 10000 handwritten digits and training time of approximately 5 minutes. Progression of this research enables discrete image and time-series classification under a single algorithm, with low computing power and memory requirements.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"255-258"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80745132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531813
Noah Waller, Hunter Nauman, Derek Taylor, Rafael Del Carmen, J. Di
With the current business model and increasing complexity of hardware designs, third-party Intellectual Properties (IPs) are prevalently incorporated into first-party designs. The use of third-party IPs increases security concerns related to hardware Trojans inserted by attackers. Previous work on Golden Reference Matching focuses on matching with all entries within a single Golden Reference Library (GRL) containing whitelisted and blacklisted functionalities. This paper presents two new Golden Reference Libraries, Champion GRL and Functionality GRL, which were introduced along with coarse- grained and fine-grained asset reassignment to soft IPs and GRL entries in order to improve matching accuracy while simultaneously saving computational resources.
{"title":"Character Reassignment for Hardware Trojan Detection","authors":"Noah Waller, Hunter Nauman, Derek Taylor, Rafael Del Carmen, J. Di","doi":"10.1109/MWSCAS47672.2021.9531813","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531813","url":null,"abstract":"With the current business model and increasing complexity of hardware designs, third-party Intellectual Properties (IPs) are prevalently incorporated into first-party designs. The use of third-party IPs increases security concerns related to hardware Trojans inserted by attackers. Previous work on Golden Reference Matching focuses on matching with all entries within a single Golden Reference Library (GRL) containing whitelisted and blacklisted functionalities. This paper presents two new Golden Reference Libraries, Champion GRL and Functionality GRL, which were introduced along with coarse- grained and fine-grained asset reassignment to soft IPs and GRL entries in order to improve matching accuracy while simultaneously saving computational resources.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"861-864"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87427512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531796
Jingbo Zhou, Xinmiao Zhang
Logic locking is necessary for protecting intellectual property. Although logic-locking schemes have been proposed to resist the powerful satisfiability (SAT)-based attack, many of them are subject to removal attacks, which identify the logic- locking block and replace its output by the correct signal, so the circuit would function correctly without the right key. In order to prevent removal attacks, the stripped functional logic locking-Hamming distance (SFLL-HD) scheme and its variations corrupt the original circuit and add a logic-locking block to correct the errors. The high-complexity HD checker can be also replaced by the Cascaded(CAS)-lock block. This paper proposes a new low-complexity logic-locking scheme inspired by the Generalized(G)-Anti-SAT block. By relaxing the constraint of the G-Anti-SAT design in the SFLL setting, our new logic-locking scheme reduces the logic complexity by around 37% compared to the M-CAS block with similar resistance to the SAT and removal attacks. Additionally, unlike the SFLL-HD and Mirrored (M)- CAS schemes, the proposed logic-locking block can use a large variation of functions. This makes existing or potential attacks utilizing properties of the logic function impossible.
{"title":"A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks","authors":"Jingbo Zhou, Xinmiao Zhang","doi":"10.1109/MWSCAS47672.2021.9531796","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531796","url":null,"abstract":"Logic locking is necessary for protecting intellectual property. Although logic-locking schemes have been proposed to resist the powerful satisfiability (SAT)-based attack, many of them are subject to removal attacks, which identify the logic- locking block and replace its output by the correct signal, so the circuit would function correctly without the right key. In order to prevent removal attacks, the stripped functional logic locking-Hamming distance (SFLL-HD) scheme and its variations corrupt the original circuit and add a logic-locking block to correct the errors. The high-complexity HD checker can be also replaced by the Cascaded(CAS)-lock block. This paper proposes a new low-complexity logic-locking scheme inspired by the Generalized(G)-Anti-SAT block. By relaxing the constraint of the G-Anti-SAT design in the SFLL setting, our new logic-locking scheme reduces the logic complexity by around 37% compared to the M-CAS block with similar resistance to the SAT and removal attacks. Additionally, unlike the SFLL-HD and Mirrored (M)- CAS schemes, the proposed logic-locking block can use a large variation of functions. This makes existing or potential attacks utilizing properties of the logic function impossible.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"869-873"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75584405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531691
Suwan Kim, Taewhan Kim
We propose a practical approach to the cell replacement problem for resolving the pin inaccessibility in the ECO (engineering-change-order) routing stage. The prior cell replacement method performs in two steps: (i) it prepares a subsidiary (i.e., alternative) cell library that includes for each cell type a set of diverse cell layouts. Then, (ii) it iteratively tries to replace the cells of routing failures with some cells in the subsidiary library during ECO routing in order to fix the routing failures. In this work, we downsize the subsidiary library produced in step (i) to speed up the sequential and time-consuming process of step (ii). Precisely, we propose a function based on the well-known formulation of Levenshtein distance to measure the degree of the pin topology difference between the layout of a cell type in the target library and a layout of the same type in the subsidiary library. Then, we update the subsidiary library to include, for each cell type, exactly one layout that has the biggest pin topology difference. Through experiments with benchmark circuits, it is shown that using the subsidiary library produced by our topology difference formulation enables to reduce the number of trials of cell replacements significantly over the conventional method while fixing almost the same amount of routing violations.
{"title":"Practical Approach to Cell Replacement for Resolving Pin Inaccessibility","authors":"Suwan Kim, Taewhan Kim","doi":"10.1109/MWSCAS47672.2021.9531691","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531691","url":null,"abstract":"We propose a practical approach to the cell replacement problem for resolving the pin inaccessibility in the ECO (engineering-change-order) routing stage. The prior cell replacement method performs in two steps: (i) it prepares a subsidiary (i.e., alternative) cell library that includes for each cell type a set of diverse cell layouts. Then, (ii) it iteratively tries to replace the cells of routing failures with some cells in the subsidiary library during ECO routing in order to fix the routing failures. In this work, we downsize the subsidiary library produced in step (i) to speed up the sequential and time-consuming process of step (ii). Precisely, we propose a function based on the well-known formulation of Levenshtein distance to measure the degree of the pin topology difference between the layout of a cell type in the target library and a layout of the same type in the subsidiary library. Then, we update the subsidiary library to include, for each cell type, exactly one layout that has the biggest pin topology difference. Through experiments with benchmark circuits, it is shown that using the subsidiary library produced by our topology difference formulation enables to reduce the number of trials of cell replacements significantly over the conventional method while fixing almost the same amount of routing violations.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"34 1","pages":"224-227"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90809799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531782
Genevieve Sapijaszko, W. Mikhael
Image recognition systems are critical components in numerous applications, often requiring real-time implementations that are both fast and accurate. Convolutional Neural Networks (CNNs) are an emerging tool used to meet these conditions. However, in image recognition, CNNs are often designed to fit general image datasets leading to implementations that may have more layers and nodes than are warranted in particular applications. In this paper, a neuroevolution algorithm is developed to reduce a CNN architecture’s complexity by determining the minimal CNN structure and hyperparameters needed to fit a traffic sign dataset. A neuroevolution algorithm is employed to tune the CNN’s parameters and topology to enable a more efficient parameter space search. Results show that despite reducing complexity, the system still maintains high recognition accuracy compared to popular CNNs, such as AlexNet, VGGNet 16, VGGNet 19, GoogleNet, ResNet 50, and ResNet 101.
{"title":"Designing Convolutional Neural Networks Using Neuroevolution for Traffic Sign Datasets","authors":"Genevieve Sapijaszko, W. Mikhael","doi":"10.1109/MWSCAS47672.2021.9531782","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531782","url":null,"abstract":"Image recognition systems are critical components in numerous applications, often requiring real-time implementations that are both fast and accurate. Convolutional Neural Networks (CNNs) are an emerging tool used to meet these conditions. However, in image recognition, CNNs are often designed to fit general image datasets leading to implementations that may have more layers and nodes than are warranted in particular applications. In this paper, a neuroevolution algorithm is developed to reduce a CNN architecture’s complexity by determining the minimal CNN structure and hyperparameters needed to fit a traffic sign dataset. A neuroevolution algorithm is employed to tune the CNN’s parameters and topology to enable a more efficient parameter space search. Results show that despite reducing complexity, the system still maintains high recognition accuracy compared to popular CNNs, such as AlexNet, VGGNet 16, VGGNet 19, GoogleNet, ResNet 50, and ResNet 101.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"34 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88143590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531803
S. Mahran, O. Liboiron-Ladouceur, G. Cowan
This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.
{"title":"20 Gb/s Dual-Mode SST VCSEL Driver","authors":"S. Mahran, O. Liboiron-Ladouceur, G. Cowan","doi":"10.1109/MWSCAS47672.2021.9531803","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531803","url":null,"abstract":"This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"124 1","pages":"428-431"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88626427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531861
Dibyajyoti Mukherjee, D. Mallick
This work presents the design and analysis of magnetoelectric (ME) transducer based wireless power transfer (WPT) system incorporating a suitable interface power management circuit (PMC). ME transducers provide effective means to design high-efficiency power transfer to medical implantable devices at low frequencies addressing the trade-off between size miniaturization, lower skin attenuation and higher power transfer. A tri-layered ME laminated transducer operating at 50kHz is designed and fabricated to study the source characteristics. The proposed ME WPT device produces 2.4V output voltage and 1.75mW output power across a load of 3kΩ when the input magnetic field is 2.5mT. A novel PMC design based on Dickson Charge Pump followed by peak detector, buck regulator, and synchronous electric charge extraction (SECE) switching technique is considered which is implemented using low-cost, off-the-shelf components on PCB. The proposed circuit is characterized by very low current consumption and is specifically designed for operating at an input voltage ranging between 350mV to 15V, which provides a significant flexibility in terms of transducer design specifically towards high efficiency WPT systems.
{"title":"Magnetoelectric Wireless Power Transfer System for Biomedical Implants","authors":"Dibyajyoti Mukherjee, D. Mallick","doi":"10.1109/MWSCAS47672.2021.9531861","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531861","url":null,"abstract":"This work presents the design and analysis of magnetoelectric (ME) transducer based wireless power transfer (WPT) system incorporating a suitable interface power management circuit (PMC). ME transducers provide effective means to design high-efficiency power transfer to medical implantable devices at low frequencies addressing the trade-off between size miniaturization, lower skin attenuation and higher power transfer. A tri-layered ME laminated transducer operating at 50kHz is designed and fabricated to study the source characteristics. The proposed ME WPT device produces 2.4V output voltage and 1.75mW output power across a load of 3kΩ when the input magnetic field is 2.5mT. A novel PMC design based on Dickson Charge Pump followed by peak detector, buck regulator, and synchronous electric charge extraction (SECE) switching technique is considered which is implemented using low-cost, off-the-shelf components on PCB. The proposed circuit is characterized by very low current consumption and is specifically designed for operating at an input voltage ranging between 350mV to 15V, which provides a significant flexibility in terms of transducer design specifically towards high efficiency WPT systems.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"91 1","pages":"356-359"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84904652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531734
K. Ochs, Bakr Al Beattie, S. Jenderny
A promising approach for efficiently solving NP-hard optimization problems is based on mapping the problems onto Ising machines. Oscillator-based Ising machines can be implemented by utilizing sub-harmonic injection locking, which enables binary phase shifts between the oscillators and leads to an improved reliability of Ising machines. Based on a modified Kuramoto model with sub-harmonic injection locking, we synthesize an ideal electrical circuit displaying the phase dynamics of an Ising machine. The ideal circuit can be utilized to specifically take non-ideal effects into account, serving as a starting point for designing Ising machines with increased performance when considering existing electrical components. We furthermore derive a corresponding wave digital model, which is utilized for emulating the synthesized electrical circuit. The emulation results show that the synthesized circuit indeed models the phase dynamics of an Ising machine capable of solving Max-Cut problems with an accuracy of 88% for a 5-node problem and weights between 0 and 31.
{"title":"An Ising Machine Solving Max-Cut Problems based on the Circuit Synthesis of the Phase Dynamics of a Modified Kuramoto Model","authors":"K. Ochs, Bakr Al Beattie, S. Jenderny","doi":"10.1109/MWSCAS47672.2021.9531734","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531734","url":null,"abstract":"A promising approach for efficiently solving NP-hard optimization problems is based on mapping the problems onto Ising machines. Oscillator-based Ising machines can be implemented by utilizing sub-harmonic injection locking, which enables binary phase shifts between the oscillators and leads to an improved reliability of Ising machines. Based on a modified Kuramoto model with sub-harmonic injection locking, we synthesize an ideal electrical circuit displaying the phase dynamics of an Ising machine. The ideal circuit can be utilized to specifically take non-ideal effects into account, serving as a starting point for designing Ising machines with increased performance when considering existing electrical components. We furthermore derive a corresponding wave digital model, which is utilized for emulating the synthesized electrical circuit. The emulation results show that the synthesized circuit indeed models the phase dynamics of an Ising machine capable of solving Max-Cut problems with an accuracy of 88% for a 5-node problem and weights between 0 and 31.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"11 1","pages":"982-985"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85028742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531704
Haixiang Zhao, R. Sarpeshkar, S. Mandal
This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and auto-correlation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the IHP 0.25 µm BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.01 mm2 and typically consumes 100 µA, which are 10× and 8× better, respectively, than prior implementations.
{"title":"A Compact and Power-Efficient Noise Generator for Stochastic Simulations","authors":"Haixiang Zhao, R. Sarpeshkar, S. Mandal","doi":"10.1109/MWSCAS47672.2021.9531704","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531704","url":null,"abstract":"This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and auto-correlation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the IHP 0.25 µm BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.01 mm2 and typically consumes 100 µA, which are 10× and 8× better, respectively, than prior implementations.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"212 1","pages":"806-811"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77767673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531701
W. Jenkins, Magni Hussain
Previous research results have demonstrated that the bio-inspired Lévy Flight Firefly Algorithm (LFFA) can be effectively used in IIR adaptive filters, non-linear adaptive filters, IIR coupled form adaptive filters, and IIR lattice-ladder adaptive filters. It has recently been shown that the LFFA can be applied to adaptive 2-D McClellan "unconstrained" Transform filters so the adaptivity can approximate the frequency domain contours. This paper demonstrates how a special block length modification to the LFFA algorithm produces a 2-D Modified LFFA (2-D MLFFA) that enhances the adaptive convergence rate and lowers the MSE as the 2D-MLFFA converges toward the global minimum MSE.
{"title":"Modification Comparisons of the Particle Swarm and Levy Flight Firefly Adaptive DSP Algorithms","authors":"W. Jenkins, Magni Hussain","doi":"10.1109/MWSCAS47672.2021.9531701","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531701","url":null,"abstract":"Previous research results have demonstrated that the bio-inspired Lévy Flight Firefly Algorithm (LFFA) can be effectively used in IIR adaptive filters, non-linear adaptive filters, IIR coupled form adaptive filters, and IIR lattice-ladder adaptive filters. It has recently been shown that the LFFA can be applied to adaptive 2-D McClellan \"unconstrained\" Transform filters so the adaptivity can approximate the frequency domain contours. This paper demonstrates how a special block length modification to the LFFA algorithm produces a 2-D Modified LFFA (2-D MLFFA) that enhances the adaptive convergence rate and lowers the MSE as the 2D-MLFFA converges toward the global minimum MSE.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82960884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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