Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256972
Yao‐Feng Chang, Yen‐Ting Chen, F. Xue, Yanzhen Wang, F. Zhou, B. Fowler, J. Lee
The electrical characteristics of SiOx-based complementary resistive switching (CRS) memristor have been investigated. Post-deposition annealing (PDA: 500°C 5min in O2) of TaN/SiO2/n++ Si-substrate CRS memristor has been found to reduce operational variation in device characteristics, as well as improve the electrical stability during repeated switching. In this work, we have also studied the effects of sweeping polarity, operating temperature, electrode material and dimension scaling. Our experimental results not only provide additional insights into optimization of the SiOx-based CRS memory but also help in constructing a physical picture for the switching mechanism.
研究了硅氧基互补电阻开关(CRS)忆阻器的电学特性。发现TaN/SiO2/n++ si衬底CRS记忆电阻器的沉积后退火(PDA: 500°C 5min in O2)减少了器件特性的操作变化，并提高了重复开关时的电稳定性。在这项工作中，我们还研究了扫描极性，工作温度，电极材料和尺寸缩放的影响。我们的实验结果不仅为基于siox的CRS存储器的优化提供了额外的见解，而且有助于构建开关机制的物理图景。
{"title":"Study of SiOx-based complementary resistive switching memristor","authors":"Yao‐Feng Chang, Yen‐Ting Chen, F. Xue, Yanzhen Wang, F. Zhou, B. Fowler, J. Lee","doi":"10.1109/DRC.2012.6256972","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256972","url":null,"abstract":"The electrical characteristics of SiOx-based complementary resistive switching (CRS) memristor have been investigated. Post-deposition annealing (PDA: 500°C 5min in O2) of TaN/SiO2/n++ Si-substrate CRS memristor has been found to reduce operational variation in device characteristics, as well as improve the electrical stability during repeated switching. In this work, we have also studied the effects of sweeping polarity, operating temperature, electrode material and dimension scaling. Our experimental results not only provide additional insights into optimization of the SiOx-based CRS memory but also help in constructing a physical picture for the switching mechanism.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"89 1","pages":"49-50"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84473631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257030
N. Ketteniss, B. Reuters, B. Hollander, H. Hahn, H. Kalisch, A. Vescan
A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.
{"title":"Quaternary nitride enhancement mode HFET with 260 mS/mm and a threshold voltage of +0.5 V","authors":"N. Ketteniss, B. Reuters, B. Hollander, H. Hahn, H. Kalisch, A. Vescan","doi":"10.1109/DRC.2012.6257030","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257030","url":null,"abstract":"A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"17 1","pages":"161-162"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89957840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256958
A. Sarkar, B. Behin-Aein, S. Srinivasan, S. Datta
In our recent work we have proposed the possibility of using magnets interacting via spin currents to implement all-spin logic (ASL) devices for information processing, fundamentally different from the standard charge-based architecture. Information is stored in the state of magnetization of the magnets and is communicated between magnets through pure spin currents. Simulations of these multi-magnet networks with our experimentally benchmarked model [2] indicate that such spin-magnet circuits can mimic many of the attributes of standard charge-based circuits such as inverters, universal NAND/NOR gates, ring oscillators etc .. However, these circuits do not take full advantage of the natural hybrid analog/digital character of spin currents and magnets, the possibility of which we discuss in this paper. Indeed, our contribution in this paper is twofold: We show that a simple model of an ASL device, maps on to the well-known 'leaky integrate and fire' equation of neuron dynamics, highlighting the analogy of the magnet to a neuron. We introduce LLGz for the first time in this paper and relate it to our full rigorous model. We also show that LLGz captures the steady state behavior of magnets predicted by the full model.
{"title":"All Spin Logic device as a compact artificial neuron","authors":"A. Sarkar, B. Behin-Aein, S. Srinivasan, S. Datta","doi":"10.1109/DRC.2012.6256958","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256958","url":null,"abstract":"In our recent work we have proposed the possibility of using magnets interacting via spin currents to implement all-spin logic (ASL) devices for information processing, fundamentally different from the standard charge-based architecture. Information is stored in the state of magnetization of the magnets and is communicated between magnets through pure spin currents. Simulations of these multi-magnet networks with our experimentally benchmarked model [2] indicate that such spin-magnet circuits can mimic many of the attributes of standard charge-based circuits such as inverters, universal NAND/NOR gates, ring oscillators etc .. However, these circuits do not take full advantage of the natural hybrid analog/digital character of spin currents and magnets, the possibility of which we discuss in this paper. Indeed, our contribution in this paper is twofold: We show that a simple model of an ASL device, maps on to the well-known 'leaky integrate and fire' equation of neuron dynamics, highlighting the analogy of the magnet to a neuron. We introduce LLGz for the first time in this paper and relate it to our full rigorous model. We also show that LLGz captures the steady state behavior of magnets predicted by the full model.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"121 1","pages":"99-100"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85352346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256957
M. Sharad, G. Panagopoulos, C. Augustine, K. Roy
In this work we propose a magnetic random access memory (MRAM) bit-cell design based on non-local spin transfer torque (NLSTT). In the proposed bit-cell, the data is written into the free layer of a magnetic tunnel junction (MTJ) using spin diffusion current (non-local spin injection), without injecting charge current into the tunneling oxide. Thus, the reliability issues, related to dielectric breakdown due to high tunneling current density (for high switching speed) are significantly mitigated. Separation of read and write current paths in the bit-cell helps in optimizing read and write separately. Hence, higher MgO thickness can be used for higher cell TMR and higher read disturb margin. Higher MTJ resistance resulting from thicker MgO also lets us use voltage mode sensing, that achieves higher speed for read operation. In the proposed bit-cell, we employ two supplementary spin injectors with tilted axis anisotropy, in order to compensate for the comparatively lower efficiency for non-local spin injection. Analysis of the proposed NLSTT-MRAM bit-cell is done using a physics based simulation framework, benchmarked with experimental data for lateral spin valve (LSV). Apart from high reliability, the proposed bit-cell achieves 110% higher tunnel magneto resistance (TMR) and 4X higher read margin for I ns switching speed as compared to standard I-transistor-I MTJ (1-T I-R) STT -MRAM of similar area.
{"title":"NLSTT-MRAM: Robust spin transfer torque MRAM using non-local spin injection for write","authors":"M. Sharad, G. Panagopoulos, C. Augustine, K. Roy","doi":"10.1109/DRC.2012.6256957","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256957","url":null,"abstract":"In this work we propose a magnetic random access memory (MRAM) bit-cell design based on non-local spin transfer torque (NLSTT). In the proposed bit-cell, the data is written into the free layer of a magnetic tunnel junction (MTJ) using spin diffusion current (non-local spin injection), without injecting charge current into the tunneling oxide. Thus, the reliability issues, related to dielectric breakdown due to high tunneling current density (for high switching speed) are significantly mitigated. Separation of read and write current paths in the bit-cell helps in optimizing read and write separately. Hence, higher MgO thickness can be used for higher cell TMR and higher read disturb margin. Higher MTJ resistance resulting from thicker MgO also lets us use voltage mode sensing, that achieves higher speed for read operation. In the proposed bit-cell, we employ two supplementary spin injectors with tilted axis anisotropy, in order to compensate for the comparatively lower efficiency for non-local spin injection. Analysis of the proposed NLSTT-MRAM bit-cell is done using a physics based simulation framework, benchmarked with experimental data for lateral spin valve (LSV). Apart from high reliability, the proposed bit-cell achieves 110% higher tunnel magneto resistance (TMR) and 4X higher read margin for I ns switching speed as compared to standard I-transistor-I MTJ (1-T I-R) STT -MRAM of similar area.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"117 1","pages":"97-98"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85500093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256973
S. Madisetti, P. Nagaiah, T. Chidambaram, V. Tokranov, M. Yakimov, S. Oktyabrsky
InGaSb material family with its higher hole transport properties are potential candidates for group III-V CMOS circuits. Understanding of the dominant scattering mechanisms is crucial for the development of future high speed, low power device applications. We present Hall mobility data of p-type InGaSb quantum well (QW) channels and derive the dominant scattering mechanisms related to the interface and trapped charges that degrade mobility in these structures.
{"title":"Mobility and scattering mechanisms in buried InGaSb quantum well channels integrated with in-situ MBE grown gate oxide","authors":"S. Madisetti, P. Nagaiah, T. Chidambaram, V. Tokranov, M. Yakimov, S. Oktyabrsky","doi":"10.1109/DRC.2012.6256973","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256973","url":null,"abstract":"InGaSb material family with its higher hole transport properties are potential candidates for group III-V CMOS circuits. Understanding of the dominant scattering mechanisms is crucial for the development of future high speed, low power device applications. We present Hall mobility data of p-type InGaSb quantum well (QW) channels and derive the dominant scattering mechanisms related to the interface and trapped charges that degrade mobility in these structures.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"20 1","pages":"103-104"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86933324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256959
A. Agrawal, Jeongwon Park, D. Mohata, K. Ahmed, S. Datta
Low contact resistivity ohmic contacts are demonstrated on n-Ge at doping level ND of 1×1019 cm-3. Atomic Hydrogen (H*) clean was shown to reduce the specific contact resistivity (ρC) by 7% for the first time, due to reduction of barrier height of 70meV compared to the unclean sample. Improvement was primarily due to the reduction of the germanim oxide, GeOx, and surface passivation at the interface by H atoms as confirmed by energy-dispersive X-ray spectroscopy (EDS). The ρC of 2.7×10-5 Ω-cm2, at a moderate doping density of 1×1019 cm-3, is the lowest with the minimum possible thermal budget.
{"title":"Experimental demonstration of “Cold” low contact resistivity ohmic contacts on moderately doped n-Ge with in-situ atomic hydrogen clean","authors":"A. Agrawal, Jeongwon Park, D. Mohata, K. Ahmed, S. Datta","doi":"10.1109/DRC.2012.6256959","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256959","url":null,"abstract":"Low contact resistivity ohmic contacts are demonstrated on n-Ge at doping level N<sub>D</sub> of 1×10<sup>19</sup> cm<sup>-3</sup>. Atomic Hydrogen (H*) clean was shown to reduce the specific contact resistivity (ρ<sub>C</sub>) by 7% for the first time, due to reduction of barrier height of 70meV compared to the unclean sample. Improvement was primarily due to the reduction of the germanim oxide, GeO<sub>x</sub>, and surface passivation at the interface by H atoms as confirmed by energy-dispersive X-ray spectroscopy (EDS). The ρ<sub>C</sub> of 2.7×10<sup>-5</sup> Ω-cm<sup>2</sup>, at a moderate doping density of 1×10<sup>19</sup> cm<sup>-3</sup>, is the lowest with the minimum possible thermal budget.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"22 1","pages":"101-102"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89650456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257032
R. Bijesh, D. Mohata, H. Liu, S. Datta
Temperature dependent transfer characteristics measurements confirm that the current in heteroJn TFET is limited by band-to-band tunneling at Vds=500mV at low temperature. HeteroJn TFETs exhibit lower noise compared to homoJn TFET where the current transport is dominated by band-to-band tunneling alone. However, at 300K, heteroJn TFETs have comparable noise performance due to the strong presence of trap assisted tunneling (Nit~1013 cm-2). A carrier number fluctuation based model is developed, for the first time, to explain the flicker noise advantage of heteroJn TFETs over homoJn TFETs. HeteroJn TFETs not only provide higher drive currents but also exhibit lower flicker noise levels and hence make them suitable candidate for future low Vcc digital and analog applications.
{"title":"Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs","authors":"R. Bijesh, D. Mohata, H. Liu, S. Datta","doi":"10.1109/DRC.2012.6257032","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257032","url":null,"abstract":"Temperature dependent transfer characteristics measurements confirm that the current in heteroJn TFET is limited by band-to-band tunneling at Vds=500mV at low temperature. HeteroJn TFETs exhibit lower noise compared to homoJn TFET where the current transport is dominated by band-to-band tunneling alone. However, at 300K, heteroJn TFETs have comparable noise performance due to the strong presence of trap assisted tunneling (Nit~1013 cm-2). A carrier number fluctuation based model is developed, for the first time, to explain the flicker noise advantage of heteroJn TFETs over homoJn TFETs. HeteroJn TFETs not only provide higher drive currents but also exhibit lower flicker noise levels and hence make them suitable candidate for future low Vcc digital and analog applications.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"115 1","pages":"203-204"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88469759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256991
S. Swisher, S. Volkman, K. Braam, Jaewon Jang, V. Subramanian
Metal-oxide semiconductors have received a great deal of focus in recent years as a means of realizing transparent electronics for next generation display applications; such materials are expected to enable the realization of transparent pixel transistors for display that do not block light, enabling realization of brighter displays with higher aperture ratio. In recent years, the demonstration of amorphous thin films of transition metal oxides with mobility an order of magnitude greater than that of amorphous silicon has resulted in dramatic interest and rapid advances in the field. In particular, solution processable routes are considered particularly attractive since they may allow for low-cost fabrication techniques based on printing. There have been various reports of sol-gel based approaches to printable electronics based on these systems; however, an approach utilizing colloidal semiconductor nanocrystals has several distinct advantages. First, the high temperature required for crystal nucleation and growth can occur during the synthesis phase, thus decoupling the high temperature crystallization step from the processing constraints of the substrate. Second, and possibly even more importantly, using nanocrystals as the starting point for inorganic semiconducting inks may provide better control over the stoichiometry of the material, more consistent film composition, and a pathway towards controlled doping of the channel material. Here we report a synthesis of indium oxide nanocrystals, and the fabrication conditions that result in high-performance TFTs based on the same.
{"title":"High performance solution-processed thin-film transistors based on In2O3 nanocrystals","authors":"S. Swisher, S. Volkman, K. Braam, Jaewon Jang, V. Subramanian","doi":"10.1109/DRC.2012.6256991","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256991","url":null,"abstract":"Metal-oxide semiconductors have received a great deal of focus in recent years as a means of realizing transparent electronics for next generation display applications; such materials are expected to enable the realization of transparent pixel transistors for display that do not block light, enabling realization of brighter displays with higher aperture ratio. In recent years, the demonstration of amorphous thin films of transition metal oxides with mobility an order of magnitude greater than that of amorphous silicon has resulted in dramatic interest and rapid advances in the field. In particular, solution processable routes are considered particularly attractive since they may allow for low-cost fabrication techniques based on printing. There have been various reports of sol-gel based approaches to printable electronics based on these systems; however, an approach utilizing colloidal semiconductor nanocrystals has several distinct advantages. First, the high temperature required for crystal nucleation and growth can occur during the synthesis phase, thus decoupling the high temperature crystallization step from the processing constraints of the substrate. Second, and possibly even more importantly, using nanocrystals as the starting point for inorganic semiconducting inks may provide better control over the stoichiometry of the material, more consistent film composition, and a pathway towards controlled doping of the channel material. Here we report a synthesis of indium oxide nanocrystals, and the fabrication conditions that result in high-performance TFTs based on the same.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"38 1","pages":"241-242"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90868335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256931
C. Zota, S. H. Kim, Y. Asakura, M. Takenaka, S. Takagi
GaSb has stirred a significant interest over the recent years, due to its high bulk electron/hole mobility and optoelectronic properties [1]. Particularly, the high hole mobility makes GaSb one of the III-V materials promising for p-MOSFETs and fully-integrated CMOS applications. However, the device technologies for GaSb MOSFETs have not been fully developed yet. In this work, we address a novel formation technology of source and drain (S/D) for GaSb p-MOSFETs. One of the problems of the S/D formation in GaSb (and generally III-V) is the low dopant solubility and the necessity of high temperature annealing for dopant activation. However, thermal stability of the GaSb/oxide interfaces is low and, therefore, a S/D formation process with low thermal budget is strongly required [2]. Also, for deeply-scaled MOSFET fabrication, self-aligned S/D formation is mandatory. For these reasons, we introduce a salicide-like self-aligned metal S/D process by using Ni into GaSb. In this study, we present the results of the characterization of Ni-GaSb alloys formed by direct reaction between Ni and GaSb, which are suitable for S/D in GaSb p-MOSFETs. Finally, we demonstrate, for the first time, a GaSb p-MOSFET with self-aligned Ni-GaSb alloy S/D, which allows us to fabricate MOSFETs at temperature as low as 250°C.
{"title":"Self-aligned metal S/D GaSb p-MOSFETs using Ni-GaSb alloys","authors":"C. Zota, S. H. Kim, Y. Asakura, M. Takenaka, S. Takagi","doi":"10.1109/DRC.2012.6256931","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256931","url":null,"abstract":"GaSb has stirred a significant interest over the recent years, due to its high bulk electron/hole mobility and optoelectronic properties [1]. Particularly, the high hole mobility makes GaSb one of the III-V materials promising for p-MOSFETs and fully-integrated CMOS applications. However, the device technologies for GaSb MOSFETs have not been fully developed yet. In this work, we address a novel formation technology of source and drain (S/D) for GaSb p-MOSFETs. One of the problems of the S/D formation in GaSb (and generally III-V) is the low dopant solubility and the necessity of high temperature annealing for dopant activation. However, thermal stability of the GaSb/oxide interfaces is low and, therefore, a S/D formation process with low thermal budget is strongly required [2]. Also, for deeply-scaled MOSFET fabrication, self-aligned S/D formation is mandatory. For these reasons, we introduce a salicide-like self-aligned metal S/D process by using Ni into GaSb. In this study, we present the results of the characterization of Ni-GaSb alloys formed by direct reaction between Ni and GaSb, which are suitable for S/D in GaSb p-MOSFETs. Finally, we demonstrate, for the first time, a GaSb p-MOSFET with self-aligned Ni-GaSb alloy S/D, which allows us to fabricate MOSFETs at temperature as low as 250°C.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"8 1","pages":"71-72"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75864972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257012
E. Freeman, A. Kar, N. Shukla, R. Misra, R. Engel-Herbert, D. Schlom, V. Gopalan, K. Rabe, S. Datta
Continued physical scaling will reduce power dissipation primarily through the reduction in device capacitance; however, a far greater benefit would result if the CMOS FET could be replaced by a fundamentally new device scheme that operates under very low supply voltages. Recently, semiconductor based inter-band tunnel field effect transistors (TFET) have been explored due to their potential to achieve sub kBT/q steep switching swings, enabling low voltage operation. In this work, we explore the abrupt metal to insulator transition (MIT) of vanadium dioxide (VO2) based tunnel junction - a first step towards a correlated electron based steep switching TFET. As illustrated, the metal insulator transition MIT in materials with strong electron correlation can be utilized to modulate the tunnelling current by opening an energy gap around the Fermi level in the OFF-state, and a metal-insulator-metal tunnelling current by collapsing the gap in the ON-state.
{"title":"Characterization and modeling of metal-insulator transition (MIT) based tunnel junctions","authors":"E. Freeman, A. Kar, N. Shukla, R. Misra, R. Engel-Herbert, D. Schlom, V. Gopalan, K. Rabe, S. Datta","doi":"10.1109/DRC.2012.6257012","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257012","url":null,"abstract":"Continued physical scaling will reduce power dissipation primarily through the reduction in device capacitance; however, a far greater benefit would result if the CMOS FET could be replaced by a fundamentally new device scheme that operates under very low supply voltages. Recently, semiconductor based inter-band tunnel field effect transistors (TFET) have been explored due to their potential to achieve sub kBT/q steep switching swings, enabling low voltage operation. In this work, we explore the abrupt metal to insulator transition (MIT) of vanadium dioxide (VO2) based tunnel junction - a first step towards a correlated electron based steep switching TFET. As illustrated, the metal insulator transition MIT in materials with strong electron correlation can be utilized to modulate the tunnelling current by opening an energy gap around the Fermi level in the OFF-state, and a metal-insulator-metal tunnelling current by collapsing the gap in the ON-state.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"93 1","pages":"243-244"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83880941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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