Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256990
H. Liu, D. Mohata, A. Nidhi, V. Saripalli, V. Narayanan, S. Datta
A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.
{"title":"Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications","authors":"H. Liu, D. Mohata, A. Nidhi, V. Saripalli, V. Narayanan, S. Datta","doi":"10.1109/DRC.2012.6256990","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256990","url":null,"abstract":"A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"16 1","pages":"233-234"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80097856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256962
Guowang Li, Ronghua Wang, J. Verma, H. Xing, D. Jena
Ultra-thin body (UTB) devices with tight electrostatic and quantum confinement of charge carriers have been well developed in highly scaled silicon CMOS technology. For adopting such advanced methods, III-nitrides can benefit immensely from epitaxial AlN as the substrate platform, in contrast to conventional GaN-based substrate platform. With its large polarization charge, wide bandgap and large band offsets, AlN induces the maximal carrier densities while providing the best confinement for nitride channels of all compositions. Such devices stand also to benefit from the symmetry of electronic polarization: high density hole gases can be generated in much the same way as the high density 2DEG in GaN HEMTs, thus enabling p-channel FETs on the same material platform in a logical manner. The AlN/GaN heterojunctions where mobile carriers are located are epitaxial, and excellent transport properties are expected as opposed to the rougher oxide-semiconductor interfaces. Furthermore, AlN is an excellent electrical insulator but simultaneously an excellent thermal conductor, which makes it highly attractive to act as back-barrier and to lower junction temperatures in high power devices by efficient heat dissipation. There have been reports on relaxed GaN n-channel FETs (nFETs) on AlN [1, 2] and III-nitride based p-channel field effect transistors (pFETs) [3, 4]. All the prior work uses relaxed GaN as the channel, and strained GaN channels on AlN have not been explored before. In this work we demonstrate UTB GaN nFETs [5] and pFETs on AlN grown by molecular beam epitaxy (MBE) as the first step towards complementary logic and high power applications.
{"title":"Ultra-thin Body GaN-on-insulator nFETs and pFETs: Towards III-nitride complementary logic","authors":"Guowang Li, Ronghua Wang, J. Verma, H. Xing, D. Jena","doi":"10.1109/DRC.2012.6256962","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256962","url":null,"abstract":"Ultra-thin body (UTB) devices with tight electrostatic and quantum confinement of charge carriers have been well developed in highly scaled silicon CMOS technology. For adopting such advanced methods, III-nitrides can benefit immensely from epitaxial AlN as the substrate platform, in contrast to conventional GaN-based substrate platform. With its large polarization charge, wide bandgap and large band offsets, AlN induces the maximal carrier densities while providing the best confinement for nitride channels of all compositions. Such devices stand also to benefit from the symmetry of electronic polarization: high density hole gases can be generated in much the same way as the high density 2DEG in GaN HEMTs, thus enabling p-channel FETs on the same material platform in a logical manner. The AlN/GaN heterojunctions where mobile carriers are located are epitaxial, and excellent transport properties are expected as opposed to the rougher oxide-semiconductor interfaces. Furthermore, AlN is an excellent electrical insulator but simultaneously an excellent thermal conductor, which makes it highly attractive to act as back-barrier and to lower junction temperatures in high power devices by efficient heat dissipation. There have been reports on relaxed GaN n-channel FETs (nFETs) on AlN [1, 2] and III-nitride based p-channel field effect transistors (pFETs) [3, 4]. All the prior work uses relaxed GaN as the channel, and strained GaN channels on AlN have not been explored before. In this work we demonstrate UTB GaN nFETs [5] and pFETs on AlN grown by molecular beam epitaxy (MBE) as the first step towards complementary logic and high power applications.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"19 1","pages":"153-154"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85112817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256942
I. Young
This paper describes a methodology for benchmarking beyond CMOS exploratory devices for computation using metrics that can provide insights about the device fundamental operation. A more detailed investigation of circuits based upon two beyond-CMOS devices is given in the paper. First tunneling FET (TFET) circuits are compared to low power CMOS circuits. Then the All-Spin Logic device (ASLD) is described and a spin circuit theory based simulator is used to show the functional transient operation of an all spin logic circuit.
{"title":"Mapping a path to the beyond-CMOS technology for computation","authors":"I. Young","doi":"10.1109/DRC.2012.6256942","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256942","url":null,"abstract":"This paper describes a methodology for benchmarking beyond CMOS exploratory devices for computation using metrics that can provide insights about the device fundamental operation. A more detailed investigation of circuits based upon two beyond-CMOS devices is given in the paper. First tunneling FET (TFET) circuits are compared to low power CMOS circuits. Then the All-Spin Logic device (ASLD) is described and a spin circuit theory based simulator is used to show the functional transient operation of an all spin logic circuit.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"30 1","pages":"3-6"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91317271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257026
A. Itsuno, J. Phillips, S. Velicu
HgCdTe-based infrared (IR) detectors remain the front-runner for high performance IR focal plane array (FPA) applications due to their favorable material and optical properties. While state-of-the-art HgCdTe p-n junction technology such as the double layer planar heterostructure (DLPH) devices can achieve near theoretical performance in the mid-wave and long-wave infrared (MWIR, LWIR) spectral ranges, the cryogenic cooling requirements to suppress dark current are still much greater than desired. HgCdTe material growth by molecular beam epitaxy (MBE) provides the accurate control over alloy composition and doping required to achieve future detector architectures that may serve to reduce dark current for enhanced operation. However, controllable in situ p-type doping of HgCdTe by MBE is still problematic. As a potential solution to address these issues, we propose a unipolar, type-I barrier-integrated HgCdTe nBn IR detector based on similar principles to the type-II nBn structure used in III-V materials [1] with the intent that it may serve as a basis for advanced HgCdTe-based architectures for reduced cooling requirements.
{"title":"Unipolar barrier-integrated HgCdTe infrared detectors","authors":"A. Itsuno, J. Phillips, S. Velicu","doi":"10.1109/DRC.2012.6257026","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257026","url":null,"abstract":"HgCdTe-based infrared (IR) detectors remain the front-runner for high performance IR focal plane array (FPA) applications due to their favorable material and optical properties. While state-of-the-art HgCdTe p-n junction technology such as the double layer planar heterostructure (DLPH) devices can achieve near theoretical performance in the mid-wave and long-wave infrared (MWIR, LWIR) spectral ranges, the cryogenic cooling requirements to suppress dark current are still much greater than desired. HgCdTe material growth by molecular beam epitaxy (MBE) provides the accurate control over alloy composition and doping required to achieve future detector architectures that may serve to reduce dark current for enhanced operation. However, controllable in situ p-type doping of HgCdTe by MBE is still problematic. As a potential solution to address these issues, we propose a unipolar, type-I barrier-integrated HgCdTe nBn IR detector based on similar principles to the type-II nBn structure used in III-V materials [1] with the intent that it may serve as a basis for advanced HgCdTe-based architectures for reduced cooling requirements.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"23 1","pages":"257-258"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90820474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256971
M. Ueda, Y. Kaneko, Y. Nishitani, T. Morie, E. Fujii
A simple synaptic device with a spike-timing-dependent synaptic plasticity (STDP) learning function is a key device that can realize a brain-like processor. STDP is a learning mechanism of synapses in mammalian brains [1]. A memristor [2, 3] is a promising candidate for synaptic devices. However, since the conventional memristor is a two-terminal electric element and the signal magnitude at learning exceeds the processing, it is difficult to realize STDP learning by simultaneously processing the signal. We proposed a unique three-terminal memristor using a ferroelectric thin film [4]. Its three-terminal device structure enables the STDP function without disturbing the signal processing between neurons (Fig. 1). This all oxide memristor (OxiM) has a ferroelectric gate field-effect transistor structure (Fig. 2). Since the polarization of Pb(Zr,Ti)O3 film is changed by applying gate voltage (VG), the channel conductance at the ZnO / Pr(Zr,Ti)O3 interface can be modulated (Fig. 3). Memorized conductance can be maintained without fluctuation [4]. In addition, ferroelectric polarization can be modulated by changing the height and the width of the applied voltage pulse to the gate electrode. Fig. 4 shows the conduction change after applying pulse voltages.
{"title":"Biologically-inspired learning device using three-terminal ferroelectric memristor","authors":"M. Ueda, Y. Kaneko, Y. Nishitani, T. Morie, E. Fujii","doi":"10.1109/DRC.2012.6256971","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256971","url":null,"abstract":"A simple synaptic device with a spike-timing-dependent synaptic plasticity (STDP) learning function is a key device that can realize a brain-like processor. STDP is a learning mechanism of synapses in mammalian brains [1]. A memristor [2, 3] is a promising candidate for synaptic devices. However, since the conventional memristor is a two-terminal electric element and the signal magnitude at learning exceeds the processing, it is difficult to realize STDP learning by simultaneously processing the signal. We proposed a unique three-terminal memristor using a ferroelectric thin film [4]. Its three-terminal device structure enables the STDP function without disturbing the signal processing between neurons (Fig. 1). This all oxide memristor (OxiM) has a ferroelectric gate field-effect transistor structure (Fig. 2). Since the polarization of Pb(Zr,Ti)O3 film is changed by applying gate voltage (VG), the channel conductance at the ZnO / Pr(Zr,Ti)O3 interface can be modulated (Fig. 3). Memorized conductance can be maintained without fluctuation [4]. In addition, ferroelectric polarization can be modulated by changing the height and the width of the applied voltage pulse to the gate electrode. Fig. 4 shows the conduction change after applying pulse voltages.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"31 1","pages":"275-276"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90250491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256964
Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.
{"title":"III–V 4D transistors","authors":"Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye","doi":"10.1109/DRC.2012.6256964","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256964","url":null,"abstract":"We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73687307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257029
Y. P. Chen
Silicon based field effect transistors (FET) have been the foundation of computing industries for decades. As we approach the end of the Moore's law scaling, there have been increasing interests and efforts to explore transistors based on many "emerging" (non-Si) materials that may replace or supplement Si in future electronics and computing devices. However, Si and Si-MOSFETs remain exceptionally competitive and hard to beat by most "emerging" contenders. On the other hand, many of the non-Si based "emerging transistors" have novel physical properties that may make them highly attractive for various non-computing applications. In this talk, I will discuss transistors based on graphene and topological insulators, two classes of materials that have attracted much recent attention in physics and nanoelectronics communities. While both materials feature many novel electronic properties related to the unique Dirac electronic bandstructure, the lack of band gap brings challenges in applying them as digital electronic switches in conventional computing applications. After a brief review of graphene and TI based transistors and their prospects for digital computing applications, I will focus on two examples of exploiting the unique physical properties of these transistors for non-computing applications, particularly sensing and energy conversion.
{"title":"Graphene and topological insulator based transistors: Beyond computing applications","authors":"Y. P. Chen","doi":"10.1109/DRC.2012.6257029","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257029","url":null,"abstract":"Silicon based field effect transistors (FET) have been the foundation of computing industries for decades. As we approach the end of the Moore's law scaling, there have been increasing interests and efforts to explore transistors based on many \"emerging\" (non-Si) materials that may replace or supplement Si in future electronics and computing devices. However, Si and Si-MOSFETs remain exceptionally competitive and hard to beat by most \"emerging\" contenders. On the other hand, many of the non-Si based \"emerging transistors\" have novel physical properties that may make them highly attractive for various non-computing applications. In this talk, I will discuss transistors based on graphene and topological insulators, two classes of materials that have attracted much recent attention in physics and nanoelectronics communities. While both materials feature many novel electronic properties related to the unique Dirac electronic bandstructure, the lack of band gap brings challenges in applying them as digital electronic switches in conventional computing applications. After a brief review of graphene and TI based transistors and their prospects for digital computing applications, I will focus on two examples of exploiting the unique physical properties of these transistors for non-computing applications, particularly sensing and energy conversion.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"37 1","pages":"37-38"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74943804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256925
K. Maezawa, T. Ito, A. Kadoda, K. Nakayama, Y. Yasui, M. Mori, E. Miyazaki, T. Mizutani
The fabrication and the properties of Al2O3-InSb-Si QW MOSFETs having an ultra thin InSb channel layer is reported. The good characteristic of ID-VD with an transconductance of 67 mS/mm demonstrates that the ultra thin InSb channel layer grown directly on Si can be used for MOSFET channels. The results show that the InSb/Si pseudomorphic quantum well MOSFETs is a promising candidate for future VLSIs.
{"title":"Al2O3/InSb/Si quantum well MOSFETs having an ultra-thin InSb layer","authors":"K. Maezawa, T. Ito, A. Kadoda, K. Nakayama, Y. Yasui, M. Mori, E. Miyazaki, T. Mizutani","doi":"10.1109/DRC.2012.6256925","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256925","url":null,"abstract":"The fabrication and the properties of Al2O3-InSb-Si QW MOSFETs having an ultra thin InSb channel layer is reported. The good characteristic of ID-VD with an transconductance of 67 mS/mm demonstrates that the ultra thin InSb channel layer grown directly on Si can be used for MOSFET channels. The results show that the InSb/Si pseudomorphic quantum well MOSFETs is a promising candidate for future VLSIs.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"10 1","pages":"45-46"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75787113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256938
S. Banerjee, L. Register, E. Tutuc, D. Reddy, S. Kim, D. Basu, C. Corbet, L. Colombo, G. Carpenter, A. Macdonald
In this paper, bilayer pseudospin FET (BiSFET) is fabricated and tested for the condensate using Coulomb drag measurements in the double layer graphene system. The basic BiSFET structure can also be used as 2D-2D single particle tunnel FET, and the single particle h-h and e-e 2D-2D tunnel FETs, which is graphene's single-atom thickness could lead to more ideal interlayer tunneling characteristics provided the layers can be aligned. Single particle tunneling current calculations have been performed which show NDR characteristics, reminiscent of the BiSFET, albeit with higher operating powers.
{"title":"Novel double layer graphene transistors-bilayer pseudospin FETs and 2D-2D tunnel FETs","authors":"S. Banerjee, L. Register, E. Tutuc, D. Reddy, S. Kim, D. Basu, C. Corbet, L. Colombo, G. Carpenter, A. Macdonald","doi":"10.1109/DRC.2012.6256938","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256938","url":null,"abstract":"In this paper, bilayer pseudospin FET (BiSFET) is fabricated and tested for the condensate using Coulomb drag measurements in the double layer graphene system. The basic BiSFET structure can also be used as 2D-2D single particle tunnel FET, and the single particle h-h and e-e 2D-2D tunnel FETs, which is graphene's single-atom thickness could lead to more ideal interlayer tunneling characteristics provided the layers can be aligned. Single particle tunneling current calculations have been performed which show NDR characteristics, reminiscent of the BiSFET, albeit with higher operating powers.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"517 1","pages":"27-28"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77134281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256955
S. Avasthi, W. McClain, J. Schwartz, J. Sturm
Narrow bandgap heterojunctions on crystalline silicon such as Si/Si1-xGex are now in widespread use, but to date there has been little progress on widegap heterojunctions on silicon. In this abstract, we report: (i) TiO2/Si heterojunction with a band alignment which blocks holes from silicon but freely passes electrons, and (ii) the application of this heterojunction to form a photovoltaic cell on silicon with no p-n junction, and all fabrication below a temperature of 75 °C.
{"title":"Hole-blocking TiO2/silicon heterojunction for silicon photovoltaics","authors":"S. Avasthi, W. McClain, J. Schwartz, J. Sturm","doi":"10.1109/DRC.2012.6256955","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256955","url":null,"abstract":"Narrow bandgap heterojunctions on crystalline silicon such as Si/Si1-xGex are now in widespread use, but to date there has been little progress on widegap heterojunctions on silicon. In this abstract, we report: (i) TiO2/Si heterojunction with a band alignment which blocks holes from silicon but freely passes electrons, and (ii) the application of this heterojunction to form a photovoltaic cell on silicon with no p-n junction, and all fabrication below a temperature of 75 °C.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"9 1","pages":"93-94"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78284040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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