Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256974
M. Ebrish, S. Koester
The temperature-dependent C-V characteristics for two samples with target HfO2 thicknesses of 20 nm (sample A), and 10 nm (sample B) are shown in Figs. 2 and 3. The results show that the capacitance tuning range increases with decreasing HfO2 thicknesses, as expected. A comparison of the normalized C-V curves for both samples at room temperature is shown in Fig. 4. The capacitance tuning range from Vg - VDirac = 0 to +1.5 V is 1.17:1 for sample A and 1.38:1 for sample B. Fig. 5 shows a comparison of the C-V characteristics for the varactors with MIM capacitors fabricated on the same sample. A very consistent trend is observed where the capacitance-per-unit-area for the MIM capacitors is significantly higher than for the varactors. The EOT values extracted from the MIM capacitors are found to be 4.1 nm and 2.7 nm for samples A and B, respectively. In order to understand this behavior in more detail, numerical modeling was performed on the temperature-dependent C-V characteristics where the random potential fluctuations, σ, in the graphene was used as an adjustable fitting parameter [5]. The results are shown in Fig. 6. The fact that the fitted EOT values cannot completely account for the capacitance reduction in Fig. 5 is a strong indicator that the effective device area of the varactors is less than the layout area. However, additional modeling, particularly taking into account the effect of interface traps, and other imperfections between the graphene and HfO2 [6-7] is needed to fully understand the observed behavior. In the future, further scaling of the EOT needs to be investigated, as well as fabrication of the devices on insulating substrates for eventual use in resonator circuits. As a preliminary demonstration (Fig. 7), we have fabricated a single-finger varactor on a quartz substrate, with EOT (as determined by MIM capacitors) of 1.9 nm and tuning range >;1.5:1 at room temperature.
{"title":"Dielectric thickness dependence of quantum capacitance in graphene varactors with local metal back gates","authors":"M. Ebrish, S. Koester","doi":"10.1109/DRC.2012.6256974","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256974","url":null,"abstract":"The temperature-dependent C-V characteristics for two samples with target HfO2 thicknesses of 20 nm (sample A), and 10 nm (sample B) are shown in Figs. 2 and 3. The results show that the capacitance tuning range increases with decreasing HfO2 thicknesses, as expected. A comparison of the normalized C-V curves for both samples at room temperature is shown in Fig. 4. The capacitance tuning range from Vg - VDirac = 0 to +1.5 V is 1.17:1 for sample A and 1.38:1 for sample B. Fig. 5 shows a comparison of the C-V characteristics for the varactors with MIM capacitors fabricated on the same sample. A very consistent trend is observed where the capacitance-per-unit-area for the MIM capacitors is significantly higher than for the varactors. The EOT values extracted from the MIM capacitors are found to be 4.1 nm and 2.7 nm for samples A and B, respectively. In order to understand this behavior in more detail, numerical modeling was performed on the temperature-dependent C-V characteristics where the random potential fluctuations, σ, in the graphene was used as an adjustable fitting parameter [5]. The results are shown in Fig. 6. The fact that the fitted EOT values cannot completely account for the capacitance reduction in Fig. 5 is a strong indicator that the effective device area of the varactors is less than the layout area. However, additional modeling, particularly taking into account the effect of interface traps, and other imperfections between the graphene and HfO2 [6-7] is needed to fully understand the observed behavior. In the future, further scaling of the EOT needs to be investigated, as well as fabrication of the devices on insulating substrates for eventual use in resonator circuits. As a preliminary demonstration (Fig. 7), we have fabricated a single-finger varactor on a quartz substrate, with EOT (as determined by MIM capacitors) of 1.9 nm and tuning range >;1.5:1 at room temperature.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"7 1","pages":"105-106"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85942949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256965
K. Shepard
Biomolecular systems are traditionally studied using ensemble measurements and fluorescence-based detection. Among the most common in vitro applications are DNA microarrays to identify target gene expression profiles [1] and enzyme-linked immunosorbent assays (ELISA) to identify proteins [2]. While much can be determined with ensemble measurements, scientific and technological interest is rapidly moving to single-molecule techniques. When probing at the single-molecule level, observations can be made about the inter- and intramolecular dynamics that are usually hidden in ensemble measurements. In molecular diagnostic, single-molecule techniques often do not require amplification and simplify sample preparation. The most popular single-molecule techniques based on fluorescence [3, 4] are fundamentally limited in resolution and bandwidth by the countable number of photons emitted by a single fluorophore (typically on the order of 2500 photons/sec). Instrumentation is complex, expensive, and large-form-factor. Furthermore, most optical probes photobleach, limiting observation times and pump powers. Single-molecule measurements of the kinetics of fast biomolecular processes are often unavailable through fluorescent techniques, as they lack the required temporal resolution.
{"title":"Solid-state electronics and single-molecule biophysics","authors":"K. Shepard","doi":"10.1109/DRC.2012.6256965","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256965","url":null,"abstract":"Biomolecular systems are traditionally studied using ensemble measurements and fluorescence-based detection. Among the most common in vitro applications are DNA microarrays to identify target gene expression profiles [1] and enzyme-linked immunosorbent assays (ELISA) to identify proteins [2]. While much can be determined with ensemble measurements, scientific and technological interest is rapidly moving to single-molecule techniques. When probing at the single-molecule level, observations can be made about the inter- and intramolecular dynamics that are usually hidden in ensemble measurements. In molecular diagnostic, single-molecule techniques often do not require amplification and simplify sample preparation. The most popular single-molecule techniques based on fluorescence [3, 4] are fundamentally limited in resolution and bandwidth by the countable number of photons emitted by a single fluorophore (typically on the order of 2500 photons/sec). Instrumentation is complex, expensive, and large-form-factor. Furthermore, most optical probes photobleach, limiting observation times and pump powers. Single-molecule measurements of the kinetics of fast biomolecular processes are often unavailable through fluorescent techniques, as they lack the required temporal resolution.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"11 1","pages":"7-8"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85648410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256962
Guowang Li, Ronghua Wang, J. Verma, H. Xing, D. Jena
Ultra-thin body (UTB) devices with tight electrostatic and quantum confinement of charge carriers have been well developed in highly scaled silicon CMOS technology. For adopting such advanced methods, III-nitrides can benefit immensely from epitaxial AlN as the substrate platform, in contrast to conventional GaN-based substrate platform. With its large polarization charge, wide bandgap and large band offsets, AlN induces the maximal carrier densities while providing the best confinement for nitride channels of all compositions. Such devices stand also to benefit from the symmetry of electronic polarization: high density hole gases can be generated in much the same way as the high density 2DEG in GaN HEMTs, thus enabling p-channel FETs on the same material platform in a logical manner. The AlN/GaN heterojunctions where mobile carriers are located are epitaxial, and excellent transport properties are expected as opposed to the rougher oxide-semiconductor interfaces. Furthermore, AlN is an excellent electrical insulator but simultaneously an excellent thermal conductor, which makes it highly attractive to act as back-barrier and to lower junction temperatures in high power devices by efficient heat dissipation. There have been reports on relaxed GaN n-channel FETs (nFETs) on AlN [1, 2] and III-nitride based p-channel field effect transistors (pFETs) [3, 4]. All the prior work uses relaxed GaN as the channel, and strained GaN channels on AlN have not been explored before. In this work we demonstrate UTB GaN nFETs [5] and pFETs on AlN grown by molecular beam epitaxy (MBE) as the first step towards complementary logic and high power applications.
{"title":"Ultra-thin Body GaN-on-insulator nFETs and pFETs: Towards III-nitride complementary logic","authors":"Guowang Li, Ronghua Wang, J. Verma, H. Xing, D. Jena","doi":"10.1109/DRC.2012.6256962","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256962","url":null,"abstract":"Ultra-thin body (UTB) devices with tight electrostatic and quantum confinement of charge carriers have been well developed in highly scaled silicon CMOS technology. For adopting such advanced methods, III-nitrides can benefit immensely from epitaxial AlN as the substrate platform, in contrast to conventional GaN-based substrate platform. With its large polarization charge, wide bandgap and large band offsets, AlN induces the maximal carrier densities while providing the best confinement for nitride channels of all compositions. Such devices stand also to benefit from the symmetry of electronic polarization: high density hole gases can be generated in much the same way as the high density 2DEG in GaN HEMTs, thus enabling p-channel FETs on the same material platform in a logical manner. The AlN/GaN heterojunctions where mobile carriers are located are epitaxial, and excellent transport properties are expected as opposed to the rougher oxide-semiconductor interfaces. Furthermore, AlN is an excellent electrical insulator but simultaneously an excellent thermal conductor, which makes it highly attractive to act as back-barrier and to lower junction temperatures in high power devices by efficient heat dissipation. There have been reports on relaxed GaN n-channel FETs (nFETs) on AlN [1, 2] and III-nitride based p-channel field effect transistors (pFETs) [3, 4]. All the prior work uses relaxed GaN as the channel, and strained GaN channels on AlN have not been explored before. In this work we demonstrate UTB GaN nFETs [5] and pFETs on AlN grown by molecular beam epitaxy (MBE) as the first step towards complementary logic and high power applications.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"19 1","pages":"153-154"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85112817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256990
H. Liu, D. Mohata, A. Nidhi, V. Saripalli, V. Narayanan, S. Datta
A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.
{"title":"Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications","authors":"H. Liu, D. Mohata, A. Nidhi, V. Saripalli, V. Narayanan, S. Datta","doi":"10.1109/DRC.2012.6256990","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256990","url":null,"abstract":"A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"16 1","pages":"233-234"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80097856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257008
B. Radisavljevic, Daria Krasnozhon, M. Whitwick, A. Kis
Two-dimensional crystals offer several inherent advantages over conventional 3D electronic materials or 1D nanomaterials such as nanotubes and nanowires. Their planar geometry makes it easier to fabricate circuits and complex structures by tailoring 2D layers into desired shapes. Because of their atomic scale thickness, 2D materials also represent the ultimate limit of miniaturization in the vertical dimension and allow the fabrication of shorter transistors due to enhanced electrostatic control. Another advantage of 2D semiconductors is that their electronic properties (band gap, mobility, work function) can be tuned for example by changing the number of layers or applying external electric fields.
{"title":"MoS2-based devices and circuits","authors":"B. Radisavljevic, Daria Krasnozhon, M. Whitwick, A. Kis","doi":"10.1109/DRC.2012.6257008","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257008","url":null,"abstract":"Two-dimensional crystals offer several inherent advantages over conventional 3D electronic materials or 1D nanomaterials such as nanotubes and nanowires. Their planar geometry makes it easier to fabricate circuits and complex structures by tailoring 2D layers into desired shapes. Because of their atomic scale thickness, 2D materials also represent the ultimate limit of miniaturization in the vertical dimension and allow the fabrication of shorter transistors due to enhanced electrostatic control. Another advantage of 2D semiconductors is that their electronic properties (band gap, mobility, work function) can be tuned for example by changing the number of layers or applying external electric fields.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"72 1","pages":"179-180"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75064180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256955
S. Avasthi, W. McClain, J. Schwartz, J. Sturm
Narrow bandgap heterojunctions on crystalline silicon such as Si/Si1-xGex are now in widespread use, but to date there has been little progress on widegap heterojunctions on silicon. In this abstract, we report: (i) TiO2/Si heterojunction with a band alignment which blocks holes from silicon but freely passes electrons, and (ii) the application of this heterojunction to form a photovoltaic cell on silicon with no p-n junction, and all fabrication below a temperature of 75 °C.
{"title":"Hole-blocking TiO2/silicon heterojunction for silicon photovoltaics","authors":"S. Avasthi, W. McClain, J. Schwartz, J. Sturm","doi":"10.1109/DRC.2012.6256955","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256955","url":null,"abstract":"Narrow bandgap heterojunctions on crystalline silicon such as Si/Si1-xGex are now in widespread use, but to date there has been little progress on widegap heterojunctions on silicon. In this abstract, we report: (i) TiO2/Si heterojunction with a band alignment which blocks holes from silicon but freely passes electrons, and (ii) the application of this heterojunction to form a photovoltaic cell on silicon with no p-n junction, and all fabrication below a temperature of 75 °C.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"9 1","pages":"93-94"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78284040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257009
B. Song, B. Sensale‐Rodriguez, Ronghua Wang, A. Ketterson, M. Schuette, E. Beam, P. Saunier, Xiang Gao, Shiping Guo, P. Fay, D. Jena, H. Xing
Although recent years have seen impressive progress on high speed GaN HEMTs [1-3], fabrication approaches allowing for monolithic integration of E and D-mode devices with simplicity and low-cost, such as gate recess and plasma treatment, remain challenging. Carrier mobility in channels subject to gate recess or plasma treatment generally degrades, which is difficult to fully recover even after post-processing annealing etc. In this work, we report high-performance monolithically integrated D-mode and gate-recessed E-mode InAlN/AlN/GaN HEMTs with a nominal gate length of 30 nm (Fig. 1) and 2-level metal interconnects. The D-mode HEMTs show an extrinsic gm of 920 mS/mm and ft/fmax of 194/220 GHz. The gate-recessed E-modes show an extrinsic gm of 1306 mS/mm and ft/fmax of 225/250 GHz. The higher speed of the E-modes stems from the higher intrinsic gm, which is also found to be comparable to that reported in epitaxially defined E-modes with a 4.5 nm barrier and 20-nm gate length by Shinohara et al. [1], ~ 1700 mS/mm, suggesting that the carrier mobility likely suffers from negligible degradation in our monolithically integrated E-mode HEMTs.
{"title":"Monolithically integrated E/D-mode InAlN HEMTs with ƒt/ƒmax > 200/220 GHz","authors":"B. Song, B. Sensale‐Rodriguez, Ronghua Wang, A. Ketterson, M. Schuette, E. Beam, P. Saunier, Xiang Gao, Shiping Guo, P. Fay, D. Jena, H. Xing","doi":"10.1109/DRC.2012.6257009","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257009","url":null,"abstract":"Although recent years have seen impressive progress on high speed GaN HEMTs [1-3], fabrication approaches allowing for monolithic integration of E and D-mode devices with simplicity and low-cost, such as gate recess and plasma treatment, remain challenging. Carrier mobility in channels subject to gate recess or plasma treatment generally degrades, which is difficult to fully recover even after post-processing annealing etc. In this work, we report high-performance monolithically integrated D-mode and gate-recessed E-mode InAlN/AlN/GaN HEMTs with a nominal gate length of 30 nm (Fig. 1) and 2-level metal interconnects. The D-mode HEMTs show an extrinsic gm of 920 mS/mm and ft/fmax of 194/220 GHz. The gate-recessed E-modes show an extrinsic gm of 1306 mS/mm and ft/fmax of 225/250 GHz. The higher speed of the E-modes stems from the higher intrinsic gm, which is also found to be comparable to that reported in epitaxially defined E-modes with a 4.5 nm barrier and 20-nm gate length by Shinohara et al. [1], ~ 1700 mS/mm, suggesting that the carrier mobility likely suffers from negligible degradation in our monolithically integrated E-mode HEMTs.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78592244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256964
Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.
{"title":"III–V 4D transistors","authors":"Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye","doi":"10.1109/DRC.2012.6256964","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256964","url":null,"abstract":"We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73687307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257004
A. Hosalli, P. Frajtag, D. Van Den Broeck, T. Paskova, N. El-Masry, S. Bedair
Over the last decade, considerable efforts have gone into researching techniques to improve the efficiency of light emitting diodes (LEDs) based on the III-nitride material system. These efforts can be classified into two main approaches : improving the internal quantum efficiency (IQE) and increasing the light extraction efficiency of the LED devices. In the work outlined below, we demonstrate a unique LED structure that has a significantly enhanced light output intensity compared to c-plane LEDs by tackling both approaches simultaneously. We investigated the ratio of light output intensity of the NWs LED vs the c-plane LED as a function of current density. At lower current densities, the lower QCSE in NWs LED is responsible for a large ratio. This reduces with increasing current density as carrier screening of the polarization field in the c-plane LED negates the QCSE effect. The ratio saturates at higher current densities where the mechanism for higher light output is dominated by the light extraction efficiency that depends only on the device geometry and is independent of the current density in the NWs LED.
{"title":"Comparative study of LEDs conformally overgrown on multi-facet GaN NWs vs. conventional c-plane LEDs","authors":"A. Hosalli, P. Frajtag, D. Van Den Broeck, T. Paskova, N. El-Masry, S. Bedair","doi":"10.1109/DRC.2012.6257004","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257004","url":null,"abstract":"Over the last decade, considerable efforts have gone into researching techniques to improve the efficiency of light emitting diodes (LEDs) based on the III-nitride material system. These efforts can be classified into two main approaches : improving the internal quantum efficiency (IQE) and increasing the light extraction efficiency of the LED devices. In the work outlined below, we demonstrate a unique LED structure that has a significantly enhanced light output intensity compared to c-plane LEDs by tackling both approaches simultaneously. We investigated the ratio of light output intensity of the NWs LED vs the c-plane LED as a function of current density. At lower current densities, the lower QCSE in NWs LED is responsible for a large ratio. This reduces with increasing current density as carrier screening of the polarization field in the c-plane LED negates the QCSE effect. The ratio saturates at higher current densities where the mechanism for higher light output is dominated by the light extraction efficiency that depends only on the device geometry and is independent of the current density in the NWs LED.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"41 1","pages":"141-142"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81209892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257001
J. Sanz-Robinson, W. Rieutort-Louis, N. Verma, S. Wagner, J. Sturm
Schottky diodes can play a valuable role as rectifiers in Large-Area Electronics (LAE) systems and circuits. They can be used to recover a DC signal when an AC carrier is used to transmit signals between adjacent plastic electronic sheets through near-field wireless coupling [1], rectify DC power after AC transmission between sheets to provide power to sensors, and so forth. In this paper we describe: 1) the intrinsic frequency limits of Schottky diodes fabricated on hydrogenated amorphous silicon (a-Si:H); 2) circuit design strategies for using the diodes at frequencies far beyond their intrinsic limits; 3) and the application of these strategies to demonstrate, to the best of out knowledge, the first amorphous silicon (a-Si:H) full-wave rectifier, with an AC-to-DC power conversion efficiency (PCE) ranging from approximately 46% at 200 Hz to greater than 10 % at 1 MHz.
{"title":"Frequency dependence of amorphous silicon Schottky diodes for Large-Area rectification applications","authors":"J. Sanz-Robinson, W. Rieutort-Louis, N. Verma, S. Wagner, J. Sturm","doi":"10.1109/DRC.2012.6257001","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257001","url":null,"abstract":"Schottky diodes can play a valuable role as rectifiers in Large-Area Electronics (LAE) systems and circuits. They can be used to recover a DC signal when an AC carrier is used to transmit signals between adjacent plastic electronic sheets through near-field wireless coupling [1], rectify DC power after AC transmission between sheets to provide power to sensors, and so forth. In this paper we describe: 1) the intrinsic frequency limits of Schottky diodes fabricated on hydrogenated amorphous silicon (a-Si:H); 2) circuit design strategies for using the diodes at frequencies far beyond their intrinsic limits; 3) and the application of these strategies to demonstrate, to the best of out knowledge, the first amorphous silicon (a-Si:H) full-wave rectifier, with an AC-to-DC power conversion efficiency (PCE) ranging from approximately 46% at 200 Hz to greater than 10 % at 1 MHz.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"14 1","pages":"135-136"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81632378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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