Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831844
R. Pendse
Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.
{"title":"Overview of embedded packaging technologies","authors":"R. Pendse","doi":"10.1109/IITC.2014.6831844","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831844","url":null,"abstract":"Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"48 1","pages":"97-98"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75464577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831869
H. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, Daniel Smith, Dingyou Zhang, Shan Gao
This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.
{"title":"Challenges to via middle TSV integration at sub-28nm nodes","authors":"H. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, Daniel Smith, Dingyou Zhang, Shan Gao","doi":"10.1109/IITC.2014.6831869","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831869","url":null,"abstract":"This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"8 1","pages":"199-202"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82449454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831868
K. Sankaran, S. Clima, M. Mees, C. Adelmann, Z. Tokei, G. Pourtois
The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.
基于第一性原理模拟和固有体积电阻率和电迁移的基准，对互连应用中铜和钨的替代金属的性质进行了综述。
{"title":"Exploring alternative metals to Cu and W for interconnects: An ab initio insight","authors":"K. Sankaran, S. Clima, M. Mees, C. Adelmann, Z. Tokei, G. Pourtois","doi":"10.1109/IITC.2014.6831868","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831868","url":null,"abstract":"The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"4 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88902258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831832
Zhiqiang Wei, T. Ninomiya, S. Muraoka, K. Katayama, R. Yasuhara, T. Mikawa
Taking advantage of electron hopping between oxygen vacancies in filaments, ReRAM switching is caused by oxygen vacancy migration. We have developed an oxygen diffusion retention model, based on this switching mechanism, for both typical bits and outlier bits. Degradation of resistance of typical bits is due to the oxygen vacancy profile in the filament changing during oxygen diffusion, and the retention failure of outlier bits is caused by the critical percolation path being broken within the filament during oxygen diffusion.
{"title":"Switching and reliability mechanisms for ReRAM","authors":"Zhiqiang Wei, T. Ninomiya, S. Muraoka, K. Katayama, R. Yasuhara, T. Mikawa","doi":"10.1109/IITC.2014.6831832","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831832","url":null,"abstract":"Taking advantage of electron hopping between oxygen vacancies in filaments, ReRAM switching is caused by oxygen vacancy migration. We have developed an oxygen diffusion retention model, based on this switching mechanism, for both typical bits and outlier bits. Degradation of resistance of typical bits is due to the oxygen vacancy profile in the filament changing during oxygen diffusion, and the retention failure of outlier bits is caused by the critical percolation path being broken within the filament during oxygen diffusion.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"6 1","pages":"349-352"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73060138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831856
D. Yamane, T. Konishi, T. Matsushima, H. Toshiyoshi, K. Machida, K. Masu
This paper reports a novel tri-axis microelectro-mechanical systems (MEMS) capacitive sensor utilizing multi-layer electroplated gold. The high density of gold has enabled us to minimize the Brownian noise and hence to reduce the footprint of the proof mass. To optimize the flexibility of the mechanical springs for tri-axis motions, we have newly developed multi-layered metal spring structures. All the MEMS structures have been made by gold electroplating, used as a post complementary metal-oxide semiconductor (CMOS) process, and thereby the MEMS sensors can be implemented as integrated CMOS-MEMS accelerometers.
{"title":"A tri-axis MEMS capacitive sensor using multi-layered high-density metal for an integrated CMOS-MEMS accelerometer","authors":"D. Yamane, T. Konishi, T. Matsushima, H. Toshiyoshi, K. Machida, K. Masu","doi":"10.1109/IITC.2014.6831856","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831856","url":null,"abstract":"This paper reports a novel tri-axis microelectro-mechanical systems (MEMS) capacitive sensor utilizing multi-layer electroplated gold. The high density of gold has enabled us to minimize the Brownian noise and hence to reduce the footprint of the proof mass. To optimize the flexibility of the mechanical springs for tri-axis motions, we have newly developed multi-layered metal spring structures. All the MEMS structures have been made by gold electroplating, used as a post complementary metal-oxide semiconductor (CMOS) process, and thereby the MEMS sensors can be implemented as integrated CMOS-MEMS accelerometers.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"26 1","pages":"113-116"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79497964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831851
P. Verdonck, Q. Le, M. Krishtab, K. Vanstreels, S. Armini, A. Simone, M. Nguyen, M. Baklanov, S. Van Elshocht
Scaling of the Cu interconnect structures requires low-k materials which also have an adequate Young's modulus (e.g. E > 6 GPa) and good chemical resistance. This last characteristic can be determined through HF wet etching tests. In this paper, different types of low-k films (k-value range: 2.0-2.3; E range: 2 - 9 GPa) were immersed in a 0.5 volume % HF solution. The HF etching behaviour proved to be very dependent on the wetting properties of the film: even with lower Si-CH3 content, the film with highest water contact angle (i.e. most hydrophobic surface) was the most resistant against the HF etching.
{"title":"HF etching mechanisms of advanced low-k films","authors":"P. Verdonck, Q. Le, M. Krishtab, K. Vanstreels, S. Armini, A. Simone, M. Nguyen, M. Baklanov, S. Van Elshocht","doi":"10.1109/IITC.2014.6831851","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831851","url":null,"abstract":"Scaling of the Cu interconnect structures requires low-k materials which also have an adequate Young's modulus (e.g. E > 6 GPa) and good chemical resistance. This last characteristic can be determined through HF wet etching tests. In this paper, different types of low-k films (k-value range: 2.0-2.3; E range: 2 - 9 GPa) were immersed in a 0.5 volume % HF solution. The HF etching behaviour proved to be very dependent on the wetting properties of the film: even with lower Si-CH3 content, the film with highest water contact angle (i.e. most hydrophobic surface) was the most resistant against the HF etching.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"3 1","pages":"155-158"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80988949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831831
A. Ceyhan, Moongon Jung, Shreepad Panth, S. Lim, A. Naeemi
In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make comparisons between the performances of circuit designs that are implemented using these libraries.
{"title":"Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts","authors":"A. Ceyhan, Moongon Jung, Shreepad Panth, S. Lim, A. Naeemi","doi":"10.1109/IITC.2014.6831831","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831831","url":null,"abstract":"In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make comparisons between the performances of circuit designs that are implemented using these libraries.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"43 1","pages":"345-348"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87870982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831880
D. Josell, T. Moffat
Superconformal electrodeposition enables the fabrication of high aspect ratio interconnects that are ubiquitous in microelectronics. The Curvature Enhanced Accelerator Coverage (CEAC) mechanism captures the morphological and kinetic aspects of many “superfilling” processes for Damascene interconnect fabrication [1-4]. Present superfilling copper electrolytes are acidic. Alkaline chemistries might rely on a non-CEAC filling mechanism.
{"title":"Bottom-up copper deposition in alkaline electrolytes","authors":"D. Josell, T. Moffat","doi":"10.1109/IITC.2014.6831880","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831880","url":null,"abstract":"Superconformal electrodeposition enables the fabrication of high aspect ratio interconnects that are ubiquitous in microelectronics. The Curvature Enhanced Accelerator Coverage (CEAC) mechanism captures the morphological and kinetic aspects of many “superfilling” processes for Damascene interconnect fabrication [1-4]. Present superfilling copper electrolytes are acidic. Alkaline chemistries might rely on a non-CEAC filling mechanism.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"306 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77017429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831859
S. Gatineau, Changhee Ko, J. Gatineau, Clément Lansalot-Matras, Chang-Fang Hsiao
A new family of oxygen and fluorine free Nickel (Ni) precursors, which are based on allyl and alkylpyrrolylimine ligands [Ni(allyl)(PCAI-R)], has been developed and evaluated for a Ni metal film with thermal and plasma enhanced ALD using H2/NH3 as a reducing agent. From Ni(allyl)(PCAI-iPr), pure Ni film with very low resistivity (5.3 μO·cm) was obtained at 400°C by PEALD, which is close to the resistivity value of bulk Nickel (5-10 μO·cm) [1].
{"title":"Synthesis and PEALD evaluation of new Nickel precursors","authors":"S. Gatineau, Changhee Ko, J. Gatineau, Clément Lansalot-Matras, Chang-Fang Hsiao","doi":"10.1109/IITC.2014.6831859","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831859","url":null,"abstract":"A new family of oxygen and fluorine free Nickel (Ni) precursors, which are based on allyl and alkylpyrrolylimine ligands [Ni(allyl)(PCAI-R)], has been developed and evaluated for a Ni metal film with thermal and plasma enhanced ALD using H<sub>2</sub>/NH<sub>3</sub> as a reducing agent. From Ni(allyl)(PCAI-iPr), pure Ni film with very low resistivity (5.3 μO·cm) was obtained at 400°C by PEALD, which is close to the resistivity value of bulk Nickel (5-10 μO·cm) [1].","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"24 1","pages":"125-126"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84485849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831860
J. Liao, Y. T. Lai, B. Kuo, P. Gopaladasu, Scott Wang, S. Yao, Kiki Wang, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh
Back-end-of line (BEOL) interconnect scaling has led to the implementation of self-aligned via (SAV) schemes for ≤ 90 nm BEOL pitches [1]. In one implementation of this scheme, a TiN metal hardmask (MHM) is used for the trench pattern definition while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process that enables the use of thin (≤ 15 nm) TiN MHM. Key attributes of the via and trench etching process in a capacitively coupled etch reactor are described to meet physical performance requirements and eliminate tradeoffs between via chain yield and via-to-metal (M2-V1) bridging. Low-k sidewall damage, post-etch wet clean, and metallization are discussed. Finally, the physical etch performance is correlated to the device breakdown voltage (VBD) and time-dependent dielectric breakdown (TDDB) lifetime performance.
线后端(BEOL)互连缩放导致了≤90 nm BEOL间距的自对准通孔(SAV)方案的实现[1]。在该方案的一种实现中，TiN金属硬掩模(MHM)用于沟槽图案定义，而互连过孔使用三层抗蚀剂掩模进行图图化，使过孔与底层沟槽线自对齐[2]。在这项工作中，我们描述了一种SAV蚀刻工艺，可以使用薄(≤15 nm) TiN MHM。描述了电容耦合蚀刻反应器中通孔和沟槽蚀刻工艺的关键属性，以满足物理性能要求，并消除通孔链产率和通孔到金属(M2-V1)桥接之间的权衡。讨论了低k的侧壁损伤、蚀刻后湿清洗和金属化。最后，物理蚀刻性能与器件击穿电压(VBD)和时变介质击穿(TDDB)寿命性能相关。
{"title":"A self-aligned via etch process to increase yield and reliability of 90 nm pitch critical interconnects with ultra-thin TiN hardmask","authors":"J. Liao, Y. T. Lai, B. Kuo, P. Gopaladasu, Scott Wang, S. Yao, Kiki Wang, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh","doi":"10.1109/IITC.2014.6831860","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831860","url":null,"abstract":"Back-end-of line (BEOL) interconnect scaling has led to the implementation of self-aligned via (SAV) schemes for ≤ 90 nm BEOL pitches [1]. In one implementation of this scheme, a TiN metal hardmask (MHM) is used for the trench pattern definition while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process that enables the use of thin (≤ 15 nm) TiN MHM. Key attributes of the via and trench etching process in a capacitively coupled etch reactor are described to meet physical performance requirements and eliminate tradeoffs between via chain yield and via-to-metal (M2-V1) bridging. Low-k sidewall damage, post-etch wet clean, and metallization are discussed. Finally, the physical etch performance is correlated to the device breakdown voltage (VBD) and time-dependent dielectric breakdown (TDDB) lifetime performance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"33 1","pages":"127-130"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80233395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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