Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537356
P. Batude, L. Brunet, C. Fenouillet-Béranger, D. Lattard, F. Andrieu, M. Vinet, L. Brevard, M. Ribotta, B. Previtali, C. Tabone, F. Ponthenier, N. Rambal, P. Sideris, X. Garros, M. Cassé, C. Theodorou, B. Sklénard, J. Lacord, P. Besson, F. Fournel, S. Kerdilès, P. Acosta-Alba, V. Mazzocchi, J. Hartmann, F. Mazen, S. Thuries, O. Billoint, P. Vivet, G. Sicard, G. Cibrario, M. Mouhdach, B. Giraud, CM. Ribotta, V. Lapras
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.
{"title":"Opportunities and challenges brought by 3D-sequential integration","authors":"P. Batude, L. Brunet, C. Fenouillet-Béranger, D. Lattard, F. Andrieu, M. Vinet, L. Brevard, M. Ribotta, B. Previtali, C. Tabone, F. Ponthenier, N. Rambal, P. Sideris, X. Garros, M. Cassé, C. Theodorou, B. Sklénard, J. Lacord, P. Besson, F. Fournel, S. Kerdilès, P. Acosta-Alba, V. Mazzocchi, J. Hartmann, F. Mazen, S. Thuries, O. Billoint, P. Vivet, G. Sicard, G. Cibrario, M. Mouhdach, B. Giraud, CM. Ribotta, V. Lapras","doi":"10.1109/IITC51362.2021.9537356","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537356","url":null,"abstract":"The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"14 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85888582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537369
Yuki Yamada, M. Yahagi, J. Koike
Cu interconnection would face rapid increase in resistivity due to the thick double layer of Ta/TaN. In this paper, we propose a single interlayer having dual function of liner and barrier to replace Ta/TaN. Thermodynamic simulation was employed to explore suitable interlayer materials. Key parameters for material selections included T0 curve, Cu immiscibility with the interlayer, and interface reaction between the interlayer and SiO2. The results confirmed Co–Zr and Co–Ti alloys to be potential candidates for the interlayer as experimentally reported in our previous work.
{"title":"Thermodynamic evaluation of the liner and barrier properties of a single-phase interlayer for advanced Cu interconnections","authors":"Yuki Yamada, M. Yahagi, J. Koike","doi":"10.1109/IITC51362.2021.9537369","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537369","url":null,"abstract":"Cu interconnection would face rapid increase in resistivity due to the thick double layer of Ta/TaN. In this paper, we propose a single interlayer having dual function of liner and barrier to replace Ta/TaN. Thermodynamic simulation was employed to explore suitable interlayer materials. Key parameters for material selections included T0 curve, Cu immiscibility with the interlayer, and interface reaction between the interlayer and SiO2. The results confirmed Co–Zr and Co–Ti alloys to be potential candidates for the interlayer as experimentally reported in our previous work.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"120 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87929039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537376
J. Silomon, J. Gluch, J. Posseckardt, A. Clausner, J. Paul, D. Breuer, E. Zschech
In previous works, the resulting damages in the back end of line (BEoL) stack triggered by Copper pillar (Cu-pillar) shear-off events were evaluated and classified [1]. It was determined, especially by utilizing acoustic emission (AE) measurements, that damage events consist of multiple extremely fast sub-processes. The objective of this work is the development of an approach to enable the identification of the areas of damage initiation and comprehend the damage propagation in a BEoL stack under mechanical load by triggering only the initial sub-processes. Mechanical stress was induced into the BEoL stack utilizing a displacement-controlled sub-critical Cu-pillar loading approach with the approximate parametrization determined in previous experiments [1]. During mechanical loading, AE signals were constantly measured. As soon as significant acoustic events were detected, the experiment was aborted. The occurring damages were analyzed utilizing a customized nano X-ray computed tomography (nXCT) setup and focused ion beam (FIB) milling as well as scanning electron microscopy (SEM) imaging. In this work, a methodology could be developed to enable the evaluation of BEoL damages in an early, sub-critical stage. These results provide a better understanding of the damage formation and propagation in the BEoL stack and enable a design optimization procedure for the most damage prone areas.
{"title":"BEoL Damage Evaluation Utilizing Sub-Critical Cu-Pillar Shear Tests, Acoustic Emission, nXCT, and SEM/FIB Analysis","authors":"J. Silomon, J. Gluch, J. Posseckardt, A. Clausner, J. Paul, D. Breuer, E. Zschech","doi":"10.1109/IITC51362.2021.9537376","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537376","url":null,"abstract":"In previous works, the resulting damages in the back end of line (BEoL) stack triggered by Copper pillar (Cu-pillar) shear-off events were evaluated and classified [1]. It was determined, especially by utilizing acoustic emission (AE) measurements, that damage events consist of multiple extremely fast sub-processes. The objective of this work is the development of an approach to enable the identification of the areas of damage initiation and comprehend the damage propagation in a BEoL stack under mechanical load by triggering only the initial sub-processes. Mechanical stress was induced into the BEoL stack utilizing a displacement-controlled sub-critical Cu-pillar loading approach with the approximate parametrization determined in previous experiments [1]. During mechanical loading, AE signals were constantly measured. As soon as significant acoustic events were detected, the experiment was aborted. The occurring damages were analyzed utilizing a customized nano X-ray computed tomography (nXCT) setup and focused ion beam (FIB) milling as well as scanning electron microscopy (SEM) imaging. In this work, a methodology could be developed to enable the evaluation of BEoL damages in an early, sub-critical stage. These results provide a better understanding of the damage formation and propagation in the BEoL stack and enable a design optimization procedure for the most damage prone areas.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"90 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90673708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831872
K. Takeda, M. Aoki
A three-layer-stacked wafer with CMOS devices was fabricated by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings seamless copper bonding in face-to-face (F2F) and back-to-face (B2F) configurations. The low capacitance of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV.
{"title":"3D integration technology using hybrid wafer bonding and via-last TSV process","authors":"K. Takeda, M. Aoki","doi":"10.1109/IITC.2014.6831872","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831872","url":null,"abstract":"A three-layer-stacked wafer with CMOS devices was fabricated by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings seamless copper bonding in face-to-face (F2F) and back-to-face (B2F) configurations. The low capacitance of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"211-214"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73484982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831900
J. Bogan, A. McCoy, P. Casey, R. O'Connor, C. Byrne, G. Hughes
In this x-ray photoelectron spectroscopy (XPS) study ultra-thin Si and MnO films were deposited on a range of low dielectric constant carbon doped oxides (CDO) with varying carbon content, in order to accurately determine the binding energy (BE) positions of the Si 2p and O 1s core level peaks as a function of carbon concentration. The results show a measurable correlation between carbon content and BE position of both the Si 2p and O 1s core level peaks. Furthermore, it has been shown that the full width at half maximum (FWHM) of the various CDO substrate peaks are significantly larger than for SiO2 making it difficult to unambiguously determine manganese silicate barrier layer formation on these substrates. In a separate set of experiments, the formation of a manganese silicate barrier layer on these CDO substrates following the deposition and high temperature annealing of thin MnO layers is inferred from analysis of the O1s and Mn2p core level spectra.
{"title":"Photoemission study of the impact of carbon content on Mn silicate barrier formation on low-k dielectric materials","authors":"J. Bogan, A. McCoy, P. Casey, R. O'Connor, C. Byrne, G. Hughes","doi":"10.1109/IITC.2014.6831900","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831900","url":null,"abstract":"In this x-ray photoelectron spectroscopy (XPS) study ultra-thin Si and MnO films were deposited on a range of low dielectric constant carbon doped oxides (CDO) with varying carbon content, in order to accurately determine the binding energy (BE) positions of the Si 2p and O 1s core level peaks as a function of carbon concentration. The results show a measurable correlation between carbon content and BE position of both the Si 2p and O 1s core level peaks. Furthermore, it has been shown that the full width at half maximum (FWHM) of the various CDO substrate peaks are significantly larger than for SiO2 making it difficult to unambiguously determine manganese silicate barrier layer formation on these substrates. In a separate set of experiments, the formation of a manganese silicate barrier layer on these CDO substrates following the deposition and high temperature annealing of thin MnO layers is inferred from analysis of the O1s and Mn2p core level spectra.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"87 1","pages":"331-334"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73879816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831883
D. Kopp, M. A. Khan, G. Bernstein, P. Fay
Ultra-broadband chip-to-chip interconnects at high frequencies are demonstrated. These interconnects, based on the Quilt Packaging (QP) approach, appear to be promising for applications in millimeter-wave circuits due to their extremely wide bandwidth and ease of assembly. The performance of chip-to-chip interconnects in a 50 Ω coplanar waveguide environment on high-resistivity silicon substrates has been measured to 220 GHz using a vector network analyzer, and is compared with projections obtained from 3D electromagnetic modeling. Single-mode, resonance-free operation is demonstrated through 220 GHz, with insertion loss below 1.5 dB over the full frequency range. Although the resistance of the conductive epoxy (used for the prototypes reported here) limits the performance of the QP nodules, simulations indicate that better joining methods such as soldering promise to yield insertion loss of much less than 1 dB at 220 GHz.
{"title":"Ultra-broadband chip-to-chip interconnects to 220 GHz for Si-based millimeter-wave systems","authors":"D. Kopp, M. A. Khan, G. Bernstein, P. Fay","doi":"10.1109/IITC.2014.6831883","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831883","url":null,"abstract":"Ultra-broadband chip-to-chip interconnects at high frequencies are demonstrated. These interconnects, based on the Quilt Packaging (QP) approach, appear to be promising for applications in millimeter-wave circuits due to their extremely wide bandwidth and ease of assembly. The performance of chip-to-chip interconnects in a 50 Ω coplanar waveguide environment on high-resistivity silicon substrates has been measured to 220 GHz using a vector network analyzer, and is compared with projections obtained from 3D electromagnetic modeling. Single-mode, resonance-free operation is demonstrated through 220 GHz, with insertion loss below 1.5 dB over the full frequency range. Although the resistance of the conductive epoxy (used for the prototypes reported here) limits the performance of the QP nodules, simulations indicate that better joining methods such as soldering promise to yield insertion loss of much less than 1 dB at 220 GHz.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"28 1","pages":"293-296"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75555130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831886
Zhong Guan, M. Marek-Sadowska, S. Nassif, Baozhen Li
In this paper, we study electromigration (EM) reliability of signal lines. We propose a general model for current conversion from pulsed DC to steady DC based on the consistency of maximal atomic flux divergence. Both long and short lead lines with high frequency current are considered. The calculated effective steady DC agrees with the measured results. Our conversion scheme can be applied also to signal lines with complex current paths.
{"title":"Atomic flux divergence based current conversion scheme for signal line electromigration reliability assessment","authors":"Zhong Guan, M. Marek-Sadowska, S. Nassif, Baozhen Li","doi":"10.1109/IITC.2014.6831886","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831886","url":null,"abstract":"In this paper, we study electromigration (EM) reliability of signal lines. We propose a general model for current conversion from pulsed DC to steady DC based on the consistency of maximal atomic flux divergence. Both long and short lead lines with high frequency current are considered. The calculated effective steady DC agrees with the measured results. Our conversion scheme can be applied also to signal lines with complex current paths.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"9 1","pages":"245-248"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82557737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831864
Kevin L. Lin, C. Carver, R. Chebiam, J. Clarke, Jacob Faber, M. Harmes, T. Indukuri, C. Jezewski, M. Kobrinsky, B. Krist, Narendra V. Lakamraju, H. Lang, A. Myers, J. Plombon, K. Singh, H. Yoo
A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.
为了模拟金属屏障和介质在一个整体结构中的加工条件，研制了一种侧壁平面电容器(SW CAP)车辆。对于已知的低k介电介质上铜的钽屏障，SW CAP TDDB与在集成车辆上测量的TDDB相似。SW CAP结果可用于比较不同介质系统的电气可靠性，并可用于确定铜金属屏障的物理连续性。
{"title":"Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films","authors":"Kevin L. Lin, C. Carver, R. Chebiam, J. Clarke, Jacob Faber, M. Harmes, T. Indukuri, C. Jezewski, M. Kobrinsky, B. Krist, Narendra V. Lakamraju, H. Lang, A. Myers, J. Plombon, K. Singh, H. Yoo","doi":"10.1109/IITC.2014.6831864","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831864","url":null,"abstract":"A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"11 1","pages":"177-180"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81994437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831898
S. George
The atomic layer deposition (ALD) of ultrathin and continuous metal films is very challenging. This paper describes a general procedure that can yield an ultrathin and continuous metal ALD film using a W ALD adhesion layer.
{"title":"Atomic layer deposition of ultrathin and continuous metal films","authors":"S. George","doi":"10.1109/IITC.2014.6831898","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831898","url":null,"abstract":"The atomic layer deposition (ALD) of ultrathin and continuous metal films is very challenging. This paper describes a general procedure that can yield an ultrathin and continuous metal ALD film using a W ALD adhesion layer.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"17 1","pages":"325-326"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90418033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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