Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831873
J. Plawsky, J. Borja, T. Lu, H. Bakhru, R. Rosenberg, W. Gill, T. Shaw, R. Laibowitz, E. Liniger, S. Cohen, G. Bonilla
Summary form only given. The reliability of new ultra-porous low-k materials is often a fascinating and complex tale involving multiple concepts from material science, electrical and chemical engineering. Pursuing an understanding of reliability for novel low-k materials requires the dissection of fundamental mechanisms and phenomena altering the electrical and physical properties of the dielectric matrix. Failure mechanisms can be categorized into two main groups. Intrinsic failure arises from damage to the dielectric matrix due to the transport of charge carriers. Ion catalyzed failure results from the drift of ionic species originating from the metal/dielectric interface. Integration of sub-20nm process technology nodes can be radically advanced by resolving how major failure mechanisms coexist and collaborate to generate dielectric failures. Here, we present a set of dynamic applied field experiments designed to identify changes in the conduction and reliability of dielectric films as result of bias and temperature stress (BTS). It is shown that ionic species originating from the metal/dielectric interface can behave as trapping centers for charge carriers under BTS. Trapping of electrons into ionic centers could increase the scattering of charge carriers which leads to the additional formation of intrinsic defects across the dielectric matrix, thus accelerating intrinsic failure. A mechanism is proposed to describe how leakage current decay at the onset of BTS is related to charge carrier confinement into intrinsic and ionic defects. The kinetics of charge trapping events were found to be consistent with a time-dependent reaction rate constant, k = k0 · (t + 1)β-1 where 0<;β<;1. This formulation leads to a classic, stretched exponential decay rate that we are looking to use to help predict dielectric reliability.
{"title":"Reliability of ultra-porous low-k materials for advanced interconnects","authors":"J. Plawsky, J. Borja, T. Lu, H. Bakhru, R. Rosenberg, W. Gill, T. Shaw, R. Laibowitz, E. Liniger, S. Cohen, G. Bonilla","doi":"10.1109/IITC.2014.6831873","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831873","url":null,"abstract":"Summary form only given. The reliability of new ultra-porous low-k materials is often a fascinating and complex tale involving multiple concepts from material science, electrical and chemical engineering. Pursuing an understanding of reliability for novel low-k materials requires the dissection of fundamental mechanisms and phenomena altering the electrical and physical properties of the dielectric matrix. Failure mechanisms can be categorized into two main groups. Intrinsic failure arises from damage to the dielectric matrix due to the transport of charge carriers. Ion catalyzed failure results from the drift of ionic species originating from the metal/dielectric interface. Integration of sub-20nm process technology nodes can be radically advanced by resolving how major failure mechanisms coexist and collaborate to generate dielectric failures. Here, we present a set of dynamic applied field experiments designed to identify changes in the conduction and reliability of dielectric films as result of bias and temperature stress (BTS). It is shown that ionic species originating from the metal/dielectric interface can behave as trapping centers for charge carriers under BTS. Trapping of electrons into ionic centers could increase the scattering of charge carriers which leads to the additional formation of intrinsic defects across the dielectric matrix, thus accelerating intrinsic failure. A mechanism is proposed to describe how leakage current decay at the onset of BTS is related to charge carrier confinement into intrinsic and ionic defects. The kinetics of charge trapping events were found to be consistent with a time-dependent reaction rate constant, k = k0 · (t + 1)β-1 where 0<;β<;1. This formulation leads to a classic, stretched exponential decay rate that we are looking to use to help predict dielectric reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 1","pages":"217-218"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89384885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831841
Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim
In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.
{"title":"Impact of die partitioning on reliability and yield of 3D DRAM","authors":"Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim","doi":"10.1109/IITC.2014.6831841","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831841","url":null,"abstract":"In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"34 1","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90214970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831836
J. Gambino, R. Graf, J. Malinowski, A. Cote, W. Guthrie, K. Watson, P. Chapman, K. K. Sims, M. D. Levy, T. Aoki, G. A. Mason, M. Jaffe
RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 μm RF technology.
{"title":"Reliability of segmented edge seal ring for RF devices","authors":"J. Gambino, R. Graf, J. Malinowski, A. Cote, W. Guthrie, K. Watson, P. Chapman, K. K. Sims, M. D. Levy, T. Aoki, G. A. Mason, M. Jaffe","doi":"10.1109/IITC.2014.6831836","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831836","url":null,"abstract":"RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 μm RF technology.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"73 1","pages":"367-370"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831866
D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah
Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.
{"title":"Advanced metal and dielectric barrier cap films for Cu low k interconnects","authors":"D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah","doi":"10.1109/IITC.2014.6831866","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831866","url":null,"abstract":"Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"14 1","pages":"185-188"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84368741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831837
P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
{"title":"3D sequential integration opportunities and technology optimization","authors":"P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet","doi":"10.1109/IITC.2014.6831837","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831837","url":null,"abstract":"Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"45 1","pages":"373-376"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90949561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831846
Moongon Jung, D. Pan, S. Lim
We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.
{"title":"Through-silicon-via material property variation impact on full-chip reliability and timing","authors":"Moongon Jung, D. Pan, S. Lim","doi":"10.1109/IITC.2014.6831846","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831846","url":null,"abstract":"We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"42 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831892
R. Brain, N. Bisnik, H.P. Chen, J. Neulinger, N. Lindert, J. Peach, L. Rockford, Y. Wang, K. Zhang
A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].
{"title":"Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology","authors":"R. Brain, N. Bisnik, H.P. Chen, J. Neulinger, N. Lindert, J. Peach, L. Rockford, Y. Wang, K. Zhang","doi":"10.1109/IITC.2014.6831892","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831892","url":null,"abstract":"A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"54 1","pages":"299-302"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83235808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831901
Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos
Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.
{"title":"Restoration and pore sealing of low-k films by UV-assisted processes","authors":"Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos","doi":"10.1109/IITC.2014.6831901","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831901","url":null,"abstract":"Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"10 1","pages":"335-338"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80807185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831852
H. Fiedler, S. Hermann, M. Rennau, S. Schulz, T. Gessner
We prepared CNT based vias on wafer scale. Based on the electrical characterization we extracted the localization length of the CNTs. While for short CNTs the classical transport regime is valid, the Anderson localization regime applies for longer CNTs. Supplementary the characteristic length scales were estimated based on the structure of the CNTs being in good agreement with the parameters extracted from the electrical measurements.
{"title":"Localization length of integrated multi-walled carbon nanotubes","authors":"H. Fiedler, S. Hermann, M. Rennau, S. Schulz, T. Gessner","doi":"10.1109/IITC.2014.6831852","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831852","url":null,"abstract":"We prepared CNT based vias on wafer scale. Based on the electrical characterization we extracted the localization length of the CNTs. While for short CNTs the classical transport regime is valid, the Anderson localization regime applies for longer CNTs. Supplementary the characteristic length scales were estimated based on the structure of the CNTs being in good agreement with the parameters extracted from the electrical measurements.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"55 1","pages":"159-162"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88174999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831830
T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens
The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.
{"title":"Interconnects scaling challenge for sub-20nm spin torque transfer magnetic random access memory technology","authors":"T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens","doi":"10.1109/IITC.2014.6831830","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831830","url":null,"abstract":"The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"209 1","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88496520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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