Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831852
H. Fiedler, S. Hermann, M. Rennau, S. Schulz, T. Gessner
We prepared CNT based vias on wafer scale. Based on the electrical characterization we extracted the localization length of the CNTs. While for short CNTs the classical transport regime is valid, the Anderson localization regime applies for longer CNTs. Supplementary the characteristic length scales were estimated based on the structure of the CNTs being in good agreement with the parameters extracted from the electrical measurements.
{"title":"Localization length of integrated multi-walled carbon nanotubes","authors":"H. Fiedler, S. Hermann, M. Rennau, S. Schulz, T. Gessner","doi":"10.1109/IITC.2014.6831852","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831852","url":null,"abstract":"We prepared CNT based vias on wafer scale. Based on the electrical characterization we extracted the localization length of the CNTs. While for short CNTs the classical transport regime is valid, the Anderson localization regime applies for longer CNTs. Supplementary the characteristic length scales were estimated based on the structure of the CNTs being in good agreement with the parameters extracted from the electrical measurements.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"55 1","pages":"159-162"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88174999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831836
J. Gambino, R. Graf, J. Malinowski, A. Cote, W. Guthrie, K. Watson, P. Chapman, K. K. Sims, M. D. Levy, T. Aoki, G. A. Mason, M. Jaffe
RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 μm RF technology.
{"title":"Reliability of segmented edge seal ring for RF devices","authors":"J. Gambino, R. Graf, J. Malinowski, A. Cote, W. Guthrie, K. Watson, P. Chapman, K. K. Sims, M. D. Levy, T. Aoki, G. A. Mason, M. Jaffe","doi":"10.1109/IITC.2014.6831836","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831836","url":null,"abstract":"RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 μm RF technology.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"73 1","pages":"367-370"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831846
Moongon Jung, D. Pan, S. Lim
We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.
{"title":"Through-silicon-via material property variation impact on full-chip reliability and timing","authors":"Moongon Jung, D. Pan, S. Lim","doi":"10.1109/IITC.2014.6831846","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831846","url":null,"abstract":"We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"42 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831866
D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah
Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.
{"title":"Advanced metal and dielectric barrier cap films for Cu low k interconnects","authors":"D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah","doi":"10.1109/IITC.2014.6831866","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831866","url":null,"abstract":"Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"14 1","pages":"185-188"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84368741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831841
Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim
In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.
{"title":"Impact of die partitioning on reliability and yield of 3D DRAM","authors":"Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim","doi":"10.1109/IITC.2014.6831841","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831841","url":null,"abstract":"In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"34 1","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90214970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831837
P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
{"title":"3D sequential integration opportunities and technology optimization","authors":"P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet","doi":"10.1109/IITC.2014.6831837","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831837","url":null,"abstract":"Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"45 1","pages":"373-376"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90949561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831901
Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos
Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.
{"title":"Restoration and pore sealing of low-k films by UV-assisted processes","authors":"Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos","doi":"10.1109/IITC.2014.6831901","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831901","url":null,"abstract":"Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"10 1","pages":"335-338"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80807185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831844
R. Pendse
Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.
{"title":"Overview of embedded packaging technologies","authors":"R. Pendse","doi":"10.1109/IITC.2014.6831844","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831844","url":null,"abstract":"Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"48 1","pages":"97-98"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75464577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831888
C. Yang, B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, D. Edelstein
Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.
{"title":"Thermal stress control in Cu interconnects","authors":"C. Yang, B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, D. Edelstein","doi":"10.1109/IITC.2014.6831888","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831888","url":null,"abstract":"Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"148 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74264340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831840
S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah
Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.
{"title":"Foundry TSV integration and manufacturing challenges","authors":"S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah","doi":"10.1109/IITC.2014.6831840","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831840","url":null,"abstract":"Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"385-388"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74594723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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