Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537364
J. Koike, Toshihito Kuge, Linghan Chen, M. Yahagi
We report the recent results of NiAl and CuAl2 intermetallic compounds for advanced-node interconnect materials in place of Cu. Reported results of Co and Ru are briefly reviewed for comparison. CuAl2 can be a good choice in terms of liner-free and barrier-free interconnections having a low resistivity and a good TDDB and EM reliability.
{"title":"Intermetallic Compounds For Interconnect Metal Beyond 3 nm Node","authors":"J. Koike, Toshihito Kuge, Linghan Chen, M. Yahagi","doi":"10.1109/IITC51362.2021.9537364","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537364","url":null,"abstract":"We report the recent results of NiAl and CuAl2 intermetallic compounds for advanced-node interconnect materials in place of Cu. Reported results of Co and Ru are briefly reviewed for comparison. CuAl2 can be a good choice in terms of liner-free and barrier-free interconnections having a low resistivity and a good TDDB and EM reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85790076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537408
Grant Miller, S. Jain, Santosh Kelgeri, Pranav Ranganathan, A. Ceyhan
In this paper, we introduce novel, holistic, electromigration-(EM) and dynamic voltage drop-aware power grid (PG) design and analysis methods that can help resolve the critical limitations that guard-band-driven approaches of today’s modern design closure flows enforce upon physical designers in their quest to achieve the best possible power/performance/area (PPA). These methods can easily be integrated into any existing design flow. The proposed structured strategies to co-optimize inherent trade-offs in PG reliability and PPA improvement can help enable higher transistor density and accurately quantify the impact of IR drop for block-level timing within conventional automatic place-and-route (PnR) flows through the use of an exhaustive, but low-cost in-house solution. We demonstrate up to 9% area savings and up to 5% power reduction while maintaining achievable frequency. The proposed flow updates pave the path for future work to apply our machine-learning-enhanced design space exploration approaches to better control trade-offs between PG reliability and PPA improvement.
{"title":"Novel IR/EM-Aware Power Grid Design and Analysis Methodologies for Optimal PPA at Sub-10nm Technology Nodes","authors":"Grant Miller, S. Jain, Santosh Kelgeri, Pranav Ranganathan, A. Ceyhan","doi":"10.1109/IITC51362.2021.9537408","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537408","url":null,"abstract":"In this paper, we introduce novel, holistic, electromigration-(EM) and dynamic voltage drop-aware power grid (PG) design and analysis methods that can help resolve the critical limitations that guard-band-driven approaches of today’s modern design closure flows enforce upon physical designers in their quest to achieve the best possible power/performance/area (PPA). These methods can easily be integrated into any existing design flow. The proposed structured strategies to co-optimize inherent trade-offs in PG reliability and PPA improvement can help enable higher transistor density and accurately quantify the impact of IR drop for block-level timing within conventional automatic place-and-route (PnR) flows through the use of an exhaustive, but low-cost in-house solution. We demonstrate up to 9% area savings and up to 5% power reduction while maintaining achievable frequency. The proposed flow updates pave the path for future work to apply our machine-learning-enhanced design space exploration approaches to better control trade-offs between PG reliability and PPA improvement.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89244897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2.5D/3D IC packaging and fan-out wafer-level packaging (FOWLP) have attracted much attention both from the academics and industries. In these technologies, the manufacturing of redistribution/rerouting layer (RDL) plays an important role. In this paper, an all-wet, low cost RDL fabrication process is designed and experimentally demonstrated, employing photosensitive polyimide (PSPI) as the dielectric layer and electroless plating for the seed/barrier layers. Using the spin coating technique, the PSPI dielectric layer with uniform thickness is formed on the surface of the substrate, followed by the patterning of mirco-vias and the thermal curing. With the help of O2 plasma cleaning for 10 mins, the residual PSPI at the corners of patterned micro-vias is removed completely and the profiles of the patterned micro-vias are further improved. In addition, the rough surface morphology of PSPI layer after the O2 plasma cleaning is beneficial to enhance the adhesion property of the electroless plated seed/barrier layers, which is verified by the standard cross cut test. Finally, with semi-additive process (SAP), fine-profile RDL with micro-vias is successfully fabricated and presented.
{"title":"An All-Wet, Low Cost RDL Fabrication Process with Electroless Plated Seed/Barrier Layers","authors":"Ziru Cai, Yingtao Ding, Zhaohu Wu, Ziyue Zhang, Yuquan Su, Zhiming Chen","doi":"10.1109/IITC51362.2021.9537437","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537437","url":null,"abstract":"2.5D/3D IC packaging and fan-out wafer-level packaging (FOWLP) have attracted much attention both from the academics and industries. In these technologies, the manufacturing of redistribution/rerouting layer (RDL) plays an important role. In this paper, an all-wet, low cost RDL fabrication process is designed and experimentally demonstrated, employing photosensitive polyimide (PSPI) as the dielectric layer and electroless plating for the seed/barrier layers. Using the spin coating technique, the PSPI dielectric layer with uniform thickness is formed on the surface of the substrate, followed by the patterning of mirco-vias and the thermal curing. With the help of O2 plasma cleaning for 10 mins, the residual PSPI at the corners of patterned micro-vias is removed completely and the profiles of the patterned micro-vias are further improved. In addition, the rough surface morphology of PSPI layer after the O2 plasma cleaning is beneficial to enhance the adhesion property of the electroless plated seed/barrier layers, which is verified by the standard cross cut test. Finally, with semi-additive process (SAP), fine-profile RDL with micro-vias is successfully fabricated and presented.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"402 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87888541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537540
Zhe Wang, Ikumi Ozawa, Y. Susumago, T. Odashima, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima
In order to fabricate a wearable flexible display as a flexible hybrid electronic (FHE) device with micro-LED dies, we demonstrate multi-level metallization on an elastomer using die-first fan-out wafer-level packaging (FOWLP). The elastic substrate of this display is PDMS (polydimethylsiloxane) in which the array of 3-color micro-LEDs is embedded. In this study, we address serious issues such as die shift and stress accumulation in advanced FOWLP to integrate a self-luminescent flexible micro-LED display.
{"title":"Multi-level Metallization on an Elastomer PDMS for FOWLP-based Flexible Hybrid Electronics","authors":"Zhe Wang, Ikumi Ozawa, Y. Susumago, T. Odashima, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima","doi":"10.1109/IITC51362.2021.9537540","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537540","url":null,"abstract":"In order to fabricate a wearable flexible display as a flexible hybrid electronic (FHE) device with micro-LED dies, we demonstrate multi-level metallization on an elastomer using die-first fan-out wafer-level packaging (FOWLP). The elastic substrate of this display is PDMS (polydimethylsiloxane) in which the array of 3-color micro-LEDs is embedded. In this study, we address serious issues such as die shift and stress accumulation in advanced FOWLP to integrate a self-luminescent flexible micro-LED display.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82446443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537391
Bettina Wehring, L. Gerlich, B. Uhlig
This work examines barrier systems of metallization layers made up of novel materials for next generation computing. The diffusion of cobalt into a Ta/Ru as well as a TaN/Ru layer was analyzed by XPS depth profiles after annealing. The diffusion coefficients were estimated by applying the Mixing-Roughness-Information Depth (MRI) model to the concentration profile of cobalt and the activation energy for diffusion was calculated for both materials. Furthermore the thin films were analyzed regarding their crystal structure change upon annealing. Diffusion coefficients of D(Co in Ta/Ru) ~ 6.162e–13 exp(−139.7/RT) m2/s and D(Co in TaN/Ru) ~ 2.9948e–16 exp(−87.63/RT) m2/s were estimated.
这项工作研究了由新材料组成的下一代计算金属化层的屏障系统。利用XPS深度谱分析了退火后钴在Ta/Ru层和TaN/Ru层中的扩散。将混合-粗糙度-信息深度(MRI)模型应用于钴的浓度分布估计了扩散系数，并计算了两种材料的扩散活化能。进一步分析了薄膜在退火过程中晶体结构的变化。估计了D(Co in Ta/Ru) ~ 6.162e-13 exp(−139.7/RT) m2/s和D(Co in TaN/Ru) ~ 2.9948e-16 exp(−87.63/RT) m2/s的扩散系数。
{"title":"XPS Diffusion analysis of Ta(N)/Ru Diffusion Barriers for Cobalt Interconnects","authors":"Bettina Wehring, L. Gerlich, B. Uhlig","doi":"10.1109/IITC51362.2021.9537391","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537391","url":null,"abstract":"This work examines barrier systems of metallization layers made up of novel materials for next generation computing. The diffusion of cobalt into a Ta/Ru as well as a TaN/Ru layer was analyzed by XPS depth profiles after annealing. The diffusion coefficients were estimated by applying the Mixing-Roughness-Information Depth (MRI) model to the concentration profile of cobalt and the activation energy for diffusion was calculated for both materials. Furthermore the thin films were analyzed regarding their crystal structure change upon annealing. Diffusion coefficients of D(Co in Ta/Ru) ~ 6.162e–13 exp(−139.7/RT) m2/s and D(Co in TaN/Ru) ~ 2.9948e–16 exp(−87.63/RT) m2/s were estimated.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76546492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537395
Y. Yoon, Chang-Jo Kim, Junki Jang, K. Sung, H. Kim, Yunki Choi, Jeonghoon Ahn, Won-Chull Han, W. Jang, Rakhwan Kim, Don-Jin Shin, Juheon Kim, Y. Lim, H. Yim, W. Kang, Jongmil Youn
We demonstrate that when a thin ALD (atomic layer deposition) TaN as a barrier metal is deposited to the Cu interconnect, the upper via resistance is significantly increased. We also exhibit that the abnormal upper via resistance is consistent with the N/Ta increase by nitrogen diffusion. To overcome this issue, we investigate a hybrid TaN (PVD TaN on the top of ALD TaN), which prevents the nitrogen diffusion to the bottom of the upper via, resulting in the improvement of the upper via resistance.
{"title":"The via resistance analysis at ALD-to-PVD TaN transition layer","authors":"Y. Yoon, Chang-Jo Kim, Junki Jang, K. Sung, H. Kim, Yunki Choi, Jeonghoon Ahn, Won-Chull Han, W. Jang, Rakhwan Kim, Don-Jin Shin, Juheon Kim, Y. Lim, H. Yim, W. Kang, Jongmil Youn","doi":"10.1109/IITC51362.2021.9537395","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537395","url":null,"abstract":"We demonstrate that when a thin ALD (atomic layer deposition) TaN as a barrier metal is deposited to the Cu interconnect, the upper via resistance is significantly increased. We also exhibit that the abnormal upper via resistance is consistent with the N/Ta increase by nitrogen diffusion. To overcome this issue, we investigate a hybrid TaN (PVD TaN on the top of ALD TaN), which prevents the nitrogen diffusion to the bottom of the upper via, resulting in the improvement of the upper via resistance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"66 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83577156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537543
R. Socha
The resolution concept of k1 is introduced along with various methods to reduce the k1 through resolution enhancement techniques. The edge placement error (EPE) of a 5nm node SRAM is analyzed in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization (SMO), and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matching error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Since SEPE is difficult to reduce, more emphasis needs to be placed on reducing the overlay EPE in order to reduce the total EPE.
{"title":"Analysis of edge placement error (EPE) at the 5nm node and beyond","authors":"R. Socha","doi":"10.1109/IITC51362.2021.9537543","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537543","url":null,"abstract":"The resolution concept of k1 is introduced along with various methods to reduce the k1 through resolution enhancement techniques. The edge placement error (EPE) of a 5nm node SRAM is analyzed in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization (SMO), and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matching error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Since SEPE is difficult to reduce, more emphasis needs to be placed on reducing the overlay EPE in order to reduce the total EPE.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87179045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537487
Kihyun Choi, T. Jeong, Jinju Kim, S. Choo, Young-Hoon Kim, M. Yeo, Miji Lee, Jinseok Kim, Euncheol Lee
In this paper, we will report the reliability characterization of advanced FinFET technology which is developed by utilizing EUV. The intrinsic device reliability including HCI, BTI, and TDDB is comparable across FinFET technologies, and would not be degraded by scaling down. The use of EUV single patterning significantly improves reliability variation so that improved reliability lifetime compared to the use of ArF multi-patterning. Also, the fact that long-term reliability results support lifetime projection of TDDB follows power model, enables us to utilize more reliability margins in the scaled FinFET technologies.
{"title":"Reliability Characterization on Advanced FinFET Technology","authors":"Kihyun Choi, T. Jeong, Jinju Kim, S. Choo, Young-Hoon Kim, M. Yeo, Miji Lee, Jinseok Kim, Euncheol Lee","doi":"10.1109/IITC51362.2021.9537487","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537487","url":null,"abstract":"In this paper, we will report the reliability characterization of advanced FinFET technology which is developed by utilizing EUV. The intrinsic device reliability including HCI, BTI, and TDDB is comparable across FinFET technologies, and would not be degraded by scaling down. The use of EUV single patterning significantly improves reliability variation so that improved reliability lifetime compared to the use of ArF multi-patterning. Also, the fact that long-term reliability results support lifetime projection of TDDB follows power model, enables us to utilize more reliability margins in the scaled FinFET technologies.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"66 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90348116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537366
I. Ovchinnikov, D. Seregin, D. Abdullaev, K. Vorotilov, A. Rezvanov, V. Gvozdev, T. Blomberg, A. A. Veselov, M. Baklanov
Mechanical properties of low-k dielectrics deposited on a surface with patterned metal (Cu) lines are evaluated by using atomic force microscopy (AFM) in the PeakForce quantitative mapping (PFQNM) mode. It is shown that Young’s modulus (YM) of completely cured low-k films depends on the position in the structure. The Young’s modulus decreases with reduction of intermetal gap, and it is related to the reduced efficiency of curing. Significant reduction of YM is observed in the areas close to interface between the metal and low-k. The possible reason is bad adhesion between the low-k film and barrier layers and the reduction of effective network connectivity of silicon atoms.
{"title":"Mechanical Properties of Low-k Dielectric Deposited on Subtractively Patterned Cu Lines for Advanced Interconnects","authors":"I. Ovchinnikov, D. Seregin, D. Abdullaev, K. Vorotilov, A. Rezvanov, V. Gvozdev, T. Blomberg, A. A. Veselov, M. Baklanov","doi":"10.1109/IITC51362.2021.9537366","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537366","url":null,"abstract":"Mechanical properties of low-k dielectrics deposited on a surface with patterned metal (Cu) lines are evaluated by using atomic force microscopy (AFM) in the PeakForce quantitative mapping (PFQNM) mode. It is shown that Young’s modulus (YM) of completely cured low-k films depends on the position in the structure. The Young’s modulus decreases with reduction of intermetal gap, and it is related to the reduced efficiency of curing. Significant reduction of YM is observed in the areas close to interface between the metal and low-k. The possible reason is bad adhesion between the low-k film and barrier layers and the reduction of effective network connectivity of silicon atoms.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"48 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74663311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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