Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831877
Y. Umehara, Wen Jin
Unique nondestructive inline profile metrology of through-Silicon via (TSV) for 3D integrated circuits in production processes such as ultra-deep etching and Cu pillar forming process was introduced. We tried to measure the depth profile of TSVs from X-ray images with a tilted angle by applying model based library method. The fairly good repeatability in critical dimensions (CDs) and the depths (<;100nm, <;200nm respectively) and good correlation in CDs with results from SEM measurement were obtained, and good robustness under low SNR ~2 of the images was confirmed.
{"title":"Unique nondestructive inline metrology of TSVs by X-ray with model based library method","authors":"Y. Umehara, Wen Jin","doi":"10.1109/IITC.2014.6831877","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831877","url":null,"abstract":"Unique nondestructive inline profile metrology of through-Silicon via (TSV) for 3D integrated circuits in production processes such as ultra-deep etching and Cu pillar forming process was introduced. We tried to measure the depth profile of TSVs from X-ray images with a tilted angle by applying model based library method. The fairly good repeatability in critical dimensions (CDs) and the depths (<;100nm, <;200nm respectively) and good correlation in CDs with results from SEM measurement were obtained, and good robustness under low SNR ~2 of the images was confirmed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"57 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78091028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831896
H. Kawasaki, Kenji Matsumoto, H. Nagai, Yuuki Kikuchi, Peng Chang
We demonstrated atomic layer deposition (ALD) of manganese oxide (MnOx) for Cu capping layer. This process is expected to have not only EM (electro-migration) improvement but also admissibility of surface Cu oxidation. That will provide easy time and atmosphere management after chemical mechanical polishing (CMP). In this study, we confirmed Mn(Ox) coverage on Cu without degradation of leakage current and indication of EM improvement with simple EM test.
{"title":"Atomic layer deposition of MnOx for Cu capping layer in Cu/low-k interconnects","authors":"H. Kawasaki, Kenji Matsumoto, H. Nagai, Yuuki Kikuchi, Peng Chang","doi":"10.1109/IITC.2014.6831896","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831896","url":null,"abstract":"We demonstrated atomic layer deposition (ALD) of manganese oxide (MnOx) for Cu capping layer. This process is expected to have not only EM (electro-migration) improvement but also admissibility of surface Cu oxidation. That will provide easy time and atmosphere management after chemical mechanical polishing (CMP). In this study, we confirmed Mn(Ox) coverage on Cu without degradation of leakage current and indication of EM improvement with simple EM test.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78311995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831863
C. Adelmann, L. Wen, A. Peter, Y. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, S. Van Elshocht, J. Bommels, Z. Tokei
We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.
{"title":"Alternative metals for advanced interconnects","authors":"C. Adelmann, L. Wen, A. Peter, Y. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, S. Van Elshocht, J. Bommels, Z. Tokei","doi":"10.1109/IITC.2014.6831863","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831863","url":null,"abstract":"We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"31 1","pages":"173-176"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79256184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831871
F. Inoue, H. Philipsen, M. H. van der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka
High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.
{"title":"Electroless Cu seed on Ru and Co liners in high aspect ratio TSV","authors":"F. Inoue, H. Philipsen, M. H. van der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka","doi":"10.1109/IITC.2014.6831871","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831871","url":null,"abstract":"High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"8 1","pages":"207-210"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82198455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831839
Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan
3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.
{"title":"2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms","authors":"Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan","doi":"10.1109/IITC.2014.6831839","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831839","url":null,"abstract":"3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"2 1","pages":"381-384"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82522995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831897
M. Shulaker, G. Hills, Hai Wei, Hong-Yu Chen, N. Patil, H. Wong, S. Mitra
Carbon Nanotube FETs (CNFETs) are excellent candidates for the next generation of high-performance and energy-efficient electronics, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a computer implemented entirely using CNFETs. The CNT computer is capable of performing multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we emulate 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This is the most complex carbon-based electronic system yet demonstrated. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. In addition to performance and energy benefits, CNFETs also provide a unique opportunity to achieve monolithic three-dimensional (3D) integration through low-temperature CNFET processing. Monolithic 3D integration is an attractive technological option because it enables a very high density of Inter-Layer Vias compared to Through-Silicon Vias. A summary of monolithic 3D CNFET integrated circuit demonstrations will also be given.
{"title":"Advancements with carbon nanotube digital systems","authors":"M. Shulaker, G. Hills, Hai Wei, Hong-Yu Chen, N. Patil, H. Wong, S. Mitra","doi":"10.1109/IITC.2014.6831897","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831897","url":null,"abstract":"Carbon Nanotube FETs (CNFETs) are excellent candidates for the next generation of high-performance and energy-efficient electronics, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a computer implemented entirely using CNFETs. The CNT computer is capable of performing multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we emulate 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This is the most complex carbon-based electronic system yet demonstrated. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. In addition to performance and energy benefits, CNFETs also provide a unique opportunity to achieve monolithic three-dimensional (3D) integration through low-temperature CNFET processing. Monolithic 3D integration is an attractive technological option because it enables a very high density of Inter-Layer Vias compared to Through-Silicon Vias. A summary of monolithic 3D CNFET integrated circuit demonstrations will also be given.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"5 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78844791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831833
R. M. Iraei, P. Bonhomme, N. Kani, S. Manipatruni, D. Nikonov, I. Young, A. Naeemi
The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.
{"title":"Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects","authors":"R. M. Iraei, P. Bonhomme, N. Kani, S. Manipatruni, D. Nikonov, I. Young, A. Naeemi","doi":"10.1109/IITC.2014.6831833","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831833","url":null,"abstract":"The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 1","pages":"353-356"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79914789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831834
Marta Giachino, F. Paredes, N. Ananthakrishnan, S. Liff, R. Dauskardt
Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We demonstrate a way to quantitatively measure the mechanical and kinetic behavior of an underfill epoxy resin containing a broad range of filler particles. With the introduction of fillers into the bisphenol-F-based resin, the fracture energy at the epoxy/Si interface is largely increased compared to the unfilled epoxy/Si interface. We characterize the cohesive and adhesive properties of each filled epoxy to the adjacent passivated silicon substrate and report on the moisture-assisted debonding kinetics in varying humidity and temperature environments, including accelerated testing conditions.
{"title":"Moisture-assisted failure mechanisms in underfill epoxy/silicon systems for microelectronic packaging","authors":"Marta Giachino, F. Paredes, N. Ananthakrishnan, S. Liff, R. Dauskardt","doi":"10.1109/IITC.2014.6831834","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831834","url":null,"abstract":"Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We demonstrate a way to quantitatively measure the mechanical and kinetic behavior of an underfill epoxy resin containing a broad range of filler particles. With the introduction of fillers into the bisphenol-F-based resin, the fracture energy at the epoxy/Si interface is largely increased compared to the unfilled epoxy/Si interface. We characterize the cohesive and adhesive properties of each filled epoxy to the adjacent passivated silicon substrate and report on the moisture-assisted debonding kinetics in varying humidity and temperature environments, including accelerated testing conditions.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"38 1","pages":"359-362"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86987724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831873
J. Plawsky, J. Borja, T. Lu, H. Bakhru, R. Rosenberg, W. Gill, T. Shaw, R. Laibowitz, E. Liniger, S. Cohen, G. Bonilla
Summary form only given. The reliability of new ultra-porous low-k materials is often a fascinating and complex tale involving multiple concepts from material science, electrical and chemical engineering. Pursuing an understanding of reliability for novel low-k materials requires the dissection of fundamental mechanisms and phenomena altering the electrical and physical properties of the dielectric matrix. Failure mechanisms can be categorized into two main groups. Intrinsic failure arises from damage to the dielectric matrix due to the transport of charge carriers. Ion catalyzed failure results from the drift of ionic species originating from the metal/dielectric interface. Integration of sub-20nm process technology nodes can be radically advanced by resolving how major failure mechanisms coexist and collaborate to generate dielectric failures. Here, we present a set of dynamic applied field experiments designed to identify changes in the conduction and reliability of dielectric films as result of bias and temperature stress (BTS). It is shown that ionic species originating from the metal/dielectric interface can behave as trapping centers for charge carriers under BTS. Trapping of electrons into ionic centers could increase the scattering of charge carriers which leads to the additional formation of intrinsic defects across the dielectric matrix, thus accelerating intrinsic failure. A mechanism is proposed to describe how leakage current decay at the onset of BTS is related to charge carrier confinement into intrinsic and ionic defects. The kinetics of charge trapping events were found to be consistent with a time-dependent reaction rate constant, k = k0 · (t + 1)β-1 where 0<;β<;1. This formulation leads to a classic, stretched exponential decay rate that we are looking to use to help predict dielectric reliability.
{"title":"Reliability of ultra-porous low-k materials for advanced interconnects","authors":"J. Plawsky, J. Borja, T. Lu, H. Bakhru, R. Rosenberg, W. Gill, T. Shaw, R. Laibowitz, E. Liniger, S. Cohen, G. Bonilla","doi":"10.1109/IITC.2014.6831873","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831873","url":null,"abstract":"Summary form only given. The reliability of new ultra-porous low-k materials is often a fascinating and complex tale involving multiple concepts from material science, electrical and chemical engineering. Pursuing an understanding of reliability for novel low-k materials requires the dissection of fundamental mechanisms and phenomena altering the electrical and physical properties of the dielectric matrix. Failure mechanisms can be categorized into two main groups. Intrinsic failure arises from damage to the dielectric matrix due to the transport of charge carriers. Ion catalyzed failure results from the drift of ionic species originating from the metal/dielectric interface. Integration of sub-20nm process technology nodes can be radically advanced by resolving how major failure mechanisms coexist and collaborate to generate dielectric failures. Here, we present a set of dynamic applied field experiments designed to identify changes in the conduction and reliability of dielectric films as result of bias and temperature stress (BTS). It is shown that ionic species originating from the metal/dielectric interface can behave as trapping centers for charge carriers under BTS. Trapping of electrons into ionic centers could increase the scattering of charge carriers which leads to the additional formation of intrinsic defects across the dielectric matrix, thus accelerating intrinsic failure. A mechanism is proposed to describe how leakage current decay at the onset of BTS is related to charge carrier confinement into intrinsic and ionic defects. The kinetics of charge trapping events were found to be consistent with a time-dependent reaction rate constant, k = k0 · (t + 1)β-1 where 0<;β<;1. This formulation leads to a classic, stretched exponential decay rate that we are looking to use to help predict dielectric reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 1","pages":"217-218"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89384885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831830
T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens
The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.
{"title":"Interconnects scaling challenge for sub-20nm spin torque transfer magnetic random access memory technology","authors":"T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens","doi":"10.1109/IITC.2014.6831830","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831830","url":null,"abstract":"The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"209 1","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88496520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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