Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831877
Y. Umehara, Wen Jin
Unique nondestructive inline profile metrology of through-Silicon via (TSV) for 3D integrated circuits in production processes such as ultra-deep etching and Cu pillar forming process was introduced. We tried to measure the depth profile of TSVs from X-ray images with a tilted angle by applying model based library method. The fairly good repeatability in critical dimensions (CDs) and the depths (<;100nm, <;200nm respectively) and good correlation in CDs with results from SEM measurement were obtained, and good robustness under low SNR ~2 of the images was confirmed.
{"title":"Unique nondestructive inline metrology of TSVs by X-ray with model based library method","authors":"Y. Umehara, Wen Jin","doi":"10.1109/IITC.2014.6831877","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831877","url":null,"abstract":"Unique nondestructive inline profile metrology of through-Silicon via (TSV) for 3D integrated circuits in production processes such as ultra-deep etching and Cu pillar forming process was introduced. We tried to measure the depth profile of TSVs from X-ray images with a tilted angle by applying model based library method. The fairly good repeatability in critical dimensions (CDs) and the depths (<;100nm, <;200nm respectively) and good correlation in CDs with results from SEM measurement were obtained, and good robustness under low SNR ~2 of the images was confirmed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"57 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78091028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831896
H. Kawasaki, Kenji Matsumoto, H. Nagai, Yuuki Kikuchi, Peng Chang
We demonstrated atomic layer deposition (ALD) of manganese oxide (MnOx) for Cu capping layer. This process is expected to have not only EM (electro-migration) improvement but also admissibility of surface Cu oxidation. That will provide easy time and atmosphere management after chemical mechanical polishing (CMP). In this study, we confirmed Mn(Ox) coverage on Cu without degradation of leakage current and indication of EM improvement with simple EM test.
{"title":"Atomic layer deposition of MnOx for Cu capping layer in Cu/low-k interconnects","authors":"H. Kawasaki, Kenji Matsumoto, H. Nagai, Yuuki Kikuchi, Peng Chang","doi":"10.1109/IITC.2014.6831896","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831896","url":null,"abstract":"We demonstrated atomic layer deposition (ALD) of manganese oxide (MnOx) for Cu capping layer. This process is expected to have not only EM (electro-migration) improvement but also admissibility of surface Cu oxidation. That will provide easy time and atmosphere management after chemical mechanical polishing (CMP). In this study, we confirmed Mn(Ox) coverage on Cu without degradation of leakage current and indication of EM improvement with simple EM test.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78311995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831863
C. Adelmann, L. Wen, A. Peter, Y. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, S. Van Elshocht, J. Bommels, Z. Tokei
We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.
{"title":"Alternative metals for advanced interconnects","authors":"C. Adelmann, L. Wen, A. Peter, Y. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, S. Van Elshocht, J. Bommels, Z. Tokei","doi":"10.1109/IITC.2014.6831863","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831863","url":null,"abstract":"We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"31 1","pages":"173-176"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79256184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831871
F. Inoue, H. Philipsen, M. H. van der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka
High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.
{"title":"Electroless Cu seed on Ru and Co liners in high aspect ratio TSV","authors":"F. Inoue, H. Philipsen, M. H. van der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka","doi":"10.1109/IITC.2014.6831871","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831871","url":null,"abstract":"High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"8 1","pages":"207-210"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82198455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831839
Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan
3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.
{"title":"2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms","authors":"Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan","doi":"10.1109/IITC.2014.6831839","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831839","url":null,"abstract":"3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"2 1","pages":"381-384"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82522995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831897
M. Shulaker, G. Hills, Hai Wei, Hong-Yu Chen, N. Patil, H. Wong, S. Mitra
Carbon Nanotube FETs (CNFETs) are excellent candidates for the next generation of high-performance and energy-efficient electronics, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a computer implemented entirely using CNFETs. The CNT computer is capable of performing multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we emulate 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This is the most complex carbon-based electronic system yet demonstrated. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. In addition to performance and energy benefits, CNFETs also provide a unique opportunity to achieve monolithic three-dimensional (3D) integration through low-temperature CNFET processing. Monolithic 3D integration is an attractive technological option because it enables a very high density of Inter-Layer Vias compared to Through-Silicon Vias. A summary of monolithic 3D CNFET integrated circuit demonstrations will also be given.
{"title":"Advancements with carbon nanotube digital systems","authors":"M. Shulaker, G. Hills, Hai Wei, Hong-Yu Chen, N. Patil, H. Wong, S. Mitra","doi":"10.1109/IITC.2014.6831897","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831897","url":null,"abstract":"Carbon Nanotube FETs (CNFETs) are excellent candidates for the next generation of high-performance and energy-efficient electronics, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a computer implemented entirely using CNFETs. The CNT computer is capable of performing multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we emulate 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This is the most complex carbon-based electronic system yet demonstrated. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. In addition to performance and energy benefits, CNFETs also provide a unique opportunity to achieve monolithic three-dimensional (3D) integration through low-temperature CNFET processing. Monolithic 3D integration is an attractive technological option because it enables a very high density of Inter-Layer Vias compared to Through-Silicon Vias. A summary of monolithic 3D CNFET integrated circuit demonstrations will also be given.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"5 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78844791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831833
R. M. Iraei, P. Bonhomme, N. Kani, S. Manipatruni, D. Nikonov, I. Young, A. Naeemi
The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.
{"title":"Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects","authors":"R. M. Iraei, P. Bonhomme, N. Kani, S. Manipatruni, D. Nikonov, I. Young, A. Naeemi","doi":"10.1109/IITC.2014.6831833","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831833","url":null,"abstract":"The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 1","pages":"353-356"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79914789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831834
Marta Giachino, F. Paredes, N. Ananthakrishnan, S. Liff, R. Dauskardt
Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We demonstrate a way to quantitatively measure the mechanical and kinetic behavior of an underfill epoxy resin containing a broad range of filler particles. With the introduction of fillers into the bisphenol-F-based resin, the fracture energy at the epoxy/Si interface is largely increased compared to the unfilled epoxy/Si interface. We characterize the cohesive and adhesive properties of each filled epoxy to the adjacent passivated silicon substrate and report on the moisture-assisted debonding kinetics in varying humidity and temperature environments, including accelerated testing conditions.
{"title":"Moisture-assisted failure mechanisms in underfill epoxy/silicon systems for microelectronic packaging","authors":"Marta Giachino, F. Paredes, N. Ananthakrishnan, S. Liff, R. Dauskardt","doi":"10.1109/IITC.2014.6831834","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831834","url":null,"abstract":"Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We demonstrate a way to quantitatively measure the mechanical and kinetic behavior of an underfill epoxy resin containing a broad range of filler particles. With the introduction of fillers into the bisphenol-F-based resin, the fracture energy at the epoxy/Si interface is largely increased compared to the unfilled epoxy/Si interface. We characterize the cohesive and adhesive properties of each filled epoxy to the adjacent passivated silicon substrate and report on the moisture-assisted debonding kinetics in varying humidity and temperature environments, including accelerated testing conditions.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"38 1","pages":"359-362"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86987724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831840
S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah
Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.
{"title":"Foundry TSV integration and manufacturing challenges","authors":"S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah","doi":"10.1109/IITC.2014.6831840","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831840","url":null,"abstract":"Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"385-388"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74594723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-20DOI: 10.1109/IITC.2014.6831888
C. Yang, B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, D. Edelstein
Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.
{"title":"Thermal stress control in Cu interconnects","authors":"C. Yang, B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, D. Edelstein","doi":"10.1109/IITC.2014.6831888","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831888","url":null,"abstract":"Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"148 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74264340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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