Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537315
Son Van Nguyen, H. Shobha, C. Peethala, T. Haigh, H. Huang, J. Li, J. Demarest, B. Haran, D. Hausmann, P. Lemaire, K. Sharma, P. Ramani, A. Mahorowala
AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selective AlOx deposition involves multistep process including surface treatment, selective Self-Aligned Molecules (SAM) bonding to inhibit Cu metal surface, and the selective growth of AlOx on top of SiCOH dielectric using Chemical vapor deposition process with various precursors and process conditions below 300°C. Thin selective AlOx of 4–6 nm thickness show excellent selectivity on SiCOH over Co capped Cu-SiCOH patterned structures with various spacing. The Via Chain electrical yields were measured on 32 nm pitch structures by AlOx selective deposition and are comparable to the established FAV process by Cu wet recess. This indicates that the Selective AlOx deposition process is highly selective on SiCOH dielectric surface without defect formation in the Co Capped Cu surfaces.
{"title":"Selective deposition of AlOx for Fully Aligned Via in nano Cu interconnects","authors":"Son Van Nguyen, H. Shobha, C. Peethala, T. Haigh, H. Huang, J. Li, J. Demarest, B. Haran, D. Hausmann, P. Lemaire, K. Sharma, P. Ramani, A. Mahorowala","doi":"10.1109/IITC51362.2021.9537315","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537315","url":null,"abstract":"AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selective AlOx deposition involves multistep process including surface treatment, selective Self-Aligned Molecules (SAM) bonding to inhibit Cu metal surface, and the selective growth of AlOx on top of SiCOH dielectric using Chemical vapor deposition process with various precursors and process conditions below 300°C. Thin selective AlOx of 4–6 nm thickness show excellent selectivity on SiCOH over Co capped Cu-SiCOH patterned structures with various spacing. The Via Chain electrical yields were measured on 32 nm pitch structures by AlOx selective deposition and are comparable to the established FAV process by Cu wet recess. This indicates that the Selective AlOx deposition process is highly selective on SiCOH dielectric surface without defect formation in the Co Capped Cu surfaces.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82288725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537529
Lingyen Yeh, Shun Chun Huang
Virtual metrology equipped with a variability analyzer is reported. Twenty-six process variables are modeled to predict run-to-run material removal rates in chemical mechanical polishing. The mean absolute percentage error of about 0.5 % is accomplished in prediction. Factors leading to the run-to-run variations are analyzed using exploratory factor analysis. Three major factors are found and analyzed using two different approaches. The relevant process features corresponding to the factors are extracted and possible physical explanations provided. The results suggest the proposed virtual metrology is potential to analyze variability in chemical mechanical polishing and extendable to the other processes.
{"title":"Virtual Metrology Equipped with a Variability Analyzer in Chemical Mechanical Polishing","authors":"Lingyen Yeh, Shun Chun Huang","doi":"10.1109/IITC51362.2021.9537529","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537529","url":null,"abstract":"Virtual metrology equipped with a variability analyzer is reported. Twenty-six process variables are modeled to predict run-to-run material removal rates in chemical mechanical polishing. The mean absolute percentage error of about 0.5 % is accomplished in prediction. Factors leading to the run-to-run variations are analyzed using exploratory factor analysis. Three major factors are found and analyzed using two different approaches. The relevant process features corresponding to the factors are extracted and possible physical explanations provided. The results suggest the proposed virtual metrology is potential to analyze variability in chemical mechanical polishing and extendable to the other processes.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"3 6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86562510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537435
O. O. Okudur, Mario Gonzalez, G. Van den bosch, M. Rosmeulen
Mechanical stresses introduced at various processing steps, combined with large stack thicknesses result in high wafer warpage during 3-D NAND fabrication. We demonstrate a local (device-level) to global (wafer-level) scale finite-element modeling approach that can be used to evaluate wafer warpage with scaling trends and offer potential mitigation strategies. It is shown that the anisotropy in local stresses and asymmetry in warpage are initiated after etching the slits and amplified by wordline metal deposition. Increasing number of layers is shown to significantly increase the magnitude and asymmetry of the warpage. Decreasing layer thicknesses and use of low-stress wordline metal such as Ruthenium and adjusting filler stresses can help reducing wafer-warpage related problems.
{"title":"Multi-scale Modeling Approach to Assess and Mitigate Wafer Warpage in 3-D NAND Fabrication","authors":"O. O. Okudur, Mario Gonzalez, G. Van den bosch, M. Rosmeulen","doi":"10.1109/IITC51362.2021.9537435","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537435","url":null,"abstract":"Mechanical stresses introduced at various processing steps, combined with large stack thicknesses result in high wafer warpage during 3-D NAND fabrication. We demonstrate a local (device-level) to global (wafer-level) scale finite-element modeling approach that can be used to evaluate wafer warpage with scaling trends and offer potential mitigation strategies. It is shown that the anisotropy in local stresses and asymmetry in warpage are initiated after etching the slits and amplified by wordline metal deposition. Increasing number of layers is shown to significantly increase the magnitude and asymmetry of the warpage. Decreasing layer thicknesses and use of low-stress wordline metal such as Ruthenium and adjusting filler stresses can help reducing wafer-warpage related problems.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"33 4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83856687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537481
S. Aboud, T. Gunst, J. Cobb, Joanne Huang, P. Asenov, V. Arcisauskaite
In this work, we demonstrate our first-principles based methodology to include atomistic level simulations to evaluate the promise of different metals on the performance of MOL/BEOL interconnects. The specific metals that we focus on include Cu, Ru (both fcc and hcp), Co, Mo, and W where the conductivity of these metals, including the degradation from grain boundaries is extracted from ab initio simulations, is included in a parasitic field solver and subsequently used to extract the interconnect parasitics of standard cells. PPA is evaluated through simulations of an 128x128 SRAM memory array where we find significant improvement in the read and write delay of 20% and 40%, respectively when we replace M1 with Ru(fcc).
{"title":"Materials Impact on SRAM Timing: An Ab Initio Study of Interconnects","authors":"S. Aboud, T. Gunst, J. Cobb, Joanne Huang, P. Asenov, V. Arcisauskaite","doi":"10.1109/IITC51362.2021.9537481","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537481","url":null,"abstract":"In this work, we demonstrate our first-principles based methodology to include atomistic level simulations to evaluate the promise of different metals on the performance of MOL/BEOL interconnects. The specific metals that we focus on include Cu, Ru (both fcc and hcp), Co, Mo, and W where the conductivity of these metals, including the degradation from grain boundaries is extracted from ab initio simulations, is included in a parasitic field solver and subsequently used to extract the interconnect parasitics of standard cells. PPA is evaluated through simulations of an 128x128 SRAM memory array where we find significant improvement in the read and write delay of 20% and 40%, respectively when we replace M1 with Ru(fcc).","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86144671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537344
H. Park, Seungmin Park, Yoonho Kim, S. Kim
3D packaging is able to keep the scaling in semiconductor market. Increased and shorter interconnects achieved by vertical stacking have benefits such as improved performance, reduced signal delay, and small form factor. In order to obtain high-quality 3D packaging applications, the integration of heterogeneous devices through bonding technologies is very important. Low temperature and pressure are essential during the bonding process because most of logic/memory devices has many metal and low-k dielectric layers, which are vulnerable to thermal budget and mechanical stress. Therefore, a small amount of solder with a low melting point is presently used on the top of the copper pillar for mass production. But, solder creates an intermetallic compound with copper at the bonding interface and cannot be applied to fine pitch patterns due to their reflow characteristics. Thus, Cu is emerged as a promising interconnect, but Cu-Cu bonding has few challenges because copper is easily oxidized and has a high melting point. In this paper, copper nitride, which prevents oxidation of the copper surface and promotes low temperature bonding, was studied by two step Ar/N2 plasma treatment. The optimum thickness of copper nitride passivation was derived using the design of experiment. It was also found that the copper nitride layer was almost decomposed at a temperature of 200°C.
{"title":"Cu-Cu Bonding using Optimized Copper Nitride Passivation for 3D Packaging Applications","authors":"H. Park, Seungmin Park, Yoonho Kim, S. Kim","doi":"10.1109/IITC51362.2021.9537344","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537344","url":null,"abstract":"3D packaging is able to keep the scaling in semiconductor market. Increased and shorter interconnects achieved by vertical stacking have benefits such as improved performance, reduced signal delay, and small form factor. In order to obtain high-quality 3D packaging applications, the integration of heterogeneous devices through bonding technologies is very important. Low temperature and pressure are essential during the bonding process because most of logic/memory devices has many metal and low-k dielectric layers, which are vulnerable to thermal budget and mechanical stress. Therefore, a small amount of solder with a low melting point is presently used on the top of the copper pillar for mass production. But, solder creates an intermetallic compound with copper at the bonding interface and cannot be applied to fine pitch patterns due to their reflow characteristics. Thus, Cu is emerged as a promising interconnect, but Cu-Cu bonding has few challenges because copper is easily oxidized and has a high melting point. In this paper, copper nitride, which prevents oxidation of the copper surface and promotes low temperature bonding, was studied by two step Ar/N2 plasma treatment. The optimum thickness of copper nitride passivation was derived using the design of experiment. It was also found that the copper nitride layer was almost decomposed at a temperature of 200°C.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91398861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537458
Amine Lakhdari, M. Frégnaux, L. Caillard, A. Gonçalves, M. Thiam, F. Raynal, A. Etcheberry
The constant shrinking of critical dimensions in logic manufacturing is driving a change in integration of interconnects. While copper has been the material of choice for the past few decades, it is currently facing a serious challenge from other materials like cobalt. The focus of this paper is three-fold. First, we compare the reactivity of both materials in different media. Next, we confirm that kinetics of native oxide formation when exposed to atmosphere is an order of magnitude slower for copper than for cobalt and that, in the case of cobalt, the presence of an oxide is not avoidable in the industry conditions. And finally, we investigated the compatibility of plating solutions manufactured by aveni for cobalt and copper deposition. Both solutions reveal that, not only do they etch the native oxide of a cobalt seed, but they also preserve the integrity of the underlying metallic cobalt layer. This is highlighted by the fact that no oxide is detected at the interface between the deposited metal and the seed after deposition. We therefore provide evidence of the compatibility of aveni plating solution with a wide array of integrations for next generation interconnects such as copper extension with direct-on-cobalt integration or full cobalt integration.
{"title":"Comparison of Copper and Cobalt Surface Reactivity for Advanced Interconnects","authors":"Amine Lakhdari, M. Frégnaux, L. Caillard, A. Gonçalves, M. Thiam, F. Raynal, A. Etcheberry","doi":"10.1109/IITC51362.2021.9537458","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537458","url":null,"abstract":"The constant shrinking of critical dimensions in logic manufacturing is driving a change in integration of interconnects. While copper has been the material of choice for the past few decades, it is currently facing a serious challenge from other materials like cobalt. The focus of this paper is three-fold. First, we compare the reactivity of both materials in different media. Next, we confirm that kinetics of native oxide formation when exposed to atmosphere is an order of magnitude slower for copper than for cobalt and that, in the case of cobalt, the presence of an oxide is not avoidable in the industry conditions. And finally, we investigated the compatibility of plating solutions manufactured by aveni for cobalt and copper deposition. Both solutions reveal that, not only do they etch the native oxide of a cobalt seed, but they also preserve the integrity of the underlying metallic cobalt layer. This is highlighted by the fact that no oxide is detected at the interface between the deposited metal and the seed after deposition. We therefore provide evidence of the compatibility of aveni plating solution with a wide array of integrations for next generation interconnects such as copper extension with direct-on-cobalt integration or full cobalt integration.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"2014 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73625991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537451
K. Motoyama
It has been observed that void-free Cu fill, interface control for both Cu/liner (trench sidewall and bottom) and Cu/cap (trench top), and grain size engineering are critical to improve Electromigration (EM) performance for Cu interconnects in the case of using Ru liner and Co cap. Especially, Co diffusion from the cap into a Ru liner (resulting in Co depletion at the top of Cu lines) is one of the root causes of EM degradation. A novel Co-doped Ru liner has been developed, which demonstrates a significant EM performance boost by addressing the Co diffusion issue. This Co-doped Ru liner is shown to be a promising liner of choice for Cu interconnects in advanced nodes.
{"title":"EM performance improvements for Cu interconnects with Ru-based liner and Co cap in advanced nodes : (Invited)","authors":"K. Motoyama","doi":"10.1109/IITC51362.2021.9537451","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537451","url":null,"abstract":"It has been observed that void-free Cu fill, interface control for both Cu/liner (trench sidewall and bottom) and Cu/cap (trench top), and grain size engineering are critical to improve Electromigration (EM) performance for Cu interconnects in the case of using Ru liner and Co cap. Especially, Co diffusion from the cap into a Ru liner (resulting in Co depletion at the top of Cu lines) is one of the root causes of EM degradation. A novel Co-doped Ru liner has been developed, which demonstrates a significant EM performance boost by addressing the Co diffusion issue. This Co-doped Ru liner is shown to be a promising liner of choice for Cu interconnects in advanced nodes.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"72 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75840086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537482
Keshia Mekemeza Ona, B. Charbonnier, K. Hassan
We present the simulation of an individual spiking laser to be used as a photonic neuron for a spiking neural network scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser’s heterostructure. Its full integration into a complete silicon photonics platform makes it ideal for large scale photonic SNN circuits.
我们提出了一个单独的脉冲激光作为光子神经元，用于脉冲神经网络的放大模拟。神经元是一种通过修饰CEA Leti III-V对硅集成连续波激光器异质结构而优化为脉冲工作的半导体激光器。它完全集成到一个完整的硅光子学平台，使其成为大规模光子SNN电路的理想选择。
{"title":"Design of an Integrated III–V on silicon semiconductor laser for spiking neural networks","authors":"Keshia Mekemeza Ona, B. Charbonnier, K. Hassan","doi":"10.1109/IITC51362.2021.9537482","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537482","url":null,"abstract":"We present the simulation of an individual spiking laser to be used as a photonic neuron for a spiking neural network scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser’s heterostructure. Its full integration into a complete silicon photonics platform makes it ideal for large scale photonic SNN circuits.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"12 11 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76566611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537434
S. Ikegawa, F. Mancoff, S. Aggarwal
From data centers to IoT edge devices, data processing demands and evolution in computing drive the growing need for magnetoresistive random access memory (MRAM) because of its non-volatility, high speed, robust endurance, and system power savings capability. Based on a review of past successful commercialization of MRAM, this paper provides a future perspective of MRAM products. To expand the MRAM market competing with existing memories, three directions are discussed: (1) faster access time, (2) longer endurance cycles, and (3) lower bit cost.
{"title":"Commercialization of MRAM – Historical and Future Perspective","authors":"S. Ikegawa, F. Mancoff, S. Aggarwal","doi":"10.1109/IITC51362.2021.9537434","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537434","url":null,"abstract":"From data centers to IoT edge devices, data processing demands and evolution in computing drive the growing need for magnetoresistive random access memory (MRAM) because of its non-volatility, high speed, robust endurance, and system power savings capability. Based on a review of past successful commercialization of MRAM, this paper provides a future perspective of MRAM products. To expand the MRAM market competing with existing memories, three directions are discussed: (1) faster access time, (2) longer endurance cycles, and (3) lower bit cost.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74923182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537410
M. H. van der Veen, O. Pedreira, N. Heylen, N. Jourdan, S. Lariviere, S. Park, H. Struyf, Z. Tokei, W. Lei, S. Pethe, S. Hwang, F. Chen, Z. Wu, J. Machillot, A. Cockburn, A. Jansen
In this exploratory study, selective tungsten (W) deposition is used before the copper (Cu) metallization steps with the aim to solely fill the via with W. The W deposition is tested on the bottom metal cobalt (Co) or ruthenium (Ru) and shows an excellent selectivity towards the dielectric SiO2 and dense low-k material 3.0. The via resistance shows up to a 40% reduction for the W-Cu hybrid system compared to a Cu dual damascene (DD) filled via. The material compatibility is tested in a thermal storage study and shows no performance degradation of the bottom barrierless W vias. This feasibility study using a middle of line (MOL) metal shows that a W-Cu hybrid system can be an option for further extension of Cu interconnects while suppressing the via resistance.
{"title":"Exploring W-Cu hybrid dual damascene metallization for future nodes","authors":"M. H. van der Veen, O. Pedreira, N. Heylen, N. Jourdan, S. Lariviere, S. Park, H. Struyf, Z. Tokei, W. Lei, S. Pethe, S. Hwang, F. Chen, Z. Wu, J. Machillot, A. Cockburn, A. Jansen","doi":"10.1109/IITC51362.2021.9537410","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537410","url":null,"abstract":"In this exploratory study, selective tungsten (W) deposition is used before the copper (Cu) metallization steps with the aim to solely fill the via with W. The W deposition is tested on the bottom metal cobalt (Co) or ruthenium (Ru) and shows an excellent selectivity towards the dielectric SiO2 and dense low-k material 3.0. The via resistance shows up to a 40% reduction for the W-Cu hybrid system compared to a Cu dual damascene (DD) filled via. The material compatibility is tested in a thermal storage study and shows no performance degradation of the bottom barrierless W vias. This feasibility study using a middle of line (MOL) metal shows that a W-Cu hybrid system can be an option for further extension of Cu interconnects while suppressing the via resistance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84470129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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