Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537557
B. Chehab, O. Zografos, E. Litta, Z. Ahmed, P. Schuddinck, D. Jang, G. Hellings, A. Spessot, P. Weckx, J. Ryckaert
Due to the slowdown in gate pitch scaling linked to fundamental physical limitations, standard cell (SDC) height reduction becomes a key to achieve the scaling targets. In this work, a two-level (2L) middle of line (MOL) scheme based on a forksheet (FSH) device architecture and Vertical-Horizontal-Vertical (VHV) routing style is proposed to achieve 4-Track (4T) SDC template. The proposed architecture achieves 21% higher Power-Performance-Area (PPA) compared to the traditional 5T-HVH FSH architecture with limited additional process complexity and Cost (C).
{"title":"Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node","authors":"B. Chehab, O. Zografos, E. Litta, Z. Ahmed, P. Schuddinck, D. Jang, G. Hellings, A. Spessot, P. Weckx, J. Ryckaert","doi":"10.1109/IITC51362.2021.9537557","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537557","url":null,"abstract":"Due to the slowdown in gate pitch scaling linked to fundamental physical limitations, standard cell (SDC) height reduction becomes a key to achieve the scaling targets. In this work, a two-level (2L) middle of line (MOL) scheme based on a forksheet (FSH) device architecture and Vertical-Horizontal-Vertical (VHV) routing style is proposed to achieve 4-Track (4T) SDC template. The proposed architecture achieves 21% higher Power-Performance-Area (PPA) compared to the traditional 5T-HVH FSH architecture with limited additional process complexity and Cost (C).","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84439269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537390
Y. Kayaba, Yuzo Nakamura, T. Kozeki, J. Kamada, K. Kohmura
The bonding property of a thin adhesive for the high density 3D/2.5D Si chip integration with the Cu-Cu bonding at the low temperature range (150–400 °C) was investigated. The cured thin adhesive is bondable to SiO2 after baking at 150 °C with the high surface energy (6.4 J/m2). By using this adhesive Si chip can be integrated in 3D/2.5D with no thermal sliding and no adhesive protrusion from the chip corner. The reliability test results are also investigated.
{"title":"A Thin Adhesive for 3D/2.5D Si Chip Stacking at Low Temperature","authors":"Y. Kayaba, Yuzo Nakamura, T. Kozeki, J. Kamada, K. Kohmura","doi":"10.1109/IITC51362.2021.9537390","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537390","url":null,"abstract":"The bonding property of a thin adhesive for the high density 3D/2.5D Si chip integration with the Cu-Cu bonding at the low temperature range (150–400 °C) was investigated. The cured thin adhesive is bondable to SiO2 after baking at 150 °C with the high surface energy (6.4 J/m2). By using this adhesive Si chip can be integrated in 3D/2.5D with no thermal sliding and no adhesive protrusion from the chip corner. The reliability test results are also investigated.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83668742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537362
Jingrui Chai, Xiping Jiang, Xudong Gao, Bing Yu, Xiaofeng Zhou, Pengcheng Yin, Song Wang, J. Tan, Zhengwen Wang, Mei Li, Gang Dong, Qiwei Ren
Wafer-to-wafer hybrid bonding technology is used to realize a DRAM array wafer and a logic wafer face-to-face connected with the advantages of a high density integration for high bandwidth and energy efficiency. With the proposed stacked embedded DRAM (SEDRAM), the electromagnetic crosstalk and the electrothermal performance of hybrid bonding via (HBV) are studied using the proposed Meshless radial point interpolation method (M-RPIM) to reduce the electromagnetic crosstalk and the thermal crosstalk of the array. A parallelogram layout which arranges the signal HBVs and the ground HBVs in parallelogram shows the crosstalk noise and the maximum temperature is reduced by 10% and 11% respectively. In addition, an advanced honeycomb arrangement with dummy HBVs array and the interleaving stacking TSV-HBV structure are also proposed to further improve the performance of the SEDRAM.
{"title":"An Investigation for Electromagnetic and Electrothermal coupling Characteristics of Hybrid Bond in Stacked Embedded DRAM with MRPIM","authors":"Jingrui Chai, Xiping Jiang, Xudong Gao, Bing Yu, Xiaofeng Zhou, Pengcheng Yin, Song Wang, J. Tan, Zhengwen Wang, Mei Li, Gang Dong, Qiwei Ren","doi":"10.1109/IITC51362.2021.9537362","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537362","url":null,"abstract":"Wafer-to-wafer hybrid bonding technology is used to realize a DRAM array wafer and a logic wafer face-to-face connected with the advantages of a high density integration for high bandwidth and energy efficiency. With the proposed stacked embedded DRAM (SEDRAM), the electromagnetic crosstalk and the electrothermal performance of hybrid bonding via (HBV) are studied using the proposed Meshless radial point interpolation method (M-RPIM) to reduce the electromagnetic crosstalk and the thermal crosstalk of the array. A parallelogram layout which arranges the signal HBVs and the ground HBVs in parallelogram shows the crosstalk noise and the maximum temperature is reduced by 10% and 11% respectively. In addition, an advanced honeycomb arrangement with dummy HBVs array and the interleaving stacking TSV-HBV structure are also proposed to further improve the performance of the SEDRAM.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"352 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76586698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537441
J. Soulie, Z. Tokei, J. Swerts, C. Adelmann
AlNi, Al3Sc, AlCu, and Al2Cu thin films have been investigated as potential alternatives for Cu in interconnect metallization schemes. Stoichiometric NiAl thin films of 56 nm thickness show a resistivity of 13.9 μΩ cm after post-deposition annealing at 600°C. Different capping layers were tested to overcome the formation of an oxide top layer. Al3Sc presents a resistivity of 12.5 μΩ cm after post-deposition annealing at 500°C (for 24 nm thick films). AlCu and Al2Cu outperform Ru films at 20 nm thickness and above (9.5 μΩ cm for 28 nm films). Challenges and integration feasibility are discussed.
{"title":"Aluminide intermetallics for advanced interconnect metallization: thin film studies","authors":"J. Soulie, Z. Tokei, J. Swerts, C. Adelmann","doi":"10.1109/IITC51362.2021.9537441","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537441","url":null,"abstract":"AlNi, Al3Sc, AlCu, and Al2Cu thin films have been investigated as potential alternatives for Cu in interconnect metallization schemes. Stoichiometric NiAl thin films of 56 nm thickness show a resistivity of 13.9 μΩ cm after post-deposition annealing at 600°C. Different capping layers were tested to overcome the formation of an oxide top layer. Al3Sc presents a resistivity of 12.5 μΩ cm after post-deposition annealing at 500°C (for 24 nm thick films). AlCu and Al2Cu outperform Ru films at 20 nm thickness and above (9.5 μΩ cm for 28 nm films). Challenges and integration feasibility are discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78051950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537407
A. Pacco, Teppei Nakano, A. Iwasaki, Shota Iwahata, E. Sanchez
Molybdenum (Mo) is a promising metal for applications requiring low resistivity interconnects or contact lines in small dimensions. Etching of polycrystalline metals like Mo with conventional etching methods can be challenging because of the increased surface roughness and non-uniform recess. In this paper we describe a novel sequential etching method comprising two steps. The first step is an oxidation step in ozone (O3) at elevated temperatures in the range of 180°C–290°C resulting in a smooth metal/oxide interface. The second step is a selective oxide dissolution. The benefits of this cyclic, ALE-type recess over continuous wet-etching processes are improved etch-rate control and reduced surface roughness. Finally, we also demonstrated lateral recess of Mo word lines in 3D-NAND like structures resulting in uniformly recessed, straight-walled word lines.
{"title":"Controlled ALE-type recess of molybdenum for future logic and memory applications","authors":"A. Pacco, Teppei Nakano, A. Iwasaki, Shota Iwahata, E. Sanchez","doi":"10.1109/IITC51362.2021.9537407","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537407","url":null,"abstract":"Molybdenum (Mo) is a promising metal for applications requiring low resistivity interconnects or contact lines in small dimensions. Etching of polycrystalline metals like Mo with conventional etching methods can be challenging because of the increased surface roughness and non-uniform recess. In this paper we describe a novel sequential etching method comprising two steps. The first step is an oxidation step in ozone (O3) at elevated temperatures in the range of 180°C–290°C resulting in a smooth metal/oxide interface. The second step is a selective oxide dissolution. The benefits of this cyclic, ALE-type recess over continuous wet-etching processes are improved etch-rate control and reduced surface roughness. Finally, we also demonstrated lateral recess of Mo word lines in 3D-NAND like structures resulting in uniformly recessed, straight-walled word lines.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73489368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537409
Suhr Dominique, Mevellec Vincent, Thiam Mikailou, Idier Jonathan, Raynal Frédéric, Berthon Hermine, Perrault Elisa, Hann Nicolas, Doussot Céline, Kim Yeeseul, Baus Mathilde, Lakhdari Amine, Guittet Gaëlle, Caillard Louis
As the number of wordlines has reached 128 layers in the realm of 3D-NAND, several challenges have emerged to produce these structures. Among these is metallization of the connection made with Tungsten. This paper explores Nickel alloys as an alternative metal. Several key data are presented to validate this new concept.
{"title":"An alternative to Tungsten in 3D-NAND technology","authors":"Suhr Dominique, Mevellec Vincent, Thiam Mikailou, Idier Jonathan, Raynal Frédéric, Berthon Hermine, Perrault Elisa, Hann Nicolas, Doussot Céline, Kim Yeeseul, Baus Mathilde, Lakhdari Amine, Guittet Gaëlle, Caillard Louis","doi":"10.1109/IITC51362.2021.9537409","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537409","url":null,"abstract":"As the number of wordlines has reached 128 layers in the realm of 3D-NAND, several challenges have emerged to produce these structures. Among these is metallization of the connection made with Tungsten. This paper explores Nickel alloys as an alternative metal. Several key data are presented to validate this new concept.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81671876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537450
N. Breil
In this invited paper, we demonstrate that the contact interface resistance is a major bottleneck for advanced FinFET performance scaling (38% of the external resistance at 45nm gate pitch). After analyzing the key components defining the contact interface resistivity (active doping level, Schottky barrier height, contact area), we review the engineering techniques available to improve this critical bottleneck. We propose that the contact area engineering is an essential engineering direction to unlock the benefits of advanced CMOS technology performance and discuss some related processing techniques such as the superconformal Ti deposition.
{"title":"Contact module progress and challenges in advanced CMOS technologies","authors":"N. Breil","doi":"10.1109/IITC51362.2021.9537450","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537450","url":null,"abstract":"In this invited paper, we demonstrate that the contact interface resistance is a major bottleneck for advanced FinFET performance scaling (38% of the external resistance at 45nm gate pitch). After analyzing the key components defining the contact interface resistivity (active doping level, Schottky barrier height, contact area), we review the engineering techniques available to improve this critical bottleneck. We propose that the contact area engineering is an essential engineering direction to unlock the benefits of advanced CMOS technology performance and discuss some related processing techniques such as the superconformal Ti deposition.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89511980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537311
H. Kawasaki, M. Iwashita, H. Warashina, H. Nagai, K. Iwai, H. Komatsu, Y. Ozaki, G. Pattanaik
Selective deposition of Cu diffusion barrier metal layer on dielectric with Self-Assembled Monolayer (SAM) has been demonstrated. Via resistance is expected to decrease by eliminating the barrier at via bottom in dual- and semi-damascene structure. In this study, we report the evaluation of SAMs to enable selective ALD-barrier metal deposition and, as an example, we show Cu via prefill integration using ELD-Cu with no barrier / liner at via bottom and no seam void for metal filling.
{"title":"Advanced Damascene integration using selective deposition of barrier metal with Self Assemble Monolayer","authors":"H. Kawasaki, M. Iwashita, H. Warashina, H. Nagai, K. Iwai, H. Komatsu, Y. Ozaki, G. Pattanaik","doi":"10.1109/IITC51362.2021.9537311","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537311","url":null,"abstract":"Selective deposition of Cu diffusion barrier metal layer on dielectric with Self-Assembled Monolayer (SAM) has been demonstrated. Via resistance is expected to decrease by eliminating the barrier at via bottom in dual- and semi-damascene structure. In this study, we report the evaluation of SAMs to enable selective ALD-barrier metal deposition and, as an example, we show Cu via prefill integration using ELD-Cu with no barrier / liner at via bottom and no seam void for metal filling.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"201 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75987882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537498
Youn-Hye Kim, Y. Kotsugi, Taehoon Cheon, R. Ramesh, Soo‐Hyun Kim
We report the ALD RuO2 process using a new Ru metalorganic precursor, tricarbonyl (trimethylenemethane) ruthenium [Ru(TMM)(CO)3], and molecular oxygen (O2) as a reactant at the relatively low temperature of 180 °C for a diffusion barrier application of Ru interconnect. RuO2 thin films could be prepared by controlling the reactant and precursor pulsing time ratio (to2/tRu) and the deposition pressure. The formation of RuO2 phase is generally favorable at a higher pulsing time ratio (to2/tRu) and deposition pressure. It was also demonstrated that Ru single, the mixture phase of Ru and RuO2, and RuO2 single phase could be controllably grown with deposition condition. The RuO2 films deposited under optimized pulsing conditions showed resistivity of ~103 μΩ·cm, and a growth rate of ~0.056 nm/cycle with short incubation cycles of ~15 cycles. The diffusion barrier performance of ALD-RuO2 thin films against Ru is analyzed using XRD and electrical impedance analysis. According to both analyses, the non-barrier layer structure [ALD-Ru (50 nm)/Si] began to lose its stability by forming ruthenium silcides at 750 °C, while the structure with a barrier layer [ALD-Ru/ALD-RuO2 (5 nm)/Si] were stable up to 850 °C.
{"title":"Atomic layer deposition of RuO2 using a new metalorganic precursor as a diffusion barrier for Ru interconnect","authors":"Youn-Hye Kim, Y. Kotsugi, Taehoon Cheon, R. Ramesh, Soo‐Hyun Kim","doi":"10.1109/IITC51362.2021.9537498","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537498","url":null,"abstract":"We report the ALD RuO<inf>2</inf> process using a new Ru metalorganic precursor, tricarbonyl (trimethylenemethane) ruthenium [Ru(TMM)(CO)<inf>3</inf>], and molecular oxygen (O<inf>2</inf>) as a reactant at the relatively low temperature of 180 °C for a diffusion barrier application of Ru interconnect. RuO<inf>2</inf> thin films could be prepared by controlling the reactant and precursor pulsing time ratio (t<inf>o2</inf>/t<inf>Ru</inf>) and the deposition pressure. The formation of RuO<inf>2</inf> phase is generally favorable at a higher pulsing time ratio (t<inf>o2</inf>/t<inf>Ru</inf>) and deposition pressure. It was also demonstrated that Ru single, the mixture phase of Ru and RuO<inf>2</inf>, and RuO<inf>2</inf> single phase could be controllably grown with deposition condition. The RuO<inf>2</inf> films deposited under optimized pulsing conditions showed resistivity of ~103 μΩ·cm, and a growth rate of ~0.056 nm/cycle with short incubation cycles of ~15 cycles. The diffusion barrier performance of ALD-RuO<inf>2</inf> thin films against Ru is analyzed using XRD and electrical impedance analysis. According to both analyses, the non-barrier layer structure [ALD-Ru (50 nm)/Si] began to lose its stability by forming ruthenium silcides at 750 °C, while the structure with a barrier layer [ALD-Ru/ALD-RuO<inf>2</inf> (5 nm)/Si] were stable up to 850 °C.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"35 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87015537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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