Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400746
R. Mialtu
This paper introduces an original approach to system modeling for performance analysis and optimization. The method presented herein theoretical background is the mathematical field of affine arithmetic chosen for its intrinsic data representation optimal to analysis of the mitigation of variations and refinement of deviations and error analysis. The chosen language of SystemVerilog is beneficial for it is allowing the integration of the validation process and of the verification process for the specific class of mixed signal electrical circuits and systems.
{"title":"A SystemVerilog approach in system validation with affine arithmetic","authors":"R. Mialtu","doi":"10.1109/SMICND.2012.6400746","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400746","url":null,"abstract":"This paper introduces an original approach to system modeling for performance analysis and optimization. The method presented herein theoretical background is the mathematical field of affine arithmetic chosen for its intrinsic data representation optimal to analysis of the mitigation of variations and refinement of deviations and error analysis. The chosen language of SystemVerilog is beneficial for it is allowing the integration of the validation process and of the verification process for the specific class of mixed signal electrical circuits and systems.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"60 1","pages":"407-410"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84792303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400763
M. Antoniou, E. Tee, S. Pilkington, D. K. Pal, F. Udrea, A. Hoelke
This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology.
{"title":"The lateral superjunction PSOI LIGBT and LDMOSFET","authors":"M. Antoniou, E. Tee, S. Pilkington, D. K. Pal, F. Udrea, A. Hoelke","doi":"10.1109/SMICND.2012.6400763","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400763","url":null,"abstract":"This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"12 1","pages":"351-354"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81971923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400649
E. Golovins, S. Sinha
Design of the radio systems operating in the 60 GHz band raises a number of questions regarding the frequency-domain performance of transceiver subsystems. This work, combining the baseband and RF parts of the architecture, shows that a system-level simulation model allows identifying bottlenecks in the integrated functioning of various subsystems. Comparative error rate analysis highlights the propagation channel effect domination in performance limiting.
{"title":"System-level simulator of radio communication in the EHF band","authors":"E. Golovins, S. Sinha","doi":"10.1109/SMICND.2012.6400649","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400649","url":null,"abstract":"Design of the radio systems operating in the 60 GHz band raises a number of questions regarding the frequency-domain performance of transceiver subsystems. This work, combining the baseband and RF parts of the architecture, shows that a system-level simulation model allows identifying bottlenecks in the integrated functioning of various subsystems. Comparative error rate analysis highlights the propagation channel effect domination in performance limiting.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"131 1","pages":"221-224"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76419483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400662
D. Vasilache, M. Chistè, S. Colpo, F. Giacomozzi, B. Margesin
This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.
{"title":"Wafer resistivity influence over DRIE processes for TSVs manufacturing","authors":"D. Vasilache, M. Chistè, S. Colpo, F. Giacomozzi, B. Margesin","doi":"10.1109/SMICND.2012.6400662","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400662","url":null,"abstract":"This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"150 1","pages":"175-178"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75178861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400659
N. Maticiuc, J. Hiie, T. Potlog
This work evaluates the efficacy of the chemical bath deposition (CBD) and technological conditions for preparation of homogeneous CdS thin films with high transparency and low resistivity. The effects of various technological parameters (magnetic agitation of solution, pre-treatment in vacuum, annealing in hydrogen atmosphere, and concentration of chlorine as dopant in the deposition bath) on morphology, transmittance and electrical properties were studied. Together, these results show that CBD is an efficient technique, helpful for the scaling-up of the manufacturing process of suitable and reproducible window n-type CdS layers for further solar cell application.
{"title":"Influence of technological conditions on the properties of CBD CdS layers","authors":"N. Maticiuc, J. Hiie, T. Potlog","doi":"10.1109/SMICND.2012.6400659","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400659","url":null,"abstract":"This work evaluates the efficacy of the chemical bath deposition (CBD) and technological conditions for preparation of homogeneous CdS thin films with high transparency and low resistivity. The effects of various technological parameters (magnetic agitation of solution, pre-treatment in vacuum, annealing in hydrogen atmosphere, and concentration of chlorine as dopant in the deposition bath) on morphology, transmittance and electrical properties were studied. Together, these results show that CBD is an efficient technique, helpful for the scaling-up of the manufacturing process of suitable and reproducible window n-type CdS layers for further solar cell application.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"29 1","pages":"187-190"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91201612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400729
D. Ducu, A. Manolescu
This paper presents a new circuit realization for current mode continuous time sigma delta modulator. In this sigma delta convertor for implementation of integrators in loop filter, operational floating conveyors are employed. The modulator is designed in 0.18μm TSMC CMOS technology and features low power consumption (<;3mW), low supply voltage (±1.8), and wide dynamic range (>;70db). The performance of the circuits was demonstrated using HSPICE at low voltage operation of ±1.8V.
{"title":"A continuous time sigma delta modulator with operational floating integrator","authors":"D. Ducu, A. Manolescu","doi":"10.1109/SMICND.2012.6400729","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400729","url":null,"abstract":"This paper presents a new circuit realization for current mode continuous time sigma delta modulator. In this sigma delta convertor for implementation of integrators in loop filter, operational floating conveyors are employed. The modulator is designed in 0.18μm TSMC CMOS technology and features low power consumption (<;3mW), low supply voltage (±1.8), and wide dynamic range (>;70db). The performance of the circuits was demonstrated using HSPICE at low voltage operation of ±1.8V.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"73 1","pages":"463-466"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88156610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400688
S. Bellucci, I. Sacco, F. Micciulla, A. Dąbrowska, A. Huczko, E. Caponetti, M. Floriano, A. Dinescu
Nanocomposites are nowadays the most promising new materials due to their unique properties (such as high mechanical strength, chemical and thermal resistance). The nanocomposite matrix is blended with a nanostructured filler. In this study, Silicon Carbide nanofibers (NFSiC) and their bundles were tested as a reinforcement of two epoxy resins: EPIKOTE 828 and EL 20. PAP-4 (33 phr) and P-900 (40 phr) were used as hardeners in the two cases, respectively. Several samples were prepared in the range between 0.1 and 5 % wt for both types of resins and fillers (NFSiC and NFSiC bundles). Mechanical and electrical properties were tested. The fillers were obtained using a new simple, fast, low-cost and efficient method to synthesize nanomaterials: Self-propagating High-Temperature Synthesis (SHS). The produced nanofillers were analyzed by Scanning Electron Microscope (SEM), Trasmission Electron Microscope (TEM). They were purified, as well. The nanocomposites obtained using such nanofillers were assayed by SEM and TEM techniques.
{"title":"Preliminary studies on nanocomposite based on high quality Silicon Carbide nanofibers","authors":"S. Bellucci, I. Sacco, F. Micciulla, A. Dąbrowska, A. Huczko, E. Caponetti, M. Floriano, A. Dinescu","doi":"10.1109/SMICND.2012.6400688","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400688","url":null,"abstract":"Nanocomposites are nowadays the most promising new materials due to their unique properties (such as high mechanical strength, chemical and thermal resistance). The nanocomposite matrix is blended with a nanostructured filler. In this study, Silicon Carbide nanofibers (NFSiC) and their bundles were tested as a reinforcement of two epoxy resins: EPIKOTE 828 and EL 20. PAP-4 (33 phr) and P-900 (40 phr) were used as hardeners in the two cases, respectively. Several samples were prepared in the range between 0.1 and 5 % wt for both types of resins and fillers (NFSiC and NFSiC bundles). Mechanical and electrical properties were tested. The fillers were obtained using a new simple, fast, low-cost and efficient method to synthesize nanomaterials: Self-propagating High-Temperature Synthesis (SHS). The produced nanofillers were analyzed by Scanning Electron Microscope (SEM), Trasmission Electron Microscope (TEM). They were purified, as well. The nanocomposites obtained using such nanofillers were assayed by SEM and TEM techniques.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"43 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88580783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400735
S. Rosu, C. Radoi, M. Teodorescu, P. Guglielmi, I. Bojoi, M. Pastorelli
This paper presents a simple power loss estimation method for inverter-fed low power AC asynchronous and synchronous motors. The method uses a simulation based DC/AC converter power loss estimation based on datasheet parameters and load characteristics like measured phase resistance and current phase delay. A current control scheme is used to impose a constant current at various speeds. Using this approach both asynchronous and synchronous motors can be used as a load. Total power loss is measured as the DC Link current by an amperemeter avoiding the use of complicated measurement systems.
{"title":"A simple method for power loss estimation in PWM inverter-fed motors","authors":"S. Rosu, C. Radoi, M. Teodorescu, P. Guglielmi, I. Bojoi, M. Pastorelli","doi":"10.1109/SMICND.2012.6400735","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400735","url":null,"abstract":"This paper presents a simple power loss estimation method for inverter-fed low power AC asynchronous and synchronous motors. The method uses a simulation based DC/AC converter power loss estimation based on datasheet parameters and load characteristics like measured phase resistance and current phase delay. A current control scheme is used to impose a constant current at various speeds. Using this approach both asynchronous and synchronous motors can be used as a load. Total power loss is measured as the DC Link current by an amperemeter avoiding the use of complicated measurement systems.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"44 1","pages":"445-448"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88586475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400645
L. Sirbu, L. Ghimpu, R. Muller, I. Voda, I. Tiginyanu, V. Ursaki, T. Dascălu
In this paper, we will review the electrowetting on dielectric (EWOD) principles applied to microfluidic devices. We replaced the usually used teflon surface by ZnO transparent film in order to obtain a device with an optical weak absorption in the diapason ranged from VIS to far-MIR and THz waves. We studied the piezoelectric characteristics of ZnO films obtained by RF magnetron sputtering in Ar+O2 plasma. ZnO films have been grown on SiO2/Si(100) substrate using a zinc oxide target. The morphological characteristics of the films were investigated by atomic force microscopy (AFM). We present the THz spectra from ZnO films.
{"title":"Hydrophobic ZnO used in EWOD technology and SAW devices for better bio-fluid slip AT microchannel walls controlled by DC pulses","authors":"L. Sirbu, L. Ghimpu, R. Muller, I. Voda, I. Tiginyanu, V. Ursaki, T. Dascălu","doi":"10.1109/SMICND.2012.6400645","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400645","url":null,"abstract":"In this paper, we will review the electrowetting on dielectric (EWOD) principles applied to microfluidic devices. We replaced the usually used teflon surface by ZnO transparent film in order to obtain a device with an optical weak absorption in the diapason ranged from VIS to far-MIR and THz waves. We studied the piezoelectric characteristics of ZnO films obtained by RF magnetron sputtering in Ar+O2 plasma. ZnO films have been grown on SiO2/Si(100) substrate using a zinc oxide target. The morphological characteristics of the films were investigated by atomic force microscopy (AFM). We present the THz spectra from ZnO films.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"25 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88686248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SMICND.2012.6400738
Valeriu Beiu, L. Iordaconiu, A. Beg, W. Ibrahim, F. Kharbash
This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (VTH); and also (iv) reduce VTH variations (σVTH).
{"title":"Low power and highly reliable gates using arrays of optimally sized transistors","authors":"Valeriu Beiu, L. Iordaconiu, A. Beg, W. Ibrahim, F. Kharbash","doi":"10.1109/SMICND.2012.6400738","DOIUrl":"https://doi.org/10.1109/SMICND.2012.6400738","url":null,"abstract":"This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (VTH); and also (iv) reduce VTH variations (σVTH).","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"5 1","pages":"433-436"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81639439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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