Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994465
B. Dellabetta, M. J. Gilbert
Post-CMOS logic in bilayer graphene is very promising due to the possibility of observing room temperature collective states. An excitonic superfluid is predicted to form in double layer graphene systems at room temperature if the two individual monolayers of graphene are separated by an oxide no more than a few nanometers thick [1]. Recent experiments have shown evidence of interaction enhanced transport in double layer graphene [2], but there is a significant discrepancy in the quality of the two graphene layers which may be occluding the phase transition. We present and compare the performance characteristics of ideal and disordered double layer graphene systems at room temperature in the purported regime of superfluidity. We perform quantum transport calculations on double layer graphene using the Non-Equilibrium Green's Function (NEGF) formalism in an effort to elucidate the evolution of a BEC under non-equilibrium conditions in the presence of lattice defects. We find that lattice defects spread throughout the channel can degrade interlayer current by 30%, but disorder concentrated near the contacts causes a much more significant reduction of 80% in interlayer current. We also find that steady-state spontaneous coherence is lost for defect concentrations greater than 4%; a very clean system is therefore necessary for potential post-CMOS logic applications.
{"title":"Effect of disorder on superfluidity in double layer graphene","authors":"B. Dellabetta, M. J. Gilbert","doi":"10.1109/DRC.2011.5994465","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994465","url":null,"abstract":"Post-CMOS logic in bilayer graphene is very promising due to the possibility of observing room temperature collective states. An excitonic superfluid is predicted to form in double layer graphene systems at room temperature if the two individual monolayers of graphene are separated by an oxide no more than a few nanometers thick [1]. Recent experiments have shown evidence of interaction enhanced transport in double layer graphene [2], but there is a significant discrepancy in the quality of the two graphene layers which may be occluding the phase transition. We present and compare the performance characteristics of ideal and disordered double layer graphene systems at room temperature in the purported regime of superfluidity. We perform quantum transport calculations on double layer graphene using the Non-Equilibrium Green's Function (NEGF) formalism in an effort to elucidate the evolution of a BEC under non-equilibrium conditions in the presence of lattice defects. We find that lattice defects spread throughout the channel can degrade interlayer current by 30%, but disorder concentrated near the contacts causes a much more significant reduction of 80% in interlayer current. We also find that steady-state spontaneous coherence is lost for defect concentrations greater than 4%; a very clean system is therefore necessary for potential post-CMOS logic applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114199843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994407
J. Heo, Hyun‐Jong Chung, Sung-Hoon Lee, Heejun Yang, Jaikwang Shin, U. Chung, S. Seo
Recent success of inexpensive and high-throughput chemical vapor deposition (CVD) growth [1] of graphene on Ni or Cu substrates has shown promises for potential industrial applications such as transparent electrodes [2] and field effect transistors (FET). [3] However, high-coverage uniform growth of monolayer graphene on a wafer scale is still a major obstruction, which impedes high yield integration of high performance field effect devices. Here, we report the first demonstration of high quality top-gated graphene field effect devices on 150 mm substrates exploiting unprecedented homogeneous CVD growth of monolayer graphene.
{"title":"Integration of high quality top-gated graphene field effect devices on 150 mm substrate","authors":"J. Heo, Hyun‐Jong Chung, Sung-Hoon Lee, Heejun Yang, Jaikwang Shin, U. Chung, S. Seo","doi":"10.1109/DRC.2011.5994407","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994407","url":null,"abstract":"Recent success of inexpensive and high-throughput chemical vapor deposition (CVD) growth [1] of graphene on Ni or Cu substrates has shown promises for potential industrial applications such as transparent electrodes [2] and field effect transistors (FET). [3] However, high-coverage uniform growth of monolayer graphene on a wafer scale is still a major obstruction, which impedes high yield integration of high performance field effect devices. Here, we report the first demonstration of high quality top-gated graphene field effect devices on 150 mm substrates exploiting unprecedented homogeneous CVD growth of monolayer graphene.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994435
Hui-Wen Cheng, Y. Chiu, Yiming Li
The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.
{"title":"3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices","authors":"Hui-Wen Cheng, Y. Chiu, Yiming Li","doi":"10.1109/DRC.2011.5994435","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994435","url":null,"abstract":"The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994504
S. Kolluri, S. Keller, S. Denbaars, U. Mishra
This paper presents the X-band and C-band power performance of MOCVD grown N-polar AlGaN/GaN MIS-HEMTs grown on semi-insulating SiC substrates. Additionally, an Al2O3 based etch stop technology was demonstrated for improving the manufacturability of N-polar GaN HEMTs with SixNy passivation. The reported output power densities of 16.7 W/mm at 10 GHz and 20.7 W/mm at 4 GHz represent the highest reported values so far for an N-polar device, at both of these frequencies.
{"title":"N-Polar AlGaN/GaN MIS-HEMTs on SiC with a 16.7 W/mm power density at 10 GHz using an Al2O3 based etch stop technology for the gate recess","authors":"S. Kolluri, S. Keller, S. Denbaars, U. Mishra","doi":"10.1109/DRC.2011.5994504","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994504","url":null,"abstract":"This paper presents the X-band and C-band power performance of MOCVD grown N-polar AlGaN/GaN MIS-HEMTs grown on semi-insulating SiC substrates. Additionally, an Al2O3 based etch stop technology was demonstrated for improving the manufacturability of N-polar GaN HEMTs with SixNy passivation. The reported output power densities of 16.7 W/mm at 10 GHz and 20.7 W/mm at 4 GHz represent the highest reported values so far for an N-polar device, at both of these frequencies.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994413
S. Koester
The low density of states in graphene makes it possible for the quantum capacitance to be of the same order of magnitude as the oxide capacitance for experimentally achievable gate dielectric thicknesses [1]. This property, combined with the fact that the density of states varies as a function of energy, means that the capacitance in a metal-oxide-graphene capacitor can be tuned by varying the carrier concentration [2]. The very high mobility and zero band gap in graphene also allow it to remain conductive throughout the entire tuning range, making graphene an idea material to realize a high quality factor (Q) variable capacitor (varactor). If combined with an on-chip inductor to form an LC oscillator circuit, graphene varactors could enable a new class of ultra-compact sensors with wireless readout capability. Compared to MEMS-based varactors [3], the extremely-large capacitance per unit area of graphene varactors should allow orders-of-magnitude improvement in scalability, a vital feature for numerous applications including in vivo sensing where small size is critical. In this abstract, the device concept is described and simulated performance projections are provided. The main findings in this study are that wide frequency tuning ratios (> 50%) and high Q (> 40 at 1 GHz) are possible using realistic assumptions for the graphene properties, device dimensions and parasitic resistances.
{"title":"Graphene quantum capacitance varactors for wireless sensing applications","authors":"S. Koester","doi":"10.1109/DRC.2011.5994413","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994413","url":null,"abstract":"The low density of states in graphene makes it possible for the quantum capacitance to be of the same order of magnitude as the oxide capacitance for experimentally achievable gate dielectric thicknesses [1]. This property, combined with the fact that the density of states varies as a function of energy, means that the capacitance in a metal-oxide-graphene capacitor can be tuned by varying the carrier concentration [2]. The very high mobility and zero band gap in graphene also allow it to remain conductive throughout the entire tuning range, making graphene an idea material to realize a high quality factor (Q) variable capacitor (varactor). If combined with an on-chip inductor to form an LC oscillator circuit, graphene varactors could enable a new class of ultra-compact sensors with wireless readout capability. Compared to MEMS-based varactors [3], the extremely-large capacitance per unit area of graphene varactors should allow orders-of-magnitude improvement in scalability, a vital feature for numerous applications including in vivo sensing where small size is critical. In this abstract, the device concept is described and simulated performance projections are provided. The main findings in this study are that wide frequency tuning ratios (> 50%) and high Q (> 40 at 1 GHz) are possible using realistic assumptions for the graphene properties, device dimensions and parasitic resistances.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117010870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994475
J. Sun, R. Robertazzi, J. Nowak, P. Trouilloud, G. Hu, M. Gaidis, S. Brown, D. Abraham, E. O'Sullivan, W. Gallagher, D. Worledge, A. Kent
PMA spin-torque switchable junctions have been demonstrated with lower switching current and faster switching speed compared to IMA devices. They are promising for further technology exploration in solid-state memory applications.
{"title":"Spin-torque switchable perpendicular magnetic junctions for solid-state memory","authors":"J. Sun, R. Robertazzi, J. Nowak, P. Trouilloud, G. Hu, M. Gaidis, S. Brown, D. Abraham, E. O'Sullivan, W. Gallagher, D. Worledge, A. Kent","doi":"10.1109/DRC.2011.5994475","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994475","url":null,"abstract":"PMA spin-torque switchable junctions have been demonstrated with lower switching current and faster switching speed compared to IMA devices. They are promising for further technology exploration in solid-state memory applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131294960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994446
M. Ramón, A. Gupta, C. Corbet, D. Ferrer, H. Movva, G. Carpenter, L. Colombo, G. Bourianoff, M. Doczy, D. Akinwande, E. Tutuc, S. Banerjee
There has been great interest in methods for the synthesis of high-quality, large-area graphene films, as required for practical applications in the electronics industry. In particular, recent developments in chemical vapor deposition (CVD) methods have shown a promising approach to grow large-area graphene on metal substrates by catalyzed CVD growth [1]. Reports of CVD growth on Cu and Ni are common [1–3]; however, there have been few efforts to grow graphene on Co [4], and attempts to grow graphene on Co/SiO2/Si resulted in very small domains of predominantly multilayer graphene that were not suitable for transistor fabrication. Unlike Ni, Co is attractive due to the low lattice mismatch (< 2%) between graphene and the Co (0001) surface, and Co exhibits greater compatibility with Si than Cu, which is a deep trap in Si and a fast diffuser. Here we have demonstrated graphene field-effect transistors (GFETs) fabricated using large-area monolayer graphene grown by catalyzed CVD on Co films.
{"title":"Graphene field-effect transistors using large-area monolayer graphene grown by chemical vapor deposition on Co thin films","authors":"M. Ramón, A. Gupta, C. Corbet, D. Ferrer, H. Movva, G. Carpenter, L. Colombo, G. Bourianoff, M. Doczy, D. Akinwande, E. Tutuc, S. Banerjee","doi":"10.1109/DRC.2011.5994446","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994446","url":null,"abstract":"There has been great interest in methods for the synthesis of high-quality, large-area graphene films, as required for practical applications in the electronics industry. In particular, recent developments in chemical vapor deposition (CVD) methods have shown a promising approach to grow large-area graphene on metal substrates by catalyzed CVD growth [1]. Reports of CVD growth on Cu and Ni are common [1–3]; however, there have been few efforts to grow graphene on Co [4], and attempts to grow graphene on Co/SiO2/Si resulted in very small domains of predominantly multilayer graphene that were not suitable for transistor fabrication. Unlike Ni, Co is attractive due to the low lattice mismatch (< 2%) between graphene and the Co (0001) surface, and Co exhibits greater compatibility with Si than Cu, which is a deep trap in Si and a fast diffuser. Here we have demonstrated graphene field-effect transistors (GFETs) fabricated using large-area monolayer graphene grown by catalyzed CVD on Co films.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134207093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994419
J. Siddiqui, J. Phillips, K. Leedy, B. Bayraktaroglu
ZnO thin film electronics have received much attention due to the relatively high electron mobility of ZnO thin films in comparison to amorphous silicon (a-Si) and organic thin films. There is significant interest in using ZnO thin film transistors (TFTs), or similar oxides such as InGaZnO and zinc tin oxide, to replace a-Si TFTs in large area display technologies such as active matrix liquid crystal display devices and active matrix organic light-emitting displays where transparency in the visible range and high carrier mobilities are significant advantages. In addition, the integration of high dielectric constant (high-k) dielectrics in ZnO TFTs has demonstrated performance advantages including reduced operating voltage, increased Ion/Ioff ratios, and larger transconductance. HfO2 has emerged as a high-k dielectric of choice for both silicon microelectronics and thin film electronics due to the high dielectric constant (εr ∼ 25ε0), low leakage current, and low synthesis temperature. Voltage stability is an important figure of merit for many TFT applications and much work has been done to characterize the voltage stability of a-Si and poly-crystalline silicon (p-Si) TFTs. Extensive Bias-Temperature-Stress (BTS) studies have been carried out on a-Si and p-Si TFTs to track the threshold voltage (VTH), subthreshold slope (S), mobility (μ), and grain boundary trap creation (NTG) over time and to correlate TFT parameter instabilities with physical mechanisms that include charge trapping in the gate oxide and charge state creation in the oxide, interface, and p-Si grain boundaries. Prior studies on the stability of ZnO TFTs have indicated threshold voltage shifts (ΔVTH) with the same polarity as the stress voltage (VSTR) that increase with time and that S remains unchanged below a certain VSTR, but will degrade with time above this value [1–3]. Ability to recover pre-stress characteristics with and without post-stress treatments has also been reported. Further investigation is desired to both understand the device instability behavior dependence on temperature and gate-bias and to determine the physical origins governing the instabilities in this important material system. In this work, the instabilities of HfO2/ZnO TFTs are studied by BTS investigation.
{"title":"Bias temperature stress analysis of ZnO thin film transistors with HfO2 gate dielectrics","authors":"J. Siddiqui, J. Phillips, K. Leedy, B. Bayraktaroglu","doi":"10.1109/DRC.2011.5994419","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994419","url":null,"abstract":"ZnO thin film electronics have received much attention due to the relatively high electron mobility of ZnO thin films in comparison to amorphous silicon (a-Si) and organic thin films. There is significant interest in using ZnO thin film transistors (TFTs), or similar oxides such as InGaZnO and zinc tin oxide, to replace a-Si TFTs in large area display technologies such as active matrix liquid crystal display devices and active matrix organic light-emitting displays where transparency in the visible range and high carrier mobilities are significant advantages. In addition, the integration of high dielectric constant (high-k) dielectrics in ZnO TFTs has demonstrated performance advantages including reduced operating voltage, increased Ion/Ioff ratios, and larger transconductance. HfO2 has emerged as a high-k dielectric of choice for both silicon microelectronics and thin film electronics due to the high dielectric constant (εr ∼ 25ε0), low leakage current, and low synthesis temperature. Voltage stability is an important figure of merit for many TFT applications and much work has been done to characterize the voltage stability of a-Si and poly-crystalline silicon (p-Si) TFTs. Extensive Bias-Temperature-Stress (BTS) studies have been carried out on a-Si and p-Si TFTs to track the threshold voltage (VTH), subthreshold slope (S), mobility (μ), and grain boundary trap creation (NTG) over time and to correlate TFT parameter instabilities with physical mechanisms that include charge trapping in the gate oxide and charge state creation in the oxide, interface, and p-Si grain boundaries. Prior studies on the stability of ZnO TFTs have indicated threshold voltage shifts (ΔVTH) with the same polarity as the stress voltage (VSTR) that increase with time and that S remains unchanged below a certain VSTR, but will degrade with time above this value [1–3]. Ability to recover pre-stress characteristics with and without post-stress treatments has also been reported. Further investigation is desired to both understand the device instability behavior dependence on temperature and gate-bias and to determine the physical origins governing the instabilities in this important material system. In this work, the instabilities of HfO2/ZnO TFTs are studied by BTS investigation.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994525
N. Toledo, S. C. Cruz, C. Neufeld, J. R. Lang, M. Scarpulla, T. Buehl, A. Gossard, S. Denbaars, J. Speck, U. Mishra
III-nitrides have recently been demonstrated as potential photovoltaic device material particularly in the high-energy portion of the solar spectrum [1–2]. The large lattice mismatch between InN and GaN however, makes it difficult to grow good quality high In-composition InGaN films for low bandgap subcells. The integration of III-N based solar cells, which have currently been demonstrated to work well above 2.0 eV, with mature IV and III–V based solar cell technologies, which work well at bandgaps ≤ 2.0 eV, has the potential to improve the efficiency of current multi-junction solar cells. In this paper, we present the first on-wafer integration of InGaN/GaN solar cells with non-III-nitride (GaAs) solar cells.
iii -氮化物最近被证明是一种潜在的光伏器件材料，特别是在太阳光谱的高能部分[1-2]。然而，InN和GaN之间的大晶格不匹配使得难以在低带隙亚电池中生长出高质量的高成分InGaN薄膜。III-N基太阳能电池(目前已被证明能在2.0 eV以上工作)与成熟的IV和III-V基太阳能电池技术(能在≤2.0 eV的带隙下工作)的集成，有可能提高当前多结太阳能电池的效率。在本文中，我们首次提出了InGaN/GaN太阳能电池与非iii -氮化物(GaAs)太阳能电池的片上集成。
{"title":"Integrated non-III-nitride/III-nitride tandem solar cell","authors":"N. Toledo, S. C. Cruz, C. Neufeld, J. R. Lang, M. Scarpulla, T. Buehl, A. Gossard, S. Denbaars, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.5994525","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994525","url":null,"abstract":"III-nitrides have recently been demonstrated as potential photovoltaic device material particularly in the high-energy portion of the solar spectrum [1–2]. The large lattice mismatch between InN and GaN however, makes it difficult to grow good quality high In-composition InGaN films for low bandgap subcells. The integration of III-N based solar cells, which have currently been demonstrated to work well above 2.0 eV, with mature IV and III–V based solar cell technologies, which work well at bandgaps ≤ 2.0 eV, has the potential to improve the efficiency of current multi-junction solar cells. In this paper, we present the first on-wafer integration of InGaN/GaN solar cells with non-III-nitride (GaAs) solar cells.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133950807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994468
E. Garlid, Q. Hu, C. Geppert, M. Chan, C. Palmstrøm, P. Crowell
There has been extensive theoretical discussion of the spin Hall effect (SHE) and the various ways that it could be exploited to generate or manipulate spin currents. However, only a handful of recent experiments have investigated this effect, and in semiconductor materials they have relied on optical techniques to either detect or generate spins [1,2].
{"title":"Electrical measurement of the spin Hall effects in Fe/InxGa1−xAs heterostructures","authors":"E. Garlid, Q. Hu, C. Geppert, M. Chan, C. Palmstrøm, P. Crowell","doi":"10.1109/DRC.2011.5994468","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994468","url":null,"abstract":"There has been extensive theoretical discussion of the spin Hall effect (SHE) and the various ways that it could be exploited to generate or manipulate spin currents. However, only a handful of recent experiments have investigated this effect, and in semiconductor materials they have relied on optical techniques to either detect or generate spins [1,2].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123992831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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