Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994469
Jing Li, I. Appelbaum
Recent advances in the development of techniques for electrical injection and detection of spin-polarized electrons in silicon have aroused intensive research on exploiting devices and circuits that utilize the spin degree of freedom [1–3] as well as electron charge in this dominant material of the semiconductor integrated circuits industry.
{"title":"Simultaneous spin and charge transport in gated Si devices","authors":"Jing Li, I. Appelbaum","doi":"10.1109/DRC.2011.5994469","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994469","url":null,"abstract":"Recent advances in the development of techniques for electrical injection and detection of spin-polarized electrons in silicon have aroused intensive research on exploiting devices and circuits that utilize the spin degree of freedom [1–3] as well as electron charge in this dominant material of the semiconductor integrated circuits industry.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123155886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994412
S. Islam, M. Bae, V. Dorgan, E. Pop
Recent studies using infrared (IR) imaging of graphene transistors [1,2] have revealed substantial Joule heating under realistic operating conditions for graphene-on-insulator (GOI) devices. Here we use simulations calibrated against experimental data to examine the trends of performance degradation caused by self-heating as a function of insulator (SiO2) thickness. We also examine both unipolar and ambipolar operating conditions, and find that peak channel temperatures are proportional to oxide thickness for the unipolar case (as would be expected), but for ambipolar operation an optimum oxide substrate thickness exists (∼80 nm) which minimizes peak temperature, due to competing electrostatic and thermal effects.
{"title":"Effect of oxide thickness scaling on self-heating in graphene transistors","authors":"S. Islam, M. Bae, V. Dorgan, E. Pop","doi":"10.1109/DRC.2011.5994412","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994412","url":null,"abstract":"Recent studies using infrared (IR) imaging of graphene transistors [1,2] have revealed substantial Joule heating under realistic operating conditions for graphene-on-insulator (GOI) devices. Here we use simulations calibrated against experimental data to examine the trends of performance degradation caused by self-heating as a function of insulator (SiO2) thickness. We also examine both unipolar and ambipolar operating conditions, and find that peak channel temperatures are proportional to oxide thickness for the unipolar case (as would be expected), but for ambipolar operation an optimum oxide substrate thickness exists (∼80 nm) which minimizes peak temperature, due to competing electrostatic and thermal effects.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994428
M. H. Lee, C. Kao, C. Yang, Y. Chen, H. Y. Lee, F. Chen, M. Tsai
Cross-point memory framework provides high capacity, low power consumption, and low cost in nonvolatile-memory (NVM) technology [1,2]. Resistive cross-point memory structure is one of the potential candidates with scaling down beyond the flash memory [3]. In order to increase density for cross-point architecture, the vertical diode is integrated for the controller (Fig. 1) without planar MOSFET or BJT. The metal oxide diode has been reported on the switching devices with high leakage current [4]. The p/n diode has higher ON-current and uni-polar operation for PCM (Phase Change Memory) [5,6], which is compatible with IC process. The characteristic of bipolar programming in RRAM makes the requirement of bi-directional turn-ON behavior for the switching driving device [7]. In this work, the poly-Si n/p/n diode with ambipolar operation for RRAM applications and the stress reliability for programming will be demonstrated.
{"title":"Reliability of ambipolar switching poly-Si diodes for cross-point memory applications","authors":"M. H. Lee, C. Kao, C. Yang, Y. Chen, H. Y. Lee, F. Chen, M. Tsai","doi":"10.1109/DRC.2011.5994428","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994428","url":null,"abstract":"Cross-point memory framework provides high capacity, low power consumption, and low cost in nonvolatile-memory (NVM) technology [1,2]. Resistive cross-point memory structure is one of the potential candidates with scaling down beyond the flash memory [3]. In order to increase density for cross-point architecture, the vertical diode is integrated for the controller (Fig. 1) without planar MOSFET or BJT. The metal oxide diode has been reported on the switching devices with high leakage current [4]. The p/n diode has higher ON-current and uni-polar operation for PCM (Phase Change Memory) [5,6], which is compatible with IC process. The characteristic of bipolar programming in RRAM makes the requirement of bi-directional turn-ON behavior for the switching driving device [7]. In this work, the poly-Si n/p/n diode with ambipolar operation for RRAM applications and the stress reliability for programming will be demonstrated.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121906207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994455
Ronghua Wang, Guowang Li, T. Fang, O. Laboutin, Yu Cao, W. Johnson, G. Snider, P. Fay, D. Jena, H. Xing
GaN-based high electron mobility transistors (HEMTs) have been developed for high-temperature, high-frequency and high-power applications. To improve the transistor speed, various techniques have been explored in addition to scaling down the gate length and top barrier thickness: ultrathin SiN passivation to reduce access resistance and parasitic capacitances [1]; re-grown ohmic contacts and self-alignment to minimize access resistances [2, 3]; O2 plasma treatment in the gate region prior to the metal deposition to suppress rf transconductance collapse [4]; and dielectric-free passivation (DFP) by a O2-containing plasma treatment in the access region to shorten the gate extension in InAlN HEMTs [5]. Here we report a comparative study on the impact of various plasma treatments in the access region (DFP) as well as under the gate for InAl(Ga)N barrier HEMTs, and propose a model for the observed fT improvement.
{"title":"Improvement of fT in InAl(Ga)N barrier HEMTs by plasma treatments","authors":"Ronghua Wang, Guowang Li, T. Fang, O. Laboutin, Yu Cao, W. Johnson, G. Snider, P. Fay, D. Jena, H. Xing","doi":"10.1109/DRC.2011.5994455","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994455","url":null,"abstract":"GaN-based high electron mobility transistors (HEMTs) have been developed for high-temperature, high-frequency and high-power applications. To improve the transistor speed, various techniques have been explored in addition to scaling down the gate length and top barrier thickness: ultrathin SiN passivation to reduce access resistance and parasitic capacitances [1]; re-grown ohmic contacts and self-alignment to minimize access resistances [2, 3]; O2 plasma treatment in the gate region prior to the metal deposition to suppress rf transconductance collapse [4]; and dielectric-free passivation (DFP) by a O2-containing plasma treatment in the access region to shorten the gate extension in InAlN HEMTs [5]. Here we report a comparative study on the impact of various plasma treatments in the access region (DFP) as well as under the gate for InAl(Ga)N barrier HEMTs, and propose a model for the observed fT improvement.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122894566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994433
A. Subramaniam, K. D. Cantley, R. Chapman, B. Chakrabarti, E. Vogel
Hydrogenated nano-crystalline-silicon (nc-Si) thin-film transistors (TFTs) are primary candidates for use in neuromorphic circuits and systems [1]. Such devices can be fabricated at low temperatures and over large areas, allowing cheap processing and three-dimensional integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (VT) shift under bias stress and lack of p-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer [2]. We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications.
{"title":"Ambipolar nano-crystalline-silicon TFTs with submicron dimensions and reduced threshold voltage shift","authors":"A. Subramaniam, K. D. Cantley, R. Chapman, B. Chakrabarti, E. Vogel","doi":"10.1109/DRC.2011.5994433","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994433","url":null,"abstract":"Hydrogenated nano-crystalline-silicon (nc-Si) thin-film transistors (TFTs) are primary candidates for use in neuromorphic circuits and systems [1]. Such devices can be fabricated at low temperatures and over large areas, allowing cheap processing and three-dimensional integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (VT) shift under bias stress and lack of p-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer [2]. We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125444266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994502
M. Wong, U. Singisetti, Jing Lu, J. Speck, U. Mishra
We propose that the anomalous output conductance in N-polar GaN MIS-HEMTs was caused by ionization of donor-like traps from a net negative polarization interface. It is a low-frequency phenomenon that changes the VT of the device with VD, while no evidence of increased output conductance or related device performance degradation was found under RF conditions. Appropriate back-barrier designs are needed to mitigate the DC-GDS in N-polar GaN MIS-HEMTs.
{"title":"Anomalous output conductance in N-polar GaN-based MIS-HEMTs","authors":"M. Wong, U. Singisetti, Jing Lu, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.5994502","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994502","url":null,"abstract":"We propose that the anomalous output conductance in N-polar GaN MIS-HEMTs was caused by ionization of donor-like traps from a net negative polarization interface. It is a low-frequency phenomenon that changes the VT of the device with VD, while no evidence of increased output conductance or related device performance degradation was found under RF conditions. Appropriate back-barrier designs are needed to mitigate the DC-GDS in N-polar GaN MIS-HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125046201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994480
J. Welser, K. Bernstein
Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. NRI seeks to find not just a one generation improvement on the FET, but rather a new extended scaling path. This is crucial to justify the expense of making any major change in the current technology infrastructure (both at the device and design level) - and the larger the change, the more benefit and longevity the new technology must offer.
{"title":"Challenges for post-CMOS devices & architectures","authors":"J. Welser, K. Bernstein","doi":"10.1109/DRC.2011.5994480","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994480","url":null,"abstract":"Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. NRI seeks to find not just a one generation improvement on the FET, but rather a new extended scaling path. This is crucial to justify the expense of making any major change in the current technology infrastructure (both at the device and design level) - and the larger the change, the more benefit and longevity the new technology must offer.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120951636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994507
S. L. Selvaraj, A. Watanabe, T. Egawa
Growth and optimization of AlGaN/GaN transistors on Si substrate is an important subject of investigation to surpass the cost effective substrates like GaN, SiC and sapphire. In the ongoing study of GaN devices on Si, we have achieved record high room temperature mobility (μRT) of 3215 cm2/Vs for AlGaN/GaN HEMTs grown by MOCVD. Our approach to increase the mobility involves (i) reducing dislocation density by using thick buffer on Si and (ii) using 1.5 nm AlN spacer. This is the highest μRT so far reported for AlGaN/GaN grown on GaN, SiC and sapphire substrates. The growth and device characteristics of these HEMTs which have high mobility are presented in this report.
{"title":"Enhanced mobility for MOCVD grown AlGaN/GaN HEMTs on Si substrate","authors":"S. L. Selvaraj, A. Watanabe, T. Egawa","doi":"10.1109/DRC.2011.5994507","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994507","url":null,"abstract":"Growth and optimization of AlGaN/GaN transistors on Si substrate is an important subject of investigation to surpass the cost effective substrates like GaN, SiC and sapphire. In the ongoing study of GaN devices on Si, we have achieved record high room temperature mobility (μRT) of 3215 cm2/Vs for AlGaN/GaN HEMTs grown by MOCVD. Our approach to increase the mobility involves (i) reducing dislocation density by using thick buffer on Si and (ii) using 1.5 nm AlN spacer. This is the highest μRT so far reported for AlGaN/GaN grown on GaN, SiC and sapphire substrates. The growth and device characteristics of these HEMTs which have high mobility are presented in this report.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126224770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994401
L. Liu, V. Saripalli, V. Narayanan, S. Datta
Compound semiconductors such as In0.7Ga0.3As and InSb are being actively researched as replacement for silicon channel materials for logic applications due to their superior transport properties [1,2]. Planar III–V quantum-well FETs have already demonstrated with superior performance than the state-of-the art Si MOSFETs for low supply voltage (Vcc) applications [1–3]. A key research challenge remains in addressing the scalability of III-V based quantum-well FETs to sub-14 nm node logic applications while still maintaining their excellent transport advantage. In this study, we demonstrate quasi-ballistic operation of non-planar, multi-gate, modulation doped, strained In0.7Ga0.3As quantum well FET (MuQFET), combining the electrostatic robustness of multi-gate configuration with the excellent electron mobility of high mobility quantum well channel, In0.7Ga0.3As (Figure 1).
{"title":"Experimental investigation of scalability and transport in In0.7Ga0.3As multi-gate quantum well FET (MuQFET)","authors":"L. Liu, V. Saripalli, V. Narayanan, S. Datta","doi":"10.1109/DRC.2011.5994401","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994401","url":null,"abstract":"Compound semiconductors such as In0.7Ga0.3As and InSb are being actively researched as replacement for silicon channel materials for logic applications due to their superior transport properties [1,2]. Planar III–V quantum-well FETs have already demonstrated with superior performance than the state-of-the art Si MOSFETs for low supply voltage (Vcc) applications [1–3]. A key research challenge remains in addressing the scalability of III-V based quantum-well FETs to sub-14 nm node logic applications while still maintaining their excellent transport advantage. In this study, we demonstrate quasi-ballistic operation of non-planar, multi-gate, modulation doped, strained In0.7Ga0.3As quantum well FET (MuQFET), combining the electrostatic robustness of multi-gate configuration with the excellent electron mobility of high mobility quantum well channel, In0.7Ga0.3As (Figure 1).","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122012768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994422
Pei Zhao, D. Jena, S. Koswatta
The modeled device structures are shown in Figure 1, (a) top-gated structure εox = 20 and tox = 1.5nm, and (b) back-gated structure with 90nm thick SiO2. The contact resistance and parasitic capacitance have also been taken into consideration in the simulations. Figure 2 shows the effect of M-G contacts on the transfer characteristics and transconductance, gm for the top-gated structure. The on-current, Ion, can be increased with strong M-G coupling strength Δ or heavy contact induced doping (i.e. larger ΔEcontact). The off-current, Ioff, does not increase. Large ΔEcontact increases gm, but the maximum gm does not show a strong dependence on Δ. We use Δ=50meV and ΔEcontac = −0.4eV for rest of the simulations. Figure 3 shows the IDS vs. VGS and gm vs. VGS at different VDS for the top-gated structure. Large VDS yields a higher maximum gm, but low VDS shows better linearity with a broader ƒT peak. Transfer characteristics with different channel lengths are shown in Figure 4. For the top-gated structure excellent gate electrostatics helps avoid short channel effects (SCE). Ion remains the same for all channel lengths. Ioff increases about 1.5 times when Lch decreases from 100nm to 15nm due to direct source to drain tunneling. The rise in Ioff leads to gm degradation at Lch=15nm. In the back-gated structure, the on/off ratio is degraded at shorter channel lengths, and the minimum conduction point shifts. Figure 5 shows the effect of contact resistance on ID - VGS characteristics at Lch = 100nm. At VDS = 0.3V, compared with the intrinsic case, when RS/D = 0.5Ωmm, on/off ratio decreases 3x for the top-gated structure and 1.2x for the back-gated structure. Ion reduces 22x for the top-gated structure and 6x for the back-gated structure. Figure 6 shows the comparison of ƒT -VGS with different channel lengths at VDS = 0.3V. The cutoff frequency is calculated as ƒT = 1/2πτtot, where τtot = LchCgs/gm + Cgd/gm + Cgd(RS+RD), Cgs = ∂Qch/∂VGS, RS/D = 0.5Ωmm, and Cgd = 2pF/cm and 0.5pF/cm for the top-gated and the back-gated structures, respectively. Charging/discharging process is faster at shorter channel lengths, thus the peak ƒT increases. In the back-gated structure, SCE is strong, thus the on/off ratio decreases and gm drops dramatically at short Lch. When Lch is shorter than 30nm, even the peak ƒT drops. Figure 7 summarizes the ƒT vs. Lc
{"title":"RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit","authors":"Pei Zhao, D. Jena, S. Koswatta","doi":"10.1109/DRC.2011.5994422","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994422","url":null,"abstract":"The modeled device structures are shown in Figure 1, (a) top-gated structure ε<inf>ox</inf> = 20 and t<inf>ox</inf> = 1.5nm, and (b) back-gated structure with 90nm thick SiO<inf>2</inf>. The contact resistance and parasitic capacitance have also been taken into consideration in the simulations. Figure 2 shows the effect of M-G contacts on the transfer characteristics and transconductance, g<inf>m</inf> for the top-gated structure. The on-current, I<inf>on</inf>, can be increased with strong M-G coupling strength Δ or heavy contact induced doping (i.e. larger ΔE<inf>contact</inf>). The off-current, I<inf>off</inf>, does not increase. Large ΔE<inf>contact</inf> increases g<inf>m</inf>, but the maximum g<inf>m</inf> does not show a strong dependence on Δ. We use Δ=50meV and ΔE<inf>contac</inf> = −0.4eV for rest of the simulations. Figure 3 shows the I<inf>DS</inf> vs. V<inf>GS</inf> and g<inf>m</inf> vs. V<inf>GS</inf> at different V<inf>DS</inf> for the top-gated structure. Large V<inf>DS</inf> yields a higher maximum g<inf>m</inf>, but low V<inf>DS</inf> shows better linearity with a broader ƒ<inf>T</inf> peak. Transfer characteristics with different channel lengths are shown in Figure 4. For the top-gated structure excellent gate electrostatics helps avoid short channel effects (SCE). I<inf>on</inf> remains the same for all channel lengths. I<inf>off</inf> increases about 1.5 times when L<inf>ch</inf> decreases from 100nm to 15nm due to direct source to drain tunneling. The rise in I<inf>off</inf> leads to g<inf>m</inf> degradation at L<inf>ch</inf>=15nm. In the back-gated structure, the on/off ratio is degraded at shorter channel lengths, and the minimum conduction point shifts. Figure 5 shows the effect of contact resistance on I<inf>D</inf> - V<inf>GS</inf> characteristics at L<inf>ch</inf> = 100nm. At V<inf>DS</inf> = 0.3V, compared with the intrinsic case, when R<inf>S/D</inf> = 0.5Ωmm, on/off ratio decreases 3x for the top-gated structure and 1.2x for the back-gated structure. I<inf>on</inf> reduces 22x for the top-gated structure and 6x for the back-gated structure. Figure 6 shows the comparison of ƒ<inf>T</inf> -V<inf>GS</inf> with different channel lengths at V<inf>DS</inf> = 0.3V. The cutoff frequency is calculated as ƒ<inf>T</inf> = 1/2πτ<inf>tot</inf>, where τ<inf>tot</inf> = L<inf>ch</inf>C<inf>gs</inf>/g<inf>m</inf> + C<inf>gd</inf>/g<inf>m</inf> + C<inf>gd</inf>(R<inf>S</inf>+R<inf>D</inf>), C<inf>gs</inf> = ∂Q<inf>ch</inf>/∂V<inf>GS</inf>, R<inf>S/D</inf> = 0.5Ωmm, and C<inf>gd</inf> = 2pF/cm and 0.5pF/cm for the top-gated and the back-gated structures, respectively. Charging/discharging process is faster at shorter channel lengths, thus the peak ƒ<inf>T</inf> increases. In the back-gated structure, SCE is strong, thus the on/off ratio decreases and g<inf>m</inf> drops dramatically at short L<inf>ch</inf>. When L<inf>ch</inf> is shorter than 30nm, even the peak ƒ<inf>T</inf> drops. Figure 7 summarizes the ƒ<inf>T</inf> vs. L<inf>c","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：