Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994433
A. Subramaniam, K. D. Cantley, R. Chapman, B. Chakrabarti, E. Vogel
Hydrogenated nano-crystalline-silicon (nc-Si) thin-film transistors (TFTs) are primary candidates for use in neuromorphic circuits and systems [1]. Such devices can be fabricated at low temperatures and over large areas, allowing cheap processing and three-dimensional integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (VT) shift under bias stress and lack of p-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer [2]. We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications.
{"title":"Ambipolar nano-crystalline-silicon TFTs with submicron dimensions and reduced threshold voltage shift","authors":"A. Subramaniam, K. D. Cantley, R. Chapman, B. Chakrabarti, E. Vogel","doi":"10.1109/DRC.2011.5994433","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994433","url":null,"abstract":"Hydrogenated nano-crystalline-silicon (nc-Si) thin-film transistors (TFTs) are primary candidates for use in neuromorphic circuits and systems [1]. Such devices can be fabricated at low temperatures and over large areas, allowing cheap processing and three-dimensional integration with CMOS structures. The major drawbacks of nc-Si TFTs include low carrier mobility, threshold voltage (VT) shift under bias stress and lack of p-channel operation due to unintentional n-type doping by oxygen impurity present in the nc-Si layer [2]. We have fabricated nc-Si TFTs that minimize all the above drawbacks, and are thus well suited for use in neuromorphic applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125444266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994412
S. Islam, M. Bae, V. Dorgan, E. Pop
Recent studies using infrared (IR) imaging of graphene transistors [1,2] have revealed substantial Joule heating under realistic operating conditions for graphene-on-insulator (GOI) devices. Here we use simulations calibrated against experimental data to examine the trends of performance degradation caused by self-heating as a function of insulator (SiO2) thickness. We also examine both unipolar and ambipolar operating conditions, and find that peak channel temperatures are proportional to oxide thickness for the unipolar case (as would be expected), but for ambipolar operation an optimum oxide substrate thickness exists (∼80 nm) which minimizes peak temperature, due to competing electrostatic and thermal effects.
{"title":"Effect of oxide thickness scaling on self-heating in graphene transistors","authors":"S. Islam, M. Bae, V. Dorgan, E. Pop","doi":"10.1109/DRC.2011.5994412","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994412","url":null,"abstract":"Recent studies using infrared (IR) imaging of graphene transistors [1,2] have revealed substantial Joule heating under realistic operating conditions for graphene-on-insulator (GOI) devices. Here we use simulations calibrated against experimental data to examine the trends of performance degradation caused by self-heating as a function of insulator (SiO2) thickness. We also examine both unipolar and ambipolar operating conditions, and find that peak channel temperatures are proportional to oxide thickness for the unipolar case (as would be expected), but for ambipolar operation an optimum oxide substrate thickness exists (∼80 nm) which minimizes peak temperature, due to competing electrostatic and thermal effects.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994502
M. Wong, U. Singisetti, Jing Lu, J. Speck, U. Mishra
We propose that the anomalous output conductance in N-polar GaN MIS-HEMTs was caused by ionization of donor-like traps from a net negative polarization interface. It is a low-frequency phenomenon that changes the VT of the device with VD, while no evidence of increased output conductance or related device performance degradation was found under RF conditions. Appropriate back-barrier designs are needed to mitigate the DC-GDS in N-polar GaN MIS-HEMTs.
{"title":"Anomalous output conductance in N-polar GaN-based MIS-HEMTs","authors":"M. Wong, U. Singisetti, Jing Lu, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.5994502","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994502","url":null,"abstract":"We propose that the anomalous output conductance in N-polar GaN MIS-HEMTs was caused by ionization of donor-like traps from a net negative polarization interface. It is a low-frequency phenomenon that changes the VT of the device with VD, while no evidence of increased output conductance or related device performance degradation was found under RF conditions. Appropriate back-barrier designs are needed to mitigate the DC-GDS in N-polar GaN MIS-HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125046201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994480
J. Welser, K. Bernstein
Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. NRI seeks to find not just a one generation improvement on the FET, but rather a new extended scaling path. This is crucial to justify the expense of making any major change in the current technology infrastructure (both at the device and design level) - and the larger the change, the more benefit and longevity the new technology must offer.
{"title":"Challenges for post-CMOS devices & architectures","authors":"J. Welser, K. Bernstein","doi":"10.1109/DRC.2011.5994480","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994480","url":null,"abstract":"Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. NRI seeks to find not just a one generation improvement on the FET, but rather a new extended scaling path. This is crucial to justify the expense of making any major change in the current technology infrastructure (both at the device and design level) - and the larger the change, the more benefit and longevity the new technology must offer.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120951636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994401
L. Liu, V. Saripalli, V. Narayanan, S. Datta
Compound semiconductors such as In0.7Ga0.3As and InSb are being actively researched as replacement for silicon channel materials for logic applications due to their superior transport properties [1,2]. Planar III–V quantum-well FETs have already demonstrated with superior performance than the state-of-the art Si MOSFETs for low supply voltage (Vcc) applications [1–3]. A key research challenge remains in addressing the scalability of III-V based quantum-well FETs to sub-14 nm node logic applications while still maintaining their excellent transport advantage. In this study, we demonstrate quasi-ballistic operation of non-planar, multi-gate, modulation doped, strained In0.7Ga0.3As quantum well FET (MuQFET), combining the electrostatic robustness of multi-gate configuration with the excellent electron mobility of high mobility quantum well channel, In0.7Ga0.3As (Figure 1).
{"title":"Experimental investigation of scalability and transport in In0.7Ga0.3As multi-gate quantum well FET (MuQFET)","authors":"L. Liu, V. Saripalli, V. Narayanan, S. Datta","doi":"10.1109/DRC.2011.5994401","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994401","url":null,"abstract":"Compound semiconductors such as In0.7Ga0.3As and InSb are being actively researched as replacement for silicon channel materials for logic applications due to their superior transport properties [1,2]. Planar III–V quantum-well FETs have already demonstrated with superior performance than the state-of-the art Si MOSFETs for low supply voltage (Vcc) applications [1–3]. A key research challenge remains in addressing the scalability of III-V based quantum-well FETs to sub-14 nm node logic applications while still maintaining their excellent transport advantage. In this study, we demonstrate quasi-ballistic operation of non-planar, multi-gate, modulation doped, strained In0.7Ga0.3As quantum well FET (MuQFET), combining the electrostatic robustness of multi-gate configuration with the excellent electron mobility of high mobility quantum well channel, In0.7Ga0.3As (Figure 1).","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122012768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994455
Ronghua Wang, Guowang Li, T. Fang, O. Laboutin, Yu Cao, W. Johnson, G. Snider, P. Fay, D. Jena, H. Xing
GaN-based high electron mobility transistors (HEMTs) have been developed for high-temperature, high-frequency and high-power applications. To improve the transistor speed, various techniques have been explored in addition to scaling down the gate length and top barrier thickness: ultrathin SiN passivation to reduce access resistance and parasitic capacitances [1]; re-grown ohmic contacts and self-alignment to minimize access resistances [2, 3]; O2 plasma treatment in the gate region prior to the metal deposition to suppress rf transconductance collapse [4]; and dielectric-free passivation (DFP) by a O2-containing plasma treatment in the access region to shorten the gate extension in InAlN HEMTs [5]. Here we report a comparative study on the impact of various plasma treatments in the access region (DFP) as well as under the gate for InAl(Ga)N barrier HEMTs, and propose a model for the observed fT improvement.
{"title":"Improvement of fT in InAl(Ga)N barrier HEMTs by plasma treatments","authors":"Ronghua Wang, Guowang Li, T. Fang, O. Laboutin, Yu Cao, W. Johnson, G. Snider, P. Fay, D. Jena, H. Xing","doi":"10.1109/DRC.2011.5994455","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994455","url":null,"abstract":"GaN-based high electron mobility transistors (HEMTs) have been developed for high-temperature, high-frequency and high-power applications. To improve the transistor speed, various techniques have been explored in addition to scaling down the gate length and top barrier thickness: ultrathin SiN passivation to reduce access resistance and parasitic capacitances [1]; re-grown ohmic contacts and self-alignment to minimize access resistances [2, 3]; O2 plasma treatment in the gate region prior to the metal deposition to suppress rf transconductance collapse [4]; and dielectric-free passivation (DFP) by a O2-containing plasma treatment in the access region to shorten the gate extension in InAlN HEMTs [5]. Here we report a comparative study on the impact of various plasma treatments in the access region (DFP) as well as under the gate for InAl(Ga)N barrier HEMTs, and propose a model for the observed fT improvement.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122894566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994500
M. H. Lee, C. Kao, C. Yang, C. Lee
The promising potential of tunneling FETs (TFETs) for steep switch behavior with gate controlled band-to-band tunneling (BTBT) mechanism has attracted much attention for supply voltage (VDD) scaling and power consumption next generation CMOS [1, 2]. However, the challenge for TFETs is lower drive currents as compare with MOSFET due to a high conductance resistance while reverse bias. Tunneling FETs (TFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current. In order to obtain high ION without sacrificing IOFF, and the high-k dielectric and metal gate are integrated as gate stack. To obtain high quality and avoid crystallizing of high-K layer, the gate last process was performed in this work. For N-TFET, much works have been reported on the SS improvement [4, 5]. For P-TFET, Bhuwalka et al. reported the ambipolar working of vertical TFET with negative gate bias, which obtain SS < 60mV/dec [6, 7]. In this work, we will demonstrate HK/MG (high-K/metal gate) P-TFET with the gate last process, and discuss the anisotropic effect on (110) substrate.
{"title":"P-type tunneling FET on Si (110) substrate with anisotropic effect","authors":"M. H. Lee, C. Kao, C. Yang, C. Lee","doi":"10.1109/DRC.2011.5994500","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994500","url":null,"abstract":"The promising potential of tunneling FETs (TFETs) for steep switch behavior with gate controlled band-to-band tunneling (BTBT) mechanism has attracted much attention for supply voltage (VDD) scaling and power consumption next generation CMOS [1, 2]. However, the challenge for TFETs is lower drive currents as compare with MOSFET due to a high conductance resistance while reverse bias. Tunneling FETs (TFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current. In order to obtain high ION without sacrificing IOFF, and the high-k dielectric and metal gate are integrated as gate stack. To obtain high quality and avoid crystallizing of high-K layer, the gate last process was performed in this work. For N-TFET, much works have been reported on the SS improvement [4, 5]. For P-TFET, Bhuwalka et al. reported the ambipolar working of vertical TFET with negative gate bias, which obtain SS < 60mV/dec [6, 7]. In this work, we will demonstrate HK/MG (high-K/metal gate) P-TFET with the gate last process, and discuss the anisotropic effect on (110) substrate.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116566972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994469
Jing Li, I. Appelbaum
Recent advances in the development of techniques for electrical injection and detection of spin-polarized electrons in silicon have aroused intensive research on exploiting devices and circuits that utilize the spin degree of freedom [1–3] as well as electron charge in this dominant material of the semiconductor integrated circuits industry.
{"title":"Simultaneous spin and charge transport in gated Si devices","authors":"Jing Li, I. Appelbaum","doi":"10.1109/DRC.2011.5994469","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994469","url":null,"abstract":"Recent advances in the development of techniques for electrical injection and detection of spin-polarized electrons in silicon have aroused intensive research on exploiting devices and circuits that utilize the spin degree of freedom [1–3] as well as electron charge in this dominant material of the semiconductor integrated circuits industry.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123155886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994471
D. Bhowmik, S. Salahuddin
To summarize, we proposed and simulated a nanomagnetic microwave oscillator that does not require any DC or r.f. magnetic field (unlike in conventional FMR), nor any spin torque current (unlike in STNO's). The frequency of oscillation can be effectively tuned by DC voltage in the microwave domain. The fact that magnetic fields and currents are not needed can make it a much cheaper, denser and less power hungry alternative for future electromagnetic oscillator applications.
{"title":"Proposal for piezoelectric-ferromagnet bilayer based microwave oscillators without any external magnetic field or spin transfer torque","authors":"D. Bhowmik, S. Salahuddin","doi":"10.1109/DRC.2011.5994471","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994471","url":null,"abstract":"To summarize, we proposed and simulated a nanomagnetic microwave oscillator that does not require any DC or r.f. magnetic field (unlike in conventional FMR), nor any spin torque current (unlike in STNO's). The frequency of oscillation can be effectively tuned by DC voltage in the microwave domain. The fact that magnetic fields and currents are not needed can make it a much cheaper, denser and less power hungry alternative for future electromagnetic oscillator applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124207386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994517
Chen-Guan Lee, Tanvi Joshi, K. Divakar, A. Dodabalapur
Amorphous oxide semiconductors (AOS) have been extensively studied for circuit applications, such as inverters [1], oscillators [2], and memory devices [3]. Most of the AOS-based TFTs used in the circuits are processed with high-vacuum systems even though solution-based processes have the advantages of easy processing, low fabrication cost and potential for large coverage area. In this paper, we demonstrate circuits based on solution-processed zinc-tin oxide (ZTO) TFTs, including inverters, ring oscillators and amplifiers. Performance uniformity and circuit functionality have been achieved with solution-based processing technique.
{"title":"Circuit applications based on solution-processed zinc-tin oxide TFTs","authors":"Chen-Guan Lee, Tanvi Joshi, K. Divakar, A. Dodabalapur","doi":"10.1109/DRC.2011.5994517","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994517","url":null,"abstract":"Amorphous oxide semiconductors (AOS) have been extensively studied for circuit applications, such as inverters [1], oscillators [2], and memory devices [3]. Most of the AOS-based TFTs used in the circuits are processed with high-vacuum systems even though solution-based processes have the advantages of easy processing, low fabrication cost and potential for large coverage area. In this paper, we demonstrate circuits based on solution-processed zinc-tin oxide (ZTO) TFTs, including inverters, ring oscillators and amplifiers. Performance uniformity and circuit functionality have been achieved with solution-based processing technique.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"106 16","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113946043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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