Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994403
A. Dey, C. Thelander, M. Borgstrom, B. Borg, E. Lind, L. Wernersson
InAs is an attractive channel material for III–V nanowire MOSFETs and early prototype high performance nanowire transistors have been demonstrated1. As the gate length is reduced, the nanowire diameter must be scaled quite aggressively in order to suppress short-channel effects2. However, a reduction in transconductance (gm) and drive current (ION) could be expected due to increased surface scattering for thin wires. We present data for the device properties of thin InAs nanowires, with diameters in the 15 nm range, and investigate possible improvements of the performance focusing on transistor applications. In order to boost ION, the source and drain resistance need to be reduced. Several doping sources were therefore evaluated in the study, among them selenium (Se), tin (Sn) and sulphur (S) to form n-i-n structures. We report very high current densities, up to 33 MA/cm2, comparable to modern HEMTs3, and a normalized transconductance of 1.8 S/mm for a nanowire with an intrinsic segment of nominally 150 nm and a diameter of 15 nm.
{"title":"15 nm diameter InAs nanowire MOSFETs","authors":"A. Dey, C. Thelander, M. Borgstrom, B. Borg, E. Lind, L. Wernersson","doi":"10.1109/DRC.2011.5994403","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994403","url":null,"abstract":"InAs is an attractive channel material for III–V nanowire MOSFETs and early prototype high performance nanowire transistors have been demonstrated1. As the gate length is reduced, the nanowire diameter must be scaled quite aggressively in order to suppress short-channel effects2. However, a reduction in transconductance (gm) and drive current (ION) could be expected due to increased surface scattering for thin wires. We present data for the device properties of thin InAs nanowires, with diameters in the 15 nm range, and investigate possible improvements of the performance focusing on transistor applications. In order to boost ION, the source and drain resistance need to be reduced. Several doping sources were therefore evaluated in the study, among them selenium (Se), tin (Sn) and sulphur (S) to form n-i-n structures. We report very high current densities, up to 33 MA/cm2, comparable to modern HEMTs3, and a normalized transconductance of 1.8 S/mm for a nanowire with an intrinsic segment of nominally 150 nm and a diameter of 15 nm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116376267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994524
J. Parker, P. Binetti, Y. Hung, E. Norberg, L. Coldren
We have demonstrated the first integrated ring mode-locked laser (MLL) with a reactive ion etch (RIE) lag coupler. The RIE lag directional coupler (RL-DC) is highly advantageous for integrated MLLs as it has an insertion loss <1 dB and can be designed to provide any coupling value. This provides the RL-DC with a much needed flexibility in large photonic systems unlike standard multimode interference (MMI) couplers, which typically provide only 3 dB power splitting.
{"title":"RIE lag directional coupler based integrated InGaAsP/InP ring mode-locked laser","authors":"J. Parker, P. Binetti, Y. Hung, E. Norberg, L. Coldren","doi":"10.1109/DRC.2011.5994524","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994524","url":null,"abstract":"We have demonstrated the first integrated ring mode-locked laser (MLL) with a reactive ion etch (RIE) lag coupler. The RIE lag directional coupler (RL-DC) is highly advantageous for integrated MLLs as it has an insertion loss <1 dB and can be designed to provide any coupling value. This provides the RL-DC with a much needed flexibility in large photonic systems unlike standard multimode interference (MMI) couplers, which typically provide only 3 dB power splitting.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125720929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994432
Donghyun Kim, Yongtaek Hong
Due to the handiness in obtaining a short channel length, vertical organic field-effect transistors (VOFETs) have been pointed as an alternative form of conventional organic thin-film transistor (OTFT). With VOFET structure, it is relatively simple to obtain an short channel length and a large channel width-to-length ratio (W/L) value in a restricted device area, so a large current driving capability which can hardly be achieved with organic semiconductor, can be realized. Moreover, VOFETs can be utilized as a platform for many kinds of electrical applications associated with other various functional devices such as organic light-emitting diodes (OLEDs) and sensors.
{"title":"Vertical organic field-effect transistor array fabrication based on laser holography lithography process","authors":"Donghyun Kim, Yongtaek Hong","doi":"10.1109/DRC.2011.5994432","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994432","url":null,"abstract":"Due to the handiness in obtaining a short channel length, vertical organic field-effect transistors (VOFETs) have been pointed as an alternative form of conventional organic thin-film transistor (OTFT). With VOFET structure, it is relatively simple to obtain an short channel length and a large channel width-to-length ratio (W/L) value in a restricted device area, so a large current driving capability which can hardly be achieved with organic semiconductor, can be realized. Moreover, VOFETs can be utilized as a platform for many kinds of electrical applications associated with other various functional devices such as organic light-emitting diodes (OLEDs) and sensors.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128047900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994400
R. Kapadia, K. Takei, A. C. Ford, Hui Fang, S. Chuang, M. Madsen, S. Krishna, A. Javey
Due to their high electron mobility, III–V semiconductors are promising channel materials for future devices [1]. InAs is one such promising material; however, due to the small bandgap (Eg∼0.36 eV) bulk devices are not feasible. In addition, heteroepitaxial growth of thin layers on Si is challenging due to the inherent lattice mismatch. Here, we present a platform developed for integration of single-crystalline ultra-thin compound semiconductor layers on insulator (XOI)[2], resembling the conventional SOI substrates.
{"title":"Ultra-thin compound semiconductor on insulator (XOI) for MOSFETs and TFETs","authors":"R. Kapadia, K. Takei, A. C. Ford, Hui Fang, S. Chuang, M. Madsen, S. Krishna, A. Javey","doi":"10.1109/DRC.2011.5994400","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994400","url":null,"abstract":"Due to their high electron mobility, III–V semiconductors are promising channel materials for future devices [1]. InAs is one such promising material; however, due to the small bandgap (Eg∼0.36 eV) bulk devices are not feasible. In addition, heteroepitaxial growth of thin layers on Si is challenging due to the inherent lattice mismatch. Here, we present a platform developed for integration of single-crystalline ultra-thin compound semiconductor layers on insulator (XOI)[2], resembling the conventional SOI substrates.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126978325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994443
H. Madan, D. Veksler, Y.T. Chen, J. Huang, N. Goel, G. Bersuker, S. Datta
By combining the capacitance and conductance analysis techniques, we obtained the Dit distribution throughout the band gap of In0.53Ga0.47As capacitors with H2O-based and O3-based ALD oxides. The choice of appropriate temperature to obtain the quasi-static C-V and the DC voltage sweep rate is an essential for the correct extraction of Dit. Simultaneously we obtained the trap kinetics characteristics. We claim that: (i) the H2O-based ALD deposition results in a fewer traps in the lower portion of In0.53Ga0.47As band gap, (ii) is related to the formation of the thicker native oxide in the O3-based samples; (iii) the mid gap traps in the H2O-based samples are significantly slower than those in the O3-based samples, which indicate their different nature.
{"title":"Interface states at high- к /InGaAs interface: H2O vs. O3 based ALD dielectric","authors":"H. Madan, D. Veksler, Y.T. Chen, J. Huang, N. Goel, G. Bersuker, S. Datta","doi":"10.1109/DRC.2011.5994443","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994443","url":null,"abstract":"By combining the capacitance and conductance analysis techniques, we obtained the D<inf>it</inf> distribution throughout the band gap of In<inf>0.53</inf>Ga<inf>0.47</inf>As capacitors with H<inf>2</inf>O-based and O<inf>3</inf>-based ALD oxides. The choice of appropriate temperature to obtain the quasi-static C-V and the DC voltage sweep rate is an essential for the correct extraction of D<inf>it</inf>. Simultaneously we obtained the trap kinetics characteristics. We claim that: (i) the H<inf>2</inf>O-based ALD deposition results in a fewer traps in the lower portion of In<inf>0.53</inf>Ga<inf>0.47</inf>As band gap, (ii) is related to the formation of the thicker native oxide in the O<inf>3</inf>-based samples; (iii) the mid gap traps in the H<inf>2</inf>O-based samples are significantly slower than those in the O<inf>3</inf>-based samples, which indicate their different nature.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124905382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994508
R. Chu, D. Zehnder, B. Hughes, K. Boutros
Field-effect transistors based on the low-cost GaN-on-Si platform are promising candidates for highefficiency power switching at high frequencies. We have reported a normally-off GaN-on-Si switch with a blocking voltage of 1200V, and a very low dynamic on-resistance [1]. For future improvement of the GaN-on-Si switching technology, it is important to understand the role of the non-insulating Si-substrate in device characteristics. In this paper, we discuss the static (DC) and dynamic (switching) characteristics of the GaN-on-Si device, focusing on the impact of bias conditions applied on the Si substrate. It was found that state-of-the-art dynamic on-resistance characteristics of the GaN-on-Si switch can be achieved by properly terminating the Si substrate potential.
{"title":"High performance GaN-on-Si power switch: Role of substrate bias in device characteristics","authors":"R. Chu, D. Zehnder, B. Hughes, K. Boutros","doi":"10.1109/DRC.2011.5994508","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994508","url":null,"abstract":"Field-effect transistors based on the low-cost GaN-on-Si platform are promising candidates for highefficiency power switching at high frequencies. We have reported a normally-off GaN-on-Si switch with a blocking voltage of 1200V, and a very low dynamic on-resistance [1]. For future improvement of the GaN-on-Si switching technology, it is important to understand the role of the non-insulating Si-substrate in device characteristics. In this paper, we discuss the static (DC) and dynamic (switching) characteristics of the GaN-on-Si device, focusing on the impact of bias conditions applied on the Si substrate. It was found that state-of-the-art dynamic on-resistance characteristics of the GaN-on-Si switch can be achieved by properly terminating the Si substrate potential.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994434
J. Shin, K. Kim, Hefei Hu, Ki Jun Yu, J. Rogers, J. Zuo, Xiuling Li
Heteroepitaxial integration of III–V and Si has been researched for many years since the Si is the prevalent platform and III–V can be used for light emitting source (i.e., direct bandgap) [1]. Although vertical InAs nanowires (NWs) growth on Si substrate (11.6% lattice mismatch) without catalysts and patterning has been demonstrated by several groups, [2, 3], direct heteroexpitaxial growth of ternary InxGa1−xAs nanowires hasn't been systematically studied yet, in spite of its important spectral coverage in the near infrared range. In this paper, we report the one-dimensional heteroepitaxial growth of dislocation free InxGa1−xAs nanowires on silicon (111) substrate in the entire composition range and demonstrate monolithically grown axial p-n junction tandem solar cells consisting of InxGa1−xAs NWs on Si with an efficiency that well exceeds the planar Si single junction solar cell fabricated using identical process.
{"title":"Monolithically grown InxGa1−xAs nanowire on silicon tandem solar cells with high efficiency","authors":"J. Shin, K. Kim, Hefei Hu, Ki Jun Yu, J. Rogers, J. Zuo, Xiuling Li","doi":"10.1109/DRC.2011.5994434","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994434","url":null,"abstract":"Heteroepitaxial integration of III–V and Si has been researched for many years since the Si is the prevalent platform and III–V can be used for light emitting source (i.e., direct bandgap) [1]. Although vertical InAs nanowires (NWs) growth on Si substrate (11.6% lattice mismatch) without catalysts and patterning has been demonstrated by several groups, [2, 3], direct heteroexpitaxial growth of ternary InxGa1−xAs nanowires hasn't been systematically studied yet, in spite of its important spectral coverage in the near infrared range. In this paper, we report the one-dimensional heteroepitaxial growth of dislocation free InxGa1−xAs nanowires on silicon (111) substrate in the entire composition range and demonstrate monolithically grown axial p-n junction tandem solar cells consisting of InxGa1−xAs NWs on Si with an efficiency that well exceeds the planar Si single junction solar cell fabricated using identical process.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994454
D. Moran, O. Fox, H. McLelland, S. Russell, P. May
The hydrogen-terminated diamond surface has demonstrated unique potential in the development of high power and high frequency field effect transistors (FETs) [1]. Further exploration into the intrinsic performance limitations and device operation as gate length is reduced however is essential in unveiling the potential of this exotic material system as a viable and competitive high power and high frequency device technology.
{"title":"Intrinsic DC operation and performance potential of 50nm gate length hydrogen-terminated diamond field effect transistors","authors":"D. Moran, O. Fox, H. McLelland, S. Russell, P. May","doi":"10.1109/DRC.2011.5994454","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994454","url":null,"abstract":"The hydrogen-terminated diamond surface has demonstrated unique potential in the development of high power and high frequency field effect transistors (FETs) [1]. Further exploration into the intrinsic performance limitations and device operation as gate length is reduced however is essential in unveiling the potential of this exotic material system as a viable and competitive high power and high frequency device technology.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123287715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.6086642
Uttam Singisett, M. Wong, J. Speck, U. Mishra
N-polar GaN field-effect-transistors (FETs) have the potential advantage in scaling to sub-50nm gate lengths because of the confinement provided by the wide bandgap back-barrier. High-performance enhancement-mode (E-mode) N-polar GaN devices with self-aligned source/drain have recently been demonstrated with a current gain cut-off frequency (ft) of 120 GHz at a gate length of 70 nm [1]. Further scaling of the gate length to sub-50nm dimensions would require vertical scaling of the GaN channel thickness to 5 nm and the incorporation of a high-k gate dielectric in order to maintain a high aspect ratio, and a positive threshold voltage. The proximity of the surface to the 2-DEG in the ultra-scaled channels lead to surface depletion, and reduced mobility which increase the parasitic access resistance. This problem becomes critical in the E-mode devices because of the lower modulation doping compared to D-mode devices. We report here a self-aligned N-polar GaN FET with a 5-nm GaN channel and atomic later deposited (ALD) Al2O3 gate dielectric with a peak Id of 1.2 A/mm and peak gm of 560 mS/mm. The Ron of 0.76 Ω-mm for this device is the lowest reported for E-mode GaN FETs [ 2, 3, 4].
n极氮化镓场效应晶体管(fet)具有潜在的优势，在缩放到50nm栅极长度以下，因为宽带隙背势垒提供了限制。高性能增强模式(E-mode) n极GaN器件具有自校准源/漏极，其电流增益截止频率(ft)为120 GHz，栅极长度为70 nm[1]。栅极长度进一步缩放到50nm以下的尺寸需要将GaN通道厚度垂直缩放到5nm，并结合高k栅极电介质，以保持高宽高比和正阈值电压。在超尺度通道中，表面接近2-DEG会导致表面耗竭，并降低迁移率，从而增加寄生访问阻力。这个问题在e模器件中变得至关重要，因为与d模器件相比，e模器件的调制掺杂更低。我们在这里报道了一个具有5纳米GaN通道和原子后期沉积(ALD) Al2O3栅极电介质的自定向n极GaN场效应管，其峰值Id为1.2 a /mm，峰值gm为560 mS/mm。该器件的Ron值为0.76 Ω-mm，是E-mode GaN fet中最低的[2,3,4]。
{"title":"Vertically scaled 5 nm GaN channel enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm gm and 0.76 Ω-mm Ron","authors":"Uttam Singisett, M. Wong, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.6086642","DOIUrl":"https://doi.org/10.1109/DRC.2011.6086642","url":null,"abstract":"N-polar GaN field-effect-transistors (FETs) have the potential advantage in scaling to sub-50nm gate lengths because of the confinement provided by the wide bandgap back-barrier. High-performance enhancement-mode (E-mode) N-polar GaN devices with self-aligned source/drain have recently been demonstrated with a current gain cut-off frequency (ft) of 120 GHz at a gate length of 70 nm [1]. Further scaling of the gate length to sub-50nm dimensions would require vertical scaling of the GaN channel thickness to 5 nm and the incorporation of a high-k gate dielectric in order to maintain a high aspect ratio, and a positive threshold voltage. The proximity of the surface to the 2-DEG in the ultra-scaled channels lead to surface depletion, and reduced mobility which increase the parasitic access resistance. This problem becomes critical in the E-mode devices because of the lower modulation doping compared to D-mode devices. We report here a self-aligned N-polar GaN FET with a 5-nm GaN channel and atomic later deposited (ALD) Al2O3 gate dielectric with a peak Id of 1.2 A/mm and peak gm of 560 mS/mm. The Ron of 0.76 Ω-mm for this device is the lowest reported for E-mode GaN FETs [ 2, 3, 4].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994457
Z. Yuan, A. Nainani, J. Lin, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat
III–V semiconductors are considered as promising candidates to replace silicon as the channel material in future technology nodes for transistors [1]. III–V n-channel MOSFETs have been extensively studied [2–4], showing high electron mobility. However, one of the most critical challenges in realizing high performance III–V MOSFETs is the difficulties in source/drain (S/D) design including parasitic resistance due to low solubility and poor activation of dopant and the “source starvation” effect due to low density of states [5–6]. Annealing of implant damage after S/D ion-implantation is also more problematic in III–V's due to the presence of 2 or more atomic species vs. group IV semiconductors (Fig.1). Use of Schottky-barrier (SB) metal S/D is a promising strategy to overcome these limitations [7]. Meanwhile, for III–V based CMOS logic, achieving a high mobility pMOSFET in a III–V channel remains a challenge. Antimony (Sb) based compound semiconductors have the highest electron and hole mobilities amongst all III–V materials. Recently, high performance strained channel InGaSb pMOSFETs [8] have been demonstrated. In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an InxGa1−xSb channel for good hole transport with metal S/D for low access resistance.
{"title":"Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs","authors":"Z. Yuan, A. Nainani, J. Lin, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat","doi":"10.1109/DRC.2011.5994457","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994457","url":null,"abstract":"III–V semiconductors are considered as promising candidates to replace silicon as the channel material in future technology nodes for transistors [1]. III–V n-channel MOSFETs have been extensively studied [2–4], showing high electron mobility. However, one of the most critical challenges in realizing high performance III–V MOSFETs is the difficulties in source/drain (S/D) design including parasitic resistance due to low solubility and poor activation of dopant and the “source starvation” effect due to low density of states [5–6]. Annealing of implant damage after S/D ion-implantation is also more problematic in III–V's due to the presence of 2 or more atomic species vs. group IV semiconductors (Fig.1). Use of Schottky-barrier (SB) metal S/D is a promising strategy to overcome these limitations [7]. Meanwhile, for III–V based CMOS logic, achieving a high mobility pMOSFET in a III–V channel remains a challenge. Antimony (Sb) based compound semiconductors have the highest electron and hole mobilities amongst all III–V materials. Recently, high performance strained channel InGaSb pMOSFETs [8] have been demonstrated. In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an InxGa1−xSb channel for good hole transport with metal S/D for low access resistance.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132866994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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