Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994438
A. Sattu, D. Billingsley, J. Deng, J. Yang, R. Gaska, M. Shur, G. Simin
We report on the first AlInN/GaN Heterojunction Field Effect Transistor (HFET) based Monolithic Microwave Integrated Circuit (MMIC) switch. Lattice-matched AlInN/GaN heterostructures with indium contents of ∼17% exhibit a very large conduction band discontinuity, ΔEC, of 1.7 eV. This large discontinuity results in 2DEG densities as high as 4.7×1013 cm−2 [1] and electron mobilities as high as 1617 cm2/V-s [2]. As a result these heterostructures can achieve record low sheet resistances, making them very attractive candidates for ultra-low loss microwave and other switching devices.
{"title":"Low loss AlInN/GaN Monolithic Microwave Integrated Circuit switch","authors":"A. Sattu, D. Billingsley, J. Deng, J. Yang, R. Gaska, M. Shur, G. Simin","doi":"10.1109/DRC.2011.5994438","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994438","url":null,"abstract":"We report on the first AlInN/GaN Heterojunction Field Effect Transistor (HFET) based Monolithic Microwave Integrated Circuit (MMIC) switch. Lattice-matched AlInN/GaN heterostructures with indium contents of ∼17% exhibit a very large conduction band discontinuity, ΔE<inf>C</inf>, of 1.7 eV. This large discontinuity results in 2DEG densities as high as 4.7×10<sup>13</sup> cm<sup>−2</sup> [1] and electron mobilities as high as 1617 cm<sup>2</sup>/V-s [2]. As a result these heterostructures can achieve record low sheet resistances, making them very attractive candidates for ultra-low loss microwave and other switching devices.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994472
D. Bedau, D. Backes, H. Liu, J. Langer, P. Manandhar, A. Kent
Spin-Transfer Magnetic Random Access Memory (ST-MRAM) devices hold great promise as a universal memory [Katine 2008]. ST-MRAM is non-volatile, has a small cell size, high endurance and may match the speed of SRAM. A disadvantage of the common collinearly magnetized ST-MRAM is their non-deterministic switching process, which leads to long switching times and broad switching time distributions [Devolder 2008, Koch 2004]. This delay is due to the fact that the torque is zero if the layers are either parallel or antiparallel [Slonczewski 1996] and hence switching cannot be initiated by the torque alone. Typically the process is started by an initial misalignment of the free layer stemming from thermal excitations. Relying on thermal initiation leads to incoherent reversal with an unpredictable incubation delay in the ns range [Devolder 2008] and broad switching time distributions [Koch 2004]
{"title":"Orthogonal spin transfer MRAM","authors":"D. Bedau, D. Backes, H. Liu, J. Langer, P. Manandhar, A. Kent","doi":"10.1109/DRC.2011.5994472","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994472","url":null,"abstract":"Spin-Transfer Magnetic Random Access Memory (ST-MRAM) devices hold great promise as a universal memory [Katine 2008]. ST-MRAM is non-volatile, has a small cell size, high endurance and may match the speed of SRAM. A disadvantage of the common collinearly magnetized ST-MRAM is their non-deterministic switching process, which leads to long switching times and broad switching time distributions [Devolder 2008, Koch 2004]. This delay is due to the fact that the torque is zero if the layers are either parallel or antiparallel [Slonczewski 1996] and hence switching cannot be initiated by the torque alone. Typically the process is started by an initial misalignment of the free layer stemming from thermal excitations. Relying on thermal initiation leads to incoherent reversal with an unpredictable incubation delay in the ns range [Devolder 2008] and broad switching time distributions [Koch 2004]","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128876954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994449
U. Zschieschang, N. H. Hansen, J. Pflaum, Tatsuya Yamamoto, K. Takimiya, H. Kuwabara, M. Ikeda, T. Sekitani, T. Someya, H. Klauk
Due to its large-area capability and high resolution, photolithography is the preferred patterning method for pentacene thin-film transistors (TFTs) for display and circuit applications [1,2]. Since the morphology of thin pentacene films is very sensitive to solvents and heat [3,4], the photolithographic patterning of the source/drain contacts is ideally performed prior to the pentacene deposition, which explains the general preference for the bottom-contact (coplanar) TFT structure. However, as experiments [5] and simulations [6,7] have shown, the bottom-contact TFT structure is associated with substantially larger contact resistance than the top-contact (staggered) structure, which means that for the same channel length, top-contact TFTs are expected to provide larger transconductance and higher cutoff frequency than bottom-contact TFTs. Here we report on organic TFTs with Au top contacts patterned by ordinary photolithography and wet etching (using common solvents, photoresists, and etchants) having field-effect mobilities (0.4 cm2/Vs) and on/off current ratios (107) similar to those of optimized bottom-contact pentacene TFTs [1,2,5].
{"title":"High-mobility organic thin-film transistors with photolithographically patterned top contacts","authors":"U. Zschieschang, N. H. Hansen, J. Pflaum, Tatsuya Yamamoto, K. Takimiya, H. Kuwabara, M. Ikeda, T. Sekitani, T. Someya, H. Klauk","doi":"10.1109/DRC.2011.5994449","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994449","url":null,"abstract":"Due to its large-area capability and high resolution, photolithography is the preferred patterning method for pentacene thin-film transistors (TFTs) for display and circuit applications [1,2]. Since the morphology of thin pentacene films is very sensitive to solvents and heat [3,4], the photolithographic patterning of the source/drain contacts is ideally performed prior to the pentacene deposition, which explains the general preference for the bottom-contact (coplanar) TFT structure. However, as experiments [5] and simulations [6,7] have shown, the bottom-contact TFT structure is associated with substantially larger contact resistance than the top-contact (staggered) structure, which means that for the same channel length, top-contact TFTs are expected to provide larger transconductance and higher cutoff frequency than bottom-contact TFTs. Here we report on organic TFTs with Au top contacts patterned by ordinary photolithography and wet etching (using common solvents, photoresists, and etchants) having field-effect mobilities (0.4 cm2/Vs) and on/off current ratios (107) similar to those of optimized bottom-contact pentacene TFTs [1,2,5].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120953163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994516
B. Bayraktaroglu, K. Leedy, R. Scott
Wide bandgap semiconductors based on (Zn, In, Ga, Sn)-oxides are all good candidates for the channel material in transparent thin film transistors (TTFT) because of their simultaneous high electron mobility and optical transparency properties. The choice of contact layers are, however, more limited because not all metal oxides can be doped high enough to yield low resistivity layers. Historically, the most common contact layers are ternary compounds that include indium (e.g. indium-tin-oxide, indium-zinc-oxide etc). These indium-containing transparent conductive oxide (TCO) films find widespread applications in flat panel displays and touch-sensitive surfaces of many communication devices. Because of the rapidly expanding markets for such devices, and the limited availability of indium in the world markets, the increased demand-to-supply ratio has caused the cost of indium to increase very rapidly. There are concerns about the continuity of indium supply for future devices.1
基于(Zn, In, Ga, Sn)氧化物的宽带隙半导体由于其同时具有高电子迁移率和光学透明性，都是透明薄膜晶体管(TTFT)通道材料的良好候选者。然而，接触层的选择是有限的，因为并不是所有的金属氧化物都能掺杂到足够高的水平以产生低电阻率层。历史上，最常见的接触层是包含铟的三元化合物(如氧化铟锡、氧化铟锌等)。这些含铟的透明导电氧化物(TCO)薄膜广泛应用于平板显示器和许多通信设备的触摸敏感表面。由于这种设备的市场迅速扩大，而铟在世界市场上的可用性有限，需求与供应比的增加导致铟的成本迅速增加。人们担心未来设备的铟供应能否持续
{"title":"Indium-free transparent thin film transistors based on nanocrystalline ZnO","authors":"B. Bayraktaroglu, K. Leedy, R. Scott","doi":"10.1109/DRC.2011.5994516","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994516","url":null,"abstract":"Wide bandgap semiconductors based on (Zn, In, Ga, Sn)-oxides are all good candidates for the channel material in transparent thin film transistors (TTFT) because of their simultaneous high electron mobility and optical transparency properties. The choice of contact layers are, however, more limited because not all metal oxides can be doped high enough to yield low resistivity layers. Historically, the most common contact layers are ternary compounds that include indium (e.g. indium-tin-oxide, indium-zinc-oxide etc). These indium-containing transparent conductive oxide (TCO) films find widespread applications in flat panel displays and touch-sensitive surfaces of many communication devices. Because of the rapidly expanding markets for such devices, and the limited availability of indium in the world markets, the increased demand-to-supply ratio has caused the cost of indium to increase very rapidly. There are concerns about the continuity of indium supply for future devices.1","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132444280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994430
Chen Wang, Min Xu, R. Colby, E. Stach, P. Ye
InP is a commonly used compound semiconductor with wide applications in electronic, optoelectronic, and photonic devices. Compared to GaAs, InP is widely believed to be a more forgiving material with respect to Fermi level pinning and has a higher electron saturation velocity (2.5×107 cm/s) as well. It could be a viable channel material for high-speed logic applications if a high-quality, thermodynamically stable high-k dielectric could be found. [1] It is of great importance for the understanding of high-k/InP interfaces since InP is identified as a transition layer for ALD high-k/InGaAs quantum well transistor in state-of-the-art devices. [2] Motivated by previous work on surface orientation studies of GaAs [3] and InGaAs [4], we have systematically studied NMOSFETs, MOSCAPs, and interfacial chemistry on two different crystalline surfaces: InP (100) and (111)A (In-rich). With ALD Al2O3 in direct contact as gate dielectric, a record high drain current of 600 µA/µm is obtained for an InP inversion-mode MOSFET on the (111)A surface with a gate length of 1µm, which is a factor of 2.6 enhancement compared to the (100) surface at the same VG-VT condition. The smoother Al2O3/(111)A interface and a shift of the charge-neutrality-level (CNL) [5] on InP(111)A toward the conduction band edge is identified as the origin of this drain current enhancement in spite of the extracted interface trap density (Dit). [6] In this paper, we report on “zero” drain-current drift on InP (111)A MOSFETs which is a major issue to prevent commercializing InP MOSFET technology on (100) surface in 1980s. [7]
{"title":"“Zero” drain-current drift of inversion-mode NMOSFET on InP (111)A surface","authors":"Chen Wang, Min Xu, R. Colby, E. Stach, P. Ye","doi":"10.1109/DRC.2011.5994430","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994430","url":null,"abstract":"InP is a commonly used compound semiconductor with wide applications in electronic, optoelectronic, and photonic devices. Compared to GaAs, InP is widely believed to be a more forgiving material with respect to Fermi level pinning and has a higher electron saturation velocity (2.5×107 cm/s) as well. It could be a viable channel material for high-speed logic applications if a high-quality, thermodynamically stable high-k dielectric could be found. [1] It is of great importance for the understanding of high-k/InP interfaces since InP is identified as a transition layer for ALD high-k/InGaAs quantum well transistor in state-of-the-art devices. [2] Motivated by previous work on surface orientation studies of GaAs [3] and InGaAs [4], we have systematically studied NMOSFETs, MOSCAPs, and interfacial chemistry on two different crystalline surfaces: InP (100) and (111)A (In-rich). With ALD Al2O3 in direct contact as gate dielectric, a record high drain current of 600 µA/µm is obtained for an InP inversion-mode MOSFET on the (111)A surface with a gate length of 1µm, which is a factor of 2.6 enhancement compared to the (100) surface at the same VG-VT condition. The smoother Al2O3/(111)A interface and a shift of the charge-neutrality-level (CNL) [5] on InP(111)A toward the conduction band edge is identified as the origin of this drain current enhancement in spite of the extracted interface trap density (Dit). [6] In this paper, we report on “zero” drain-current drift on InP (111)A MOSFETs which is a major issue to prevent commercializing InP MOSFET technology on (100) surface in 1980s. [7]","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129360469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994423
Yi Song, Huajie Zhou, Qiuxia Xu, Jun Luo, Chao Zhao, Q. Liang
We demonstrate high performance silicon nanowire gate-all-around MOSFETs (SNWFETs) fabricated on bulk Si by a novel top-down CMOS-compatible method. The fabricated N- and P-type SNWFETs of sub-50 nm gate length and of ∼5 nm in diameter show excellent short channel effects (SCEs) immunity with subthreshold slope (SS) of 90/69 mV/dec, DIBL of 47/10 mV/V, and high driving current of 2×103/5.4×103 µA/µm at 0.1 nA/µm off-current.
{"title":"High performance N- and P-type gate-all-around nanowire MOSFETs fabricated on bulk Si by CMOS-compatible process","authors":"Yi Song, Huajie Zhou, Qiuxia Xu, Jun Luo, Chao Zhao, Q. Liang","doi":"10.1109/DRC.2011.5994423","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994423","url":null,"abstract":"We demonstrate high performance silicon nanowire gate-all-around MOSFETs (SNWFETs) fabricated on bulk Si by a novel top-down CMOS-compatible method. The fabricated N- and P-type SNWFETs of sub-50 nm gate length and of ∼5 nm in diameter show excellent short channel effects (SCEs) immunity with subthreshold slope (SS) of 90/69 mV/dec, DIBL of 47/10 mV/V, and high driving current of 2×10<sup>3</sup>/5.4×10<sup>3</sup> µA/µm at 0.1 nA/µm off-current.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994444
P. Mensch, K. Moselund, S. Karg, E. Lortscher, M. Bjork, H. Schmid, H. Riel
The density of interface states, Dit, is important for the device performance in view of the fact that it limits the inverse subthreshold slope in both, MOSFETs and TFETs [1]. This poses particular challenges for nanowire (NW) devices, because the measured Dit is expected to increase due to the extensive processing and the various crystallographic orientations of the surface, which differ from the ideal (100) orientation. For a detailed investigation of the Dit of NWs it is best to analyze single NW MOS capacitors. However, the capacitance of a single NW MOS capacitor lies in the fF regime which is very challenging to measure. To date, very few capacitance measurements on single NWs have been reported, e.g., on lateral devices based on InAs [2], Ge [3], and Si [4]. Dit analysis of NWs has been demonstrated, however, based on capacitance measurements only of large arrays of InAs NWs [5]. In the present work, we report on the capacitance measurement and Dit analysis of vertical silicon MOS capacitors based on single NWs.
{"title":"C-V measurements of single vertical nanowire capacitors","authors":"P. Mensch, K. Moselund, S. Karg, E. Lortscher, M. Bjork, H. Schmid, H. Riel","doi":"10.1109/DRC.2011.5994444","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994444","url":null,"abstract":"The density of interface states, Dit, is important for the device performance in view of the fact that it limits the inverse subthreshold slope in both, MOSFETs and TFETs [1]. This poses particular challenges for nanowire (NW) devices, because the measured Dit is expected to increase due to the extensive processing and the various crystallographic orientations of the surface, which differ from the ideal (100) orientation. For a detailed investigation of the Dit of NWs it is best to analyze single NW MOS capacitors. However, the capacitance of a single NW MOS capacitor lies in the fF regime which is very challenging to measure. To date, very few capacitance measurements on single NWs have been reported, e.g., on lateral devices based on InAs [2], Ge [3], and Si [4]. Dit analysis of NWs has been demonstrated, however, based on capacitance measurements only of large arrays of InAs NWs [5]. In the present work, we report on the capacitance measurement and Dit analysis of vertical silicon MOS capacitors based on single NWs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131498125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994528
V. Jain, J. Rode, H. Chiang, A. Baraskar, E. Lobisser, B. Thibeault, M. Rodwell, M. Urteaga, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu
We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating fτ = 480 GHz and fmax = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz fmax even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (Wgap) to ∼ 10 nm, thereby significantly reducing the gap resistance term (Rgap) in the total base access resistance (Rbb), enabling a high fmax device. Reduction in the total collector base capacitance (Ccb) through undercut in the base mesa below base post further improved fmax. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (Je) without problems of electromigration or contact diffusion under electrical stress [1].
{"title":"1.0 THz fmax InP DHBTs in a refractory emitter and self-aligned base process for reduced base access resistance","authors":"V. Jain, J. Rode, H. Chiang, A. Baraskar, E. Lobisser, B. Thibeault, M. Rodwell, M. Urteaga, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu","doi":"10.1109/DRC.2011.5994528","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994528","url":null,"abstract":"We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating f<inf>τ</inf> = 480 GHz and f<inf>max</inf> = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz f<inf>max</inf> even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (W<inf>gap</inf>) to ∼ 10 nm, thereby significantly reducing the gap resistance term (R<inf>gap</inf>) in the total base access resistance (R<inf>bb</inf>), enabling a high f<inf>max</inf> device. Reduction in the total collector base capacitance (C<inf>cb</inf>) through undercut in the base mesa below base post further improved f<inf>max</inf>. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (J<inf>e</inf>) without problems of electromigration or contact diffusion under electrical stress [1].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994459
H. Dery, B. Ciftcioglu, Yang Song, Hui Wu, Michael C. Huang, R. Kawakami, Jing Shi, I. Krivorotov, I. Žutić, L. Sham
We present a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates [1,2] based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.
{"title":"Spintronics search engines","authors":"H. Dery, B. Ciftcioglu, Yang Song, Hui Wu, Michael C. Huang, R. Kawakami, Jing Shi, I. Krivorotov, I. Žutić, L. Sham","doi":"10.1109/DRC.2011.5994459","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994459","url":null,"abstract":"We present a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates [1,2] based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124365417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994439
K. M. Masum Habib, R. Lake
In graphene, a sheet of carbon atoms arranged in a honeycomb structure, charge carriers behave as massless Dirac fermions and move with extremely high speed leading to exotic electronic properties. However, lack of a band-gap reduces its utility for conventional electronic device applications. A tunable bandgap can be induced in bilayer graphene by application of a potential difference between the two layers.
{"title":"Numerical study of electronic transport through bilayer graphene nanoribbons","authors":"K. M. Masum Habib, R. Lake","doi":"10.1109/DRC.2011.5994439","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994439","url":null,"abstract":"In graphene, a sheet of carbon atoms arranged in a honeycomb structure, charge carriers behave as massless Dirac fermions and move with extremely high speed leading to exotic electronic properties. However, lack of a band-gap reduces its utility for conventional electronic device applications. A tunable bandgap can be induced in bilayer graphene by application of a potential difference between the two layers.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116143736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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