Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994464
Tian-shi Liu, G. Vignale
Spin wave spintronics (also known as magnonics) processes information by propagating spin waves with no charge displaced. Because dissipation is thus minimized this is rapidly becoming an important subject of research within the larger area of spintronics. The logic states in magnonic circuitry can be defined either by the phase or by the amplitude of the spin wave. In both cases, a π-phase shifter plays a crucial role in performing logical operations. The first spin wave logic gate was experimentally demonstrated by Kostylev et al 1. They utilized an inhomogeneous magnetic field to control the phase difference between spin waves propagating in different arms of a Mach-Zehnder interferometer -and thus the amplitude of the output spin wave. Later, Schneider et al 2 and Lee et al 3 developed a complete set of logic gates such as NOR, XOR and AND, based on spin wave interferometry. However, all of theses gates are controlled by a current-induced magnetic field. As the devices shrink down, π-phase shift requires a larger electric current to induce stronger magnetic field, which inevitably increases the power-loss. Therefore, voltage-controlled spin wave electronics becomes an attractive alternative avenue towards nano-scale magnonics, where exchange spin waves are of primary interest.
自旋波自旋电子学(也称为磁振学)通过传播没有电荷位移的自旋波来处理信息。由于耗散是如此最小化，这是迅速成为一个重要的研究课题，在更大的自旋电子学领域。磁电路中的逻辑状态可以由相位或自旋波的振幅来定义。在这两种情况下，π移相器在执行逻辑运算中起着至关重要的作用。第一个自旋波逻辑门是由Kostylev等人实验证明的。他们利用非均匀磁场来控制在马赫-曾德尔干涉仪不同臂上传播的自旋波之间的相位差，从而控制输出自旋波的振幅。后来Schneider et al . 2和Lee et al . 3基于自旋波干涉技术开发了一套完整的NOR、XOR、and等逻辑门。然而，所有这些门都是由电流感应磁场控制的。随着器件体积的缩小，π相移需要更大的电流来感应更强的磁场，这不可避免地增加了功率损耗。因此，电压控制的自旋波电子学成为纳米尺度磁学的一个有吸引力的替代途径，其中交换自旋波是主要的兴趣。
{"title":"Voltage-controlled spin-wave-based logic gate","authors":"Tian-shi Liu, G. Vignale","doi":"10.1109/DRC.2011.5994464","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994464","url":null,"abstract":"Spin wave spintronics (also known as magnonics) processes information by propagating spin waves with no charge displaced. Because dissipation is thus minimized this is rapidly becoming an important subject of research within the larger area of spintronics. The logic states in magnonic circuitry can be defined either by the phase or by the amplitude of the spin wave. In both cases, a π-phase shifter plays a crucial role in performing logical operations. The first spin wave logic gate was experimentally demonstrated by Kostylev et al 1. They utilized an inhomogeneous magnetic field to control the phase difference between spin waves propagating in different arms of a Mach-Zehnder interferometer -and thus the amplitude of the output spin wave. Later, Schneider et al 2 and Lee et al 3 developed a complete set of logic gates such as NOR, XOR and AND, based on spin wave interferometry. However, all of theses gates are controlled by a current-induced magnetic field. As the devices shrink down, π-phase shift requires a larger electric current to induce stronger magnetic field, which inevitably increases the power-loss. Therefore, voltage-controlled spin wave electronics becomes an attractive alternative avenue towards nano-scale magnonics, where exchange spin waves are of primary interest.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994462
C. Kshirsagar, S. Koester
Tunneling field-effect transistors (TFETs) are of tremendous interest for advanced logic applications due to their potential for sub-60-mV/dec subthreshold slope which could enable supply voltage scaling beyond what is practical for conventional MOSFETs. However, TFETs based upon tunneling in Si suffer from low on current, ION, and fail to provide steep slope at high current levels. III–V TFETs are more promising due to their potential for high drive current, but the poor gate oxide quality remains a significant challenge. Recently, a hybrid III–V-on-Si approach [1] has been proposed as a potential solution to this problem, whereby the small effective band gap, Egeff, of the InAs/Si heterojunction could increase ION, while preserving the high-quality Si/dielectric interface in the channel. Experimental demonstrations of nanostructured InAs-on-Si Esaki diodes and TFETs suggest this approach is feasible [1],[2]. However, InAs-on-Si heterostructures still exhibit relatively large Egeff (∼ 0.4 eV in unconfined geometries) and quantum effects increase Egeff substantially in confined geometries. In this paper, we provide a simulation analysis of a new device structure, the InAs/SiGe/Si TFET that could overcome this problem by utilizing a compressivelystrained SiGe layer to further decrease Egeff. We show that ION in these devices increases by 5× (at constant Ioff) and further explore the various trade-offs and performance-limiting factors in these devices.
隧道场效应晶体管(tfet)对于高级逻辑应用具有极大的兴趣，因为它们具有低于60 mv /dec的亚阈值斜率的潜力，可以使电源电压缩放超出传统mosfet的实用范围。然而，基于硅隧穿的tfet受到低电流、离子的影响，并且在高电流水平下不能提供陡峭的斜率。III-V型tfet由于具有高驱动电流的潜力而更有前景，但不良的栅极氧化物质量仍然是一个重大挑战。最近，一种III-V-on-Si的混合方法[1]被提出作为解决这一问题的潜在方法，即InAs/Si异质结的小有效带隙Egeff可以增加离子，同时保留通道中高质量的Si/介电界面。纳米结构的as -on- si Esaki二极管和tfet的实验证明，这种方法是可行的[1]，[2]。然而，InAs-on-Si异质结构仍然表现出相对较大的Egeff(在非受限几何中为~ 0.4 eV)，并且量子效应在受限几何中显著增加了Egeff。在本文中，我们提供了一个新的器件结构的仿真分析，InAs/SiGe/Si TFET可以克服这个问题，通过利用压缩应变SiGe层进一步降低Egeff。我们展示了这些设备中的离子增加了5倍(在恒定的off下)，并进一步探讨了这些设备中的各种权衡和性能限制因素。
{"title":"InAs/SiGe on Si nanowire tunneling field effect transistors","authors":"C. Kshirsagar, S. Koester","doi":"10.1109/DRC.2011.5994462","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994462","url":null,"abstract":"Tunneling field-effect transistors (TFETs) are of tremendous interest for advanced logic applications due to their potential for sub-60-mV/dec subthreshold slope which could enable supply voltage scaling beyond what is practical for conventional MOSFETs. However, TFETs based upon tunneling in Si suffer from low on current, ION, and fail to provide steep slope at high current levels. III–V TFETs are more promising due to their potential for high drive current, but the poor gate oxide quality remains a significant challenge. Recently, a hybrid III–V-on-Si approach [1] has been proposed as a potential solution to this problem, whereby the small effective band gap, Egeff, of the InAs/Si heterojunction could increase ION, while preserving the high-quality Si/dielectric interface in the channel. Experimental demonstrations of nanostructured InAs-on-Si Esaki diodes and TFETs suggest this approach is feasible [1],[2]. However, InAs-on-Si heterostructures still exhibit relatively large Egeff (∼ 0.4 eV in unconfined geometries) and quantum effects increase Egeff substantially in confined geometries. In this paper, we provide a simulation analysis of a new device structure, the InAs/SiGe/Si TFET that could overcome this problem by utilizing a compressivelystrained SiGe layer to further decrease Egeff. We show that ION in these devices increases by 5× (at constant Ioff) and further explore the various trade-offs and performance-limiting factors in these devices.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994466
N. Mojumder, S. Gupta, K. Roy
We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2–4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.
{"title":"Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations","authors":"N. Mojumder, S. Gupta, K. Roy","doi":"10.1109/DRC.2011.5994466","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994466","url":null,"abstract":"We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2–4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994448
T. Akyol, J. Yum, D. Ferrer, M. Lei, M. Downer, C. Bielawski, T. Hudnall, G. Bersuker, J.C. Lee, S. Banerjee
Using atomic layer deposited (ALD) Beryllium oxide (BeO) as a gate dielectric for the first time, we present improved surface channel MOSFETs on III–V substrates. We used a self-aligned gate-last process to fabricate MOSFETs on semi-insulating InP substrates with TaN gate electrode. The electrical characteristics of n-MOSFETs and MOS-Capacitors and physical characteristics of the BeO high-κ dielectric film were investigated and are summarized in this paper. BeO gate dielectric n-MOSFETs show excellent surface channel dc output characteristics, supporting high possibility of utilizing it in III–V CMOS technology.
{"title":"Introduction of ALD Beryllium oxide gate dielectric for III–V MOS devices","authors":"T. Akyol, J. Yum, D. Ferrer, M. Lei, M. Downer, C. Bielawski, T. Hudnall, G. Bersuker, J.C. Lee, S. Banerjee","doi":"10.1109/DRC.2011.5994448","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994448","url":null,"abstract":"Using atomic layer deposited (ALD) Beryllium oxide (BeO) as a gate dielectric for the first time, we present improved surface channel MOSFETs on III–V substrates. We used a self-aligned gate-last process to fabricate MOSFETs on semi-insulating InP substrates with TaN gate electrode. The electrical characteristics of n-MOSFETs and MOS-Capacitors and physical characteristics of the BeO high-κ dielectric film were investigated and are summarized in this paper. BeO gate dielectric n-MOSFETs show excellent surface channel dc output characteristics, supporting high possibility of utilizing it in III–V CMOS technology.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994482
Ji Cao, A. Ionescu
Carbon nanotubes (CNTs) have been intensively studied for nanoelectromechanical systems (NEMS) applications owing to their remarkable electrical and mechanical properties. Efforts have been made in single-walled CNT field-effect transistor (SWCNTFET) based ultrasensitive mass detection, radio-frequency (RF) signal processing, etc [1]. However, current techniques of manipulating CNTs (including: in-situ CNT growth and post-synthesis fabrication) often precludes bottom-up integration with pre-existing complementary metal-oxide-semiconductor (CMOS) circuits [2], due to: high process temperature, lack of self-alignment accuracy, etc.
{"title":"Lateral gate suspended-body carbon nanotube field-effect-transistors with sub-100nm air gap by precise positioning method","authors":"Ji Cao, A. Ionescu","doi":"10.1109/DRC.2011.5994482","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994482","url":null,"abstract":"Carbon nanotubes (CNTs) have been intensively studied for nanoelectromechanical systems (NEMS) applications owing to their remarkable electrical and mechanical properties. Efforts have been made in single-walled CNT field-effect transistor (SWCNTFET) based ultrasensitive mass detection, radio-frequency (RF) signal processing, etc [1]. However, current techniques of manipulating CNTs (including: in-situ CNT growth and post-synthesis fabrication) often precludes bottom-up integration with pre-existing complementary metal-oxide-semiconductor (CMOS) circuits [2], due to: high process temperature, lack of self-alignment accuracy, etc.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127903772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994415
M. Khayer, R. Lake
Band-to-band tunneling field-effect transistors (TFETs) have recently gained interest due to their operation in the sub-60 mV/decade limit which makes them ideal for reducing power dissipation in integrated circuit. III–V nanowire (NW) such as InSb NW TFETs show promise for ultra-low power and high-speed devices [1] due to its narrow direct bandgap.
{"title":"Effects of heavily doped source on the subthreshold characteristics of nanowire tunneling transistors","authors":"M. Khayer, R. Lake","doi":"10.1109/DRC.2011.5994415","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994415","url":null,"abstract":"Band-to-band tunneling field-effect transistors (TFETs) have recently gained interest due to their operation in the sub-60 mV/decade limit which makes them ideal for reducing power dissipation in integrated circuit. III–V nanowire (NW) such as InSb NW TFETs show promise for ultra-low power and high-speed devices [1] due to its narrow direct bandgap.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116704804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994479
H. Schmid, K. Moselund, M. Bjork, M. Richter, H. Ghoneim, C. Bessire, H. Riel
Gated p-i-n diodes operating as tunnel field effect transistors (TFETs) [1] are recently attracting much attention because of potential benefits over conventional MOSFETs. They are expected to have lower off-current, and operate at lower supply voltage compared to MOSFETs. Unfortunately, these promises are very difficult to realize using materials like Si, Ge and its alloys. However, encouraging experimental results were recently obtained using lower bandgap III–V (InGaAs) material systems [2, 3] offering higher tunneling probabilities. Here we report first results on the fabrication and electrical characterization of III–V / Si heterojunction TFETs with InAs as low bandgap source. This material combination maintains the advantages of Si as channel, drain and substrate material as proposed in [4].
{"title":"Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors","authors":"H. Schmid, K. Moselund, M. Bjork, M. Richter, H. Ghoneim, C. Bessire, H. Riel","doi":"10.1109/DRC.2011.5994479","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994479","url":null,"abstract":"Gated p-i-n diodes operating as tunnel field effect transistors (TFETs) [1] are recently attracting much attention because of potential benefits over conventional MOSFETs. They are expected to have lower off-current, and operate at lower supply voltage compared to MOSFETs. Unfortunately, these promises are very difficult to realize using materials like Si, Ge and its alloys. However, encouraging experimental results were recently obtained using lower bandgap III–V (InGaAs) material systems [2, 3] offering higher tunneling probabilities. Here we report first results on the fabrication and electrical characterization of III–V / Si heterojunction TFETs with InAs as low bandgap source. This material combination maintains the advantages of Si as channel, drain and substrate material as proposed in [4].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116705072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994402
A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell
Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (Raccess < 50 Ω-µ,1 and Dit < 2 · 1012 cm−2 eV−1,2 respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (Lg), e.g. 116 nm at 32 nm Lg,3 while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm Lg In0.53Ga0.47As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at Vds = 1.25 V and Vgs = 3 V and an Ron = 341 ohm-µm. To our knowledge this is the lowest Ron and smallest Lg reported to date for In0.53Ga0.47As surface channel MOSFETs.4
{"title":"60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth","authors":"A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell","doi":"10.1109/DRC.2011.5994402","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994402","url":null,"abstract":"Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (R<inf>access</inf> < 50 Ω-µ,<sup>1</sup> and D<inf>it</inf> < 2 · 10<sup>12</sup> cm<sup>−2</sup> eV<sup>−1,2</sup> respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (L<inf>g</inf>), e.g. 116 nm at 32 nm L<inf>g</inf>,<sup>3</sup> while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm L<inf>g</inf> In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at V<inf>ds</inf> = 1.25 V and V<inf>gs</inf> = 3 V and an R<inf>on</inf> = 341 ohm-µm. To our knowledge this is the lowest R<inf>on</inf> and smallest L<inf>g</inf> reported to date for In<inf>0.53</inf>Ga<inf>0.47</inf>As surface channel MOSFETs.<sup>4</sup>","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994496
S. Agarwal, E. Yablonovitch
In order to achieve significantly reduced power consumption, the transistor operating voltage needs to be reduced. To do this, a tunneling based transistor needs to rely on the density of states turn-on as shown in Fig 1 [1]. Current can only flow when the conduction and valence bands overlap. If the band edges are ideal, one might expect an infinitely sharp turn on when the band edges overlap. Surprisingly, in a typical 3d bulk TFET, the nature of the turn on is actually quadratic in the gate voltage. Nevertheless, it is possible improve this if dimensionality is reduced. Consequently, we explored the nature of the band overlap for the various dimensionalities shown in Fig 2. We find that a 2d-2d pn junction, as shown in Fig. 2(i) brings us significantly closer to an ideal step function. Confining each side of the pn junction will also significantly increase the on state conductivity at low voltages.
{"title":"Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on","authors":"S. Agarwal, E. Yablonovitch","doi":"10.1109/DRC.2011.5994496","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994496","url":null,"abstract":"In order to achieve significantly reduced power consumption, the transistor operating voltage needs to be reduced. To do this, a tunneling based transistor needs to rely on the density of states turn-on as shown in Fig 1 [1]. Current can only flow when the conduction and valence bands overlap. If the band edges are ideal, one might expect an infinitely sharp turn on when the band edges overlap. Surprisingly, in a typical 3d bulk TFET, the nature of the turn on is actually quadratic in the gate voltage. Nevertheless, it is possible improve this if dimensionality is reduced. Consequently, we explored the nature of the band overlap for the various dimensionalities shown in Fig 2. We find that a 2d-2d pn junction, as shown in Fig. 2(i) brings us significantly closer to an ideal step function. Confining each side of the pn junction will also significantly increase the on state conductivity at low voltages.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994512
Junkyo Suh, R. Nakane, N. Taoka, M. Takenaka, S. Takagi
Much attention has recently been paid to MOS channel materials with high mobility and resulting high injection velocity that can increase ION and reduce delay [1]. Among them, ultrathin body SiGe-On-Insulator (SGOI) structure with high compressive strain and high Ge content is a promising channel material for pMOSFETs under future technology nodes. Here, many theoretical studies [2–4] have reported that incorporation of a large amount of compressive strain into SiGe materials is a key technology for boosting the performance. Also, one of promising techniques for fabricating the SGOI structures is Ge condensation technique, composed of epitaxial growth of SiGe layers on SOI substrates and successive thermal oxidation [5, 6]. It is known, however, in Ge condensation using conventional unstrained SOI substrates [5, 7, 8] that strain relaxation occurs when Ge content becomes ∼0.60 and strain significantly decreases with an increase in Ge content. This strain relaxation has been attributed to crystal defect generation during Ge condensation, induced by large strain in the SGOI due to the lattice mismatch between Si and Ge [8–10].
{"title":"Highly-strained SGOI p-channel MOSFETs fabricated by applying Ge condensation technique to strained-SOI substrates","authors":"Junkyo Suh, R. Nakane, N. Taoka, M. Takenaka, S. Takagi","doi":"10.1109/DRC.2011.5994512","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994512","url":null,"abstract":"Much attention has recently been paid to MOS channel materials with high mobility and resulting high injection velocity that can increase ION and reduce delay [1]. Among them, ultrathin body SiGe-On-Insulator (SGOI) structure with high compressive strain and high Ge content is a promising channel material for pMOSFETs under future technology nodes. Here, many theoretical studies [2–4] have reported that incorporation of a large amount of compressive strain into SiGe materials is a key technology for boosting the performance. Also, one of promising techniques for fabricating the SGOI structures is Ge condensation technique, composed of epitaxial growth of SiGe layers on SOI substrates and successive thermal oxidation [5, 6]. It is known, however, in Ge condensation using conventional unstrained SOI substrates [5, 7, 8] that strain relaxation occurs when Ge content becomes ∼0.60 and strain significantly decreases with an increase in Ge content. This strain relaxation has been attributed to crystal defect generation during Ge condensation, induced by large strain in the SGOI due to the lattice mismatch between Si and Ge [8–10].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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