Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994485
J. Rogers
Biology is curved, soft and elastic; silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. This talk describes the development of ideas for electronics that offer the performance of state-of-the-art, wafer-based systems but with the mechanical properties of a rubber band. We explain the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ‘tissue-like’ electronics with unique capabilities in electrocorticography and cardiac electrophysiology, in both endocardial and epicardial modes. In vivo demonstrations with animal models illustrate the functionality offered by these technologies, and suggest several clinically relevant applications.
{"title":"Soft, curvilinear semiconductor devices for bio-integrated electronics","authors":"J. Rogers","doi":"10.1109/DRC.2011.5994485","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994485","url":null,"abstract":"Biology is curved, soft and elastic; silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. This talk describes the development of ideas for electronics that offer the performance of state-of-the-art, wafer-based systems but with the mechanical properties of a rubber band. We explain the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ‘tissue-like’ electronics with unique capabilities in electrocorticography and cardiac electrophysiology, in both endocardial and epicardial modes. In vivo demonstrations with animal models illustrate the functionality offered by these technologies, and suggest several clinically relevant applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994474
S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan
We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.
{"title":"A hybrid ferroelectric and charge nonvolatile memory","authors":"S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan","doi":"10.1109/DRC.2011.5994474","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994474","url":null,"abstract":"We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994424
A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel
Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (Lch) and width (Wch) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of Wch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.
{"title":"The effect of field effect device channel dimensions on the effective mobility of graphene","authors":"A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel","doi":"10.1109/DRC.2011.5994424","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994424","url":null,"abstract":"Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (Lch) and width (Wch) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of Wch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994440
L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu
The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.
{"title":"Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier","authors":"L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu","doi":"10.1109/DRC.2011.5994440","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994440","url":null,"abstract":"The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133397134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994497
E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani
In this work we investigate the feasibility of a steep-slope nanowire FET based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Several material pairs are investigated for the superlattice, with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the GaN-AlGaN pair provides excellent results, which led us to optimize its device structure. We obtain a peak SS ≈ 15 mV/dec and an ON-current approaching 1mA/μm.
{"title":"Investigation on superlattice heterostructures for steep-slope nanowire FETs","authors":"E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani","doi":"10.1109/DRC.2011.5994497","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994497","url":null,"abstract":"In this work we investigate the feasibility of a steep-slope nanowire FET based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Several material pairs are investigated for the superlattice, with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the GaN-AlGaN pair provides excellent results, which led us to optimize its device structure. We obtain a peak SS ≈ 15 mV/dec and an ON-current approaching 1mA/μm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994463
R. Sporea, J. Shannon, S. Silva
Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].
{"title":"High-resolution temperature sensing with source-gated transistors","authors":"R. Sporea, J. Shannon, S. Silva","doi":"10.1109/DRC.2011.5994463","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994463","url":null,"abstract":"Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131909448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994529
T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena
As GaN HEMTs are scaled down to push performance into 100's of GHz range, it is timely to investigate their performance limits. Unlike Si MOSFETs and most other III–V semiconductor based HEMTs, the electron - polar optical phonon interaction is exceptionally strong in GaN. As a result, the mean free path of hot electrons in GaN is λop ∼ 3.5nm, far shorter than typical HEMT gate lengths (Lg). Thus while Si MOSFETs and other III-V HEMTs can approach near ballistic behavior by reduction of parasitic delays and Lg, the situation is starkly different for GaN HEMTs. Here, we investigate the intrinsic performance limits of GaN HEMTs by incorporating the effect of polar optical phonon backscattering into a quasi-ballistic model. Then, we include parasitic elements and quantitatively investigate the degradation in performance. The method used is semi-analytical, and will prove very helpful in designing future generations of devices. The work not only sets a roadmap for scaling to high speeds, it also offers clear physical reasons for a number of unexplained features observed in state-of-the-art GaN HEMTs.
{"title":"Effect of optical phonon scattering on the performance limits of ultrafast GaN transistors","authors":"T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena","doi":"10.1109/DRC.2011.5994529","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994529","url":null,"abstract":"As GaN HEMTs are scaled down to push performance into 100's of GHz range, it is timely to investigate their performance limits. Unlike Si MOSFETs and most other III–V semiconductor based HEMTs, the electron - polar optical phonon interaction is exceptionally strong in GaN. As a result, the mean free path of hot electrons in GaN is λop ∼ 3.5nm, far shorter than typical HEMT gate lengths (Lg). Thus while Si MOSFETs and other III-V HEMTs can approach near ballistic behavior by reduction of parasitic delays and Lg, the situation is starkly different for GaN HEMTs. Here, we investigate the intrinsic performance limits of GaN HEMTs by incorporating the effect of polar optical phonon backscattering into a quasi-ballistic model. Then, we include parasitic elements and quantitatively investigate the degradation in performance. The method used is semi-analytical, and will prove very helpful in designing future generations of devices. The work not only sets a roadmap for scaling to high speeds, it also offers clear physical reasons for a number of unexplained features observed in state-of-the-art GaN HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994417
Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, S. Cai, K. J. Chen
Devices with steep subthreshold swing (SS) are of great interest and significance in view of increasing subthreshold leakage current with the continuous MOSFET scaling. The standby power dissipation has grown due to the nonscalability of the SS to below 60 mV/dec at room temperature (RT). To circumvent this obstacle, novel devices that employ various turn-on mechanisms have been proposed1–4. In this work, we report the observation of steep SS∼20 mV/dec in Schottky source/drain (SSD) Al2O3/InAlN/GaN MIS-HEMTs over a drain bias range of 0.1 to 5 V. The devices also feature high ION/IOFF ratio (∼109) and appreciable current drive of IDmax=230 mA/mm at room temperature. The devices are also characterized at elevated temperature (T) up to 155 °C. Steep SS lower than the theoretical diffusion limit is consistently observed over the testing temperature range. It is suggested that the steep switching behavior is obtained through the means of a dynamic de-trapping process at the Al2O3/InAlN interface. The dynamic de-trapping enables a dynamic negative shift in the threshold voltage during the gate upswing and effectively facilitates the formation of a sub-threshold swing as steep as 18 mV/dec.
{"title":"Observation of trap-assisted steep sub-threshold swing in schottky source/drain Al2O3/InAlN/GaN MISHEMT","authors":"Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, S. Cai, K. J. Chen","doi":"10.1109/DRC.2011.5994417","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994417","url":null,"abstract":"Devices with steep subthreshold swing (SS) are of great interest and significance in view of increasing subthreshold leakage current with the continuous MOSFET scaling. The standby power dissipation has grown due to the nonscalability of the SS to below 60 mV/dec at room temperature (RT). To circumvent this obstacle, novel devices that employ various turn-on mechanisms have been proposed1–4. In this work, we report the observation of steep SS∼20 mV/dec in Schottky source/drain (SSD) Al2O3/InAlN/GaN MIS-HEMTs over a drain bias range of 0.1 to 5 V. The devices also feature high ION/IOFF ratio (∼109) and appreciable current drive of IDmax=230 mA/mm at room temperature. The devices are also characterized at elevated temperature (T) up to 155 °C. Steep SS lower than the theoretical diffusion limit is consistently observed over the testing temperature range. It is suggested that the steep switching behavior is obtained through the means of a dynamic de-trapping process at the Al2O3/InAlN interface. The dynamic de-trapping enables a dynamic negative shift in the threshold voltage during the gate upswing and effectively facilitates the formation of a sub-threshold swing as steep as 18 mV/dec.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994477
H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk
Field-effect transistors (FETs) that utilize an individual semiconducting carbon nanotube (CNT) as the channel are potentially useful for the realization of logic circuits with high integration densities that can be fabricated on transparent, large-area substrates, such as glass or flexible plastics. While FETs based on individual CNTs have already demonstrated excellent static characteristics [1,2], the realization of logic circuits with good static and dynamic performance based on individual-CNT FETs remains a challenge. Bachtold et al. realized 2-input NOR gates by connecting p-channel CNT FETs to external load resistors using coaxial cables and reported a signal delay of 30 msec per stage for a 3-stage unipolar ring oscillator [3]. Javey et al. realized complementary 2-input NAND, AND, NOR and OR gates by connecting p- and n-channel CNT FETs using coaxial cables and measured a delay of 750 µsec for a 3-stage ring oscillator [4]. The only monolithically integrated circuit based transistors utilizing individual carbon nanotubes was reported by Chen et al. who measured a signal delay of 1.9 nsec per stage in a complementary ring oscillator realized on a very long (19 µm) carbon nanotube [5].
{"title":"Combinational and sequential logic with transistors based on individual carbon nanotubes","authors":"H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk","doi":"10.1109/DRC.2011.5994477","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994477","url":null,"abstract":"Field-effect transistors (FETs) that utilize an individual semiconducting carbon nanotube (CNT) as the channel are potentially useful for the realization of logic circuits with high integration densities that can be fabricated on transparent, large-area substrates, such as glass or flexible plastics. While FETs based on individual CNTs have already demonstrated excellent static characteristics [1,2], the realization of logic circuits with good static and dynamic performance based on individual-CNT FETs remains a challenge. Bachtold et al. realized 2-input NOR gates by connecting p-channel CNT FETs to external load resistors using coaxial cables and reported a signal delay of 30 msec per stage for a 3-stage unipolar ring oscillator [3]. Javey et al. realized complementary 2-input NAND, AND, NOR and OR gates by connecting p- and n-channel CNT FETs using coaxial cables and measured a delay of 750 µsec for a 3-stage ring oscillator [4]. The only monolithically integrated circuit based transistors utilizing individual carbon nanotubes was reported by Chen et al. who measured a signal delay of 1.9 nsec per stage in a complementary ring oscillator realized on a very long (19 µm) carbon nanotube [5].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994425
Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi
Germanium nanowires (GeNWs) of the group IV semiconductors could be one of the attractive candidates for electron-spin based quantum devices because of their long electron-spin coherence time. Besides, Ge has an advantage over Si in terms of the larger quantum effects due to the smaller effective mass. Single-electron transistors (SETs) are basic building blocks of such devices. To define the spin configuration in the dot, it is necessary to reach a few-electron regime or an even-odd regime where the single spin is realized for the odd number of electrons in the dot. So far, we have developed processes to fabricate SETs using n-type monocrystalline GeNWs with a back gate, and succeeded in observing the even-odd effect [1]. In this work, we have developed fabrication processes of the top-gate SETs to enhance the gating efficiency, and succeeded in reaching a few-electron regime.
{"title":"Top-gated single-electron transistor in germanium nanowires","authors":"Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi","doi":"10.1109/DRC.2011.5994425","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994425","url":null,"abstract":"Germanium nanowires (GeNWs) of the group IV semiconductors could be one of the attractive candidates for electron-spin based quantum devices because of their long electron-spin coherence time. Besides, Ge has an advantage over Si in terms of the larger quantum effects due to the smaller effective mass. Single-electron transistors (SETs) are basic building blocks of such devices. To define the spin configuration in the dot, it is necessary to reach a few-electron regime or an even-odd regime where the single spin is realized for the odd number of electrons in the dot. So far, we have developed processes to fabricate SETs using n-type monocrystalline GeNWs with a back gate, and succeeded in observing the even-odd effect [1]. In this work, we have developed fabrication processes of the top-gate SETs to enhance the gating efficiency, and succeeded in reaching a few-electron regime.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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