Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994528
V. Jain, J. Rode, H. Chiang, A. Baraskar, E. Lobisser, B. Thibeault, M. Rodwell, M. Urteaga, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu
We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating fτ = 480 GHz and fmax = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz fmax even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (Wgap) to ∼ 10 nm, thereby significantly reducing the gap resistance term (Rgap) in the total base access resistance (Rbb), enabling a high fmax device. Reduction in the total collector base capacitance (Ccb) through undercut in the base mesa below base post further improved fmax. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (Je) without problems of electromigration or contact diffusion under electrical stress [1].
{"title":"1.0 THz fmax InP DHBTs in a refractory emitter and self-aligned base process for reduced base access resistance","authors":"V. Jain, J. Rode, H. Chiang, A. Baraskar, E. Lobisser, B. Thibeault, M. Rodwell, M. Urteaga, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu","doi":"10.1109/DRC.2011.5994528","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994528","url":null,"abstract":"We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating f<inf>τ</inf> = 480 GHz and f<inf>max</inf> = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz f<inf>max</inf> even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (W<inf>gap</inf>) to ∼ 10 nm, thereby significantly reducing the gap resistance term (R<inf>gap</inf>) in the total base access resistance (R<inf>bb</inf>), enabling a high f<inf>max</inf> device. Reduction in the total collector base capacitance (C<inf>cb</inf>) through undercut in the base mesa below base post further improved f<inf>max</inf>. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (J<inf>e</inf>) without problems of electromigration or contact diffusion under electrical stress [1].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994424
A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel
Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (Lch) and width (Wch) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of Wch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.
{"title":"The effect of field effect device channel dimensions on the effective mobility of graphene","authors":"A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel","doi":"10.1109/DRC.2011.5994424","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994424","url":null,"abstract":"Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (Lch) and width (Wch) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of Wch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994474
S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan
We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.
{"title":"A hybrid ferroelectric and charge nonvolatile memory","authors":"S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan","doi":"10.1109/DRC.2011.5994474","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994474","url":null,"abstract":"We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994440
L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu
The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.
{"title":"Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier","authors":"L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu","doi":"10.1109/DRC.2011.5994440","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994440","url":null,"abstract":"The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133397134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994497
E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani
In this work we investigate the feasibility of a steep-slope nanowire FET based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Several material pairs are investigated for the superlattice, with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the GaN-AlGaN pair provides excellent results, which led us to optimize its device structure. We obtain a peak SS ≈ 15 mV/dec and an ON-current approaching 1mA/μm.
{"title":"Investigation on superlattice heterostructures for steep-slope nanowire FETs","authors":"E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani","doi":"10.1109/DRC.2011.5994497","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994497","url":null,"abstract":"In this work we investigate the feasibility of a steep-slope nanowire FET based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Several material pairs are investigated for the superlattice, with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the GaN-AlGaN pair provides excellent results, which led us to optimize its device structure. We obtain a peak SS ≈ 15 mV/dec and an ON-current approaching 1mA/μm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994463
R. Sporea, J. Shannon, S. Silva
Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].
{"title":"High-resolution temperature sensing with source-gated transistors","authors":"R. Sporea, J. Shannon, S. Silva","doi":"10.1109/DRC.2011.5994463","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994463","url":null,"abstract":"Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131909448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994529
T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena
As GaN HEMTs are scaled down to push performance into 100's of GHz range, it is timely to investigate their performance limits. Unlike Si MOSFETs and most other III–V semiconductor based HEMTs, the electron - polar optical phonon interaction is exceptionally strong in GaN. As a result, the mean free path of hot electrons in GaN is λop ∼ 3.5nm, far shorter than typical HEMT gate lengths (Lg). Thus while Si MOSFETs and other III-V HEMTs can approach near ballistic behavior by reduction of parasitic delays and Lg, the situation is starkly different for GaN HEMTs. Here, we investigate the intrinsic performance limits of GaN HEMTs by incorporating the effect of polar optical phonon backscattering into a quasi-ballistic model. Then, we include parasitic elements and quantitatively investigate the degradation in performance. The method used is semi-analytical, and will prove very helpful in designing future generations of devices. The work not only sets a roadmap for scaling to high speeds, it also offers clear physical reasons for a number of unexplained features observed in state-of-the-art GaN HEMTs.
{"title":"Effect of optical phonon scattering on the performance limits of ultrafast GaN transistors","authors":"T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena","doi":"10.1109/DRC.2011.5994529","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994529","url":null,"abstract":"As GaN HEMTs are scaled down to push performance into 100's of GHz range, it is timely to investigate their performance limits. Unlike Si MOSFETs and most other III–V semiconductor based HEMTs, the electron - polar optical phonon interaction is exceptionally strong in GaN. As a result, the mean free path of hot electrons in GaN is λop ∼ 3.5nm, far shorter than typical HEMT gate lengths (Lg). Thus while Si MOSFETs and other III-V HEMTs can approach near ballistic behavior by reduction of parasitic delays and Lg, the situation is starkly different for GaN HEMTs. Here, we investigate the intrinsic performance limits of GaN HEMTs by incorporating the effect of polar optical phonon backscattering into a quasi-ballistic model. Then, we include parasitic elements and quantitatively investigate the degradation in performance. The method used is semi-analytical, and will prove very helpful in designing future generations of devices. The work not only sets a roadmap for scaling to high speeds, it also offers clear physical reasons for a number of unexplained features observed in state-of-the-art GaN HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994477
H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk
Field-effect transistors (FETs) that utilize an individual semiconducting carbon nanotube (CNT) as the channel are potentially useful for the realization of logic circuits with high integration densities that can be fabricated on transparent, large-area substrates, such as glass or flexible plastics. While FETs based on individual CNTs have already demonstrated excellent static characteristics [1,2], the realization of logic circuits with good static and dynamic performance based on individual-CNT FETs remains a challenge. Bachtold et al. realized 2-input NOR gates by connecting p-channel CNT FETs to external load resistors using coaxial cables and reported a signal delay of 30 msec per stage for a 3-stage unipolar ring oscillator [3]. Javey et al. realized complementary 2-input NAND, AND, NOR and OR gates by connecting p- and n-channel CNT FETs using coaxial cables and measured a delay of 750 µsec for a 3-stage ring oscillator [4]. The only monolithically integrated circuit based transistors utilizing individual carbon nanotubes was reported by Chen et al. who measured a signal delay of 1.9 nsec per stage in a complementary ring oscillator realized on a very long (19 µm) carbon nanotube [5].
{"title":"Combinational and sequential logic with transistors based on individual carbon nanotubes","authors":"H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk","doi":"10.1109/DRC.2011.5994477","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994477","url":null,"abstract":"Field-effect transistors (FETs) that utilize an individual semiconducting carbon nanotube (CNT) as the channel are potentially useful for the realization of logic circuits with high integration densities that can be fabricated on transparent, large-area substrates, such as glass or flexible plastics. While FETs based on individual CNTs have already demonstrated excellent static characteristics [1,2], the realization of logic circuits with good static and dynamic performance based on individual-CNT FETs remains a challenge. Bachtold et al. realized 2-input NOR gates by connecting p-channel CNT FETs to external load resistors using coaxial cables and reported a signal delay of 30 msec per stage for a 3-stage unipolar ring oscillator [3]. Javey et al. realized complementary 2-input NAND, AND, NOR and OR gates by connecting p- and n-channel CNT FETs using coaxial cables and measured a delay of 750 µsec for a 3-stage ring oscillator [4]. The only monolithically integrated circuit based transistors utilizing individual carbon nanotubes was reported by Chen et al. who measured a signal delay of 1.9 nsec per stage in a complementary ring oscillator realized on a very long (19 µm) carbon nanotube [5].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994409
B. Fallahazad, Kayoung Lee, Seyoung Kim, C. Corbet, E. Tutuc
Graphene has emerged recently as an attractive channel material for high frequency analog device applications. High carrier mobility and large gate capacitance are both desirable attributes for such devices. A main obstacle however in depositing thin dielectrics on graphene, with high dielectric constant is its chemical inertness. This obstacle can be overcome by either directly depositing the dielectric, e.g. using sputtering or e-beam evaporation, or by using a seed layer which provides nucleation sites for atomic layer deposition (ALD). The interfacial layer however reduces the gate capacitance and can also impact the quality of the ALD dielectric subsequently grown. Here we provide a systematic study of gate capacitance scaling of graphene field effect transistors with Al2O3 gate dielectric with two seed layers, oxidized aluminum and oxidized titanium. Our results show the oxidized Ti film on graphene provides a smooth surface, which allows us to use a Ti nucleation layer as thin as 6Å, and achieve uniform coverage required for the subsequent ALD. The k-value of the ALD Al2O3 grown on graphene using oxidized Ti as nucleation layer is 12.7, a value 2.5 times larger than the ALD Al2O3 grown using oxidized Al. We demonstrate graphene devices with ultra-thin top gate dielectrics, with EOT values as low as 3.5 nm.
{"title":"Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics","authors":"B. Fallahazad, Kayoung Lee, Seyoung Kim, C. Corbet, E. Tutuc","doi":"10.1109/DRC.2011.5994409","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994409","url":null,"abstract":"Graphene has emerged recently as an attractive channel material for high frequency analog device applications. High carrier mobility and large gate capacitance are both desirable attributes for such devices. A main obstacle however in depositing thin dielectrics on graphene, with high dielectric constant is its chemical inertness. This obstacle can be overcome by either directly depositing the dielectric, e.g. using sputtering or e-beam evaporation, or by using a seed layer which provides nucleation sites for atomic layer deposition (ALD). The interfacial layer however reduces the gate capacitance and can also impact the quality of the ALD dielectric subsequently grown. Here we provide a systematic study of gate capacitance scaling of graphene field effect transistors with Al2O3 gate dielectric with two seed layers, oxidized aluminum and oxidized titanium. Our results show the oxidized Ti film on graphene provides a smooth surface, which allows us to use a Ti nucleation layer as thin as 6Å, and achieve uniform coverage required for the subsequent ALD. The k-value of the ALD Al2O3 grown on graphene using oxidized Ti as nucleation layer is 12.7, a value 2.5 times larger than the ALD Al2O3 grown using oxidized Al. We demonstrate graphene devices with ultra-thin top gate dielectrics, with EOT values as low as 3.5 nm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994531
N. Nidhi, S. Dasgupta, J. Lu, F. Wu, S. Keller, J. Speck, U. Mishra
Ga-polar InAlN-based charge-inducing barrier for HEMTs have been recently demonstrated as a viable technology for high frequency applications due to high polarization charge and hence, low resistance channels [1,2]. In this paper, we report on MBE-grown N-polar GaN/InAlN HEMTs with excellent DC and RF performance. There exists a discrepancy in the DC and RF data for N-polar MBE InAlN devices which is explained through several measurements and analysis and possible solutions are discussed.
{"title":"Trap-related delay analysis of self-aligned N-polar GaN/InAlN HEMTs with record extrinsic gm of 1105 mS/mm","authors":"N. Nidhi, S. Dasgupta, J. Lu, F. Wu, S. Keller, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.5994531","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994531","url":null,"abstract":"Ga-polar InAlN-based charge-inducing barrier for HEMTs have been recently demonstrated as a viable technology for high frequency applications due to high polarization charge and hence, low resistance channels [1,2]. In this paper, we report on MBE-grown N-polar GaN/InAlN HEMTs with excellent DC and RF performance. There exists a discrepancy in the DC and RF data for N-polar MBE InAlN devices which is explained through several measurements and analysis and possible solutions are discussed.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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