Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994445
S. Ganguly, J. Verma, Guowang Li, T. Zimmermann, H. Xing, D. Jena
Atomic layer deposited (ALD) high band gap (∼6.5eV) [1], high k (∼9.1) Al2O3 has emerged as an attractive candidate to support vertical scaling of AlN/GaN HEMTs [2] and its variants owing to its outstanding dielectric, thermal, and chemical properties. Integration of ALD oxides with GaN will enable lower gate leakage currents, high breakdown voltages, and surface passivation. In this work we present a comprehensive characterization of AlN/GaN MOS-HEMT gate stacks with ALD Al2O3 of various thicknesses. Through capacitance-voltage and Hall-effect measurements, we find the presence and propose an origin of benign donor-type interface charge (Qint) at the AlN/Al2O3 junction, and relate its presence to the polarization charges in AlN. By studying tunneling transport in corresponding (Ni/Al2O3/Ni) M-I-M diodes, we extract the Ni/Al2O3 surface barrier height (ФB), the electron tunneling effective mass in Al2O3, and discuss the resulting HEMTs.
{"title":"Barrier height, interface charge & tunneling effective mass in ALD Al2O3/AlN/GaN HEMTs","authors":"S. Ganguly, J. Verma, Guowang Li, T. Zimmermann, H. Xing, D. Jena","doi":"10.1109/DRC.2011.5994445","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994445","url":null,"abstract":"Atomic layer deposited (ALD) high band gap (∼6.5eV) [1], high k (∼9.1) Al<inf>2</inf>O<inf>3</inf> has emerged as an attractive candidate to support vertical scaling of AlN/GaN HEMTs [2] and its variants owing to its outstanding dielectric, thermal, and chemical properties. Integration of ALD oxides with GaN will enable lower gate leakage currents, high breakdown voltages, and surface passivation. In this work we present a comprehensive characterization of AlN/GaN MOS-HEMT gate stacks with ALD Al<inf>2</inf>O<inf>3</inf> of various thicknesses. Through capacitance-voltage and Hall-effect measurements, we find the presence and propose an origin of benign donor-type interface charge (Q<inf>int</inf>) at the AlN/Al<inf>2</inf>O<inf>3</inf> junction, and relate its presence to the polarization charges in AlN. By studying tunneling transport in corresponding (Ni/Al<inf>2</inf>O<inf>3</inf>/Ni) M-I-M diodes, we extract the Ni/Al<inf>2</inf>O<inf>3</inf> surface barrier height (Ф<inf>B</inf>), the electron tunneling effective mass in Al<inf>2</inf>O<inf>3</inf>, and discuss the resulting HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124583620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994503
A. Corrion, M. Chen, R. Chu, S. Burnham, S. Khalil, D. Zehnder, B. Hughes, K. Boutros
GaN-based HFETs offer a combination of high breakdown field, high current densities, and low on-resistance, making them well-suited for power-switching applications. Normally-off FETs are preferred in power switching applications for circuit simplicity and safety. Recently, a new type of normally-off GaN device has been reported: the hybrid metal-oxide-semiconductor (MOS)- or metal-insulator-semiconductor (MIS)-HFET, consisting of an MOS-type structure under the gate for normally-off operation and an HFET-like structure in the access regions for low on-resistance [1–6]. Optimization of the insulator-epi interface and insulator quality is critical for this type of device, since the electrons under gate electrode are in direct contact with the gate insulator. Previous reports of hybrid MOS-HFETs used SiO2 or SiN gate dielectrics deposited by plasma-enhanced chemical vapor deposition (PECVD). However, alternative deposition methods such as atomic layer deposition (ALD) have been shown to result in superior thickness control, uniformity, conformality, and film quality, while ALD high-k gate dielectrics such as Al2O3 have generated significant interest for GaN HFETs due to excellent GaN interface quality. In this work, we fabricated normally-off AlGaN/GaN hybrid MOS-HFETs on (111) Si substrates using gate recess etching combined with an ALD Al2O3 gate dielectric for low gate leakage, low on-resistance, and high breakdown voltage. The gate fabrication process was optimized to reduce the trap density associated with the dielectric and eliminate threshold voltage hysteresis, which can result from slow traps in the dielectric or at the dielectric-epi interface [7]. A three-terminal breakdown voltage (VB) of 1370V was measured at a gate bias of 0 V on a device with a 20 mm gate periphery and a low specific on-resistance (Ron) of 9.0 mΩ-cm2. The resulting VB2/Ron figure of merit of 208 MW/cm2 is among the highest values reported to-date for normally-off GaN-on-Si HFETs.
{"title":"Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric","authors":"A. Corrion, M. Chen, R. Chu, S. Burnham, S. Khalil, D. Zehnder, B. Hughes, K. Boutros","doi":"10.1109/DRC.2011.5994503","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994503","url":null,"abstract":"GaN-based HFETs offer a combination of high breakdown field, high current densities, and low on-resistance, making them well-suited for power-switching applications. Normally-off FETs are preferred in power switching applications for circuit simplicity and safety. Recently, a new type of normally-off GaN device has been reported: the hybrid metal-oxide-semiconductor (MOS)- or metal-insulator-semiconductor (MIS)-HFET, consisting of an MOS-type structure under the gate for normally-off operation and an HFET-like structure in the access regions for low on-resistance [1–6]. Optimization of the insulator-epi interface and insulator quality is critical for this type of device, since the electrons under gate electrode are in direct contact with the gate insulator. Previous reports of hybrid MOS-HFETs used SiO2 or SiN gate dielectrics deposited by plasma-enhanced chemical vapor deposition (PECVD). However, alternative deposition methods such as atomic layer deposition (ALD) have been shown to result in superior thickness control, uniformity, conformality, and film quality, while ALD high-k gate dielectrics such as Al2O3 have generated significant interest for GaN HFETs due to excellent GaN interface quality. In this work, we fabricated normally-off AlGaN/GaN hybrid MOS-HFETs on (111) Si substrates using gate recess etching combined with an ALD Al2O3 gate dielectric for low gate leakage, low on-resistance, and high breakdown voltage. The gate fabrication process was optimized to reduce the trap density associated with the dielectric and eliminate threshold voltage hysteresis, which can result from slow traps in the dielectric or at the dielectric-epi interface [7]. A three-terminal breakdown voltage (VB) of 1370V was measured at a gate bias of 0 V on a device with a 20 mm gate periphery and a low specific on-resistance (Ron) of 9.0 mΩ-cm2. The resulting VB2/Ron figure of merit of 208 MW/cm2 is among the highest values reported to-date for normally-off GaN-on-Si HFETs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123450748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994452
Sung Hwan Kim, Z. Jacobson, P. Patel, C. Hu, T. Liu
Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.
{"title":"Tunnel FET-based pass-transistor logic for ultra-low-power applications","authors":"Sung Hwan Kim, Z. Jacobson, P. Patel, C. Hu, T. Liu","doi":"10.1109/DRC.2011.5994452","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994452","url":null,"abstract":"Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121585392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994498
D. Mohata, R. Bijesh, V. Saripalli, T. Mayer, S. Datta
Tunnel field effect transistors (TFET) have gained interest recently owing to their potential in achieving sub-kT/q steep switching slope, thus promising low Vcc operation[1–5]. Steep switching slope has already been demonstrated in Silicon TFET [2]. However, it has been theoretically shown and experimentally proved that Si or SixGe1−x based homo-junction or hetero-junction TFETs would not meet the drive current requirement for future low power high performance logic applications [3]. III–V based hetero-junction TFETs have shown promise to provide MOSFET like high drive currents at low operating Vcc while providing the sub-kT/q steep switching slope[1,4,5]. However, the device design demands extremely scaled EOT and ultra-thin body double-gate geometry in order to achieve the desired transistor performance [4]. In this paper, we discuss a vertical TFET fabrication process with self-aligned gate [6] which can ultimately lead to the ultra-thin double-gate device geometry in order to achieve the desired TFET performance.
{"title":"Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor","authors":"D. Mohata, R. Bijesh, V. Saripalli, T. Mayer, S. Datta","doi":"10.1109/DRC.2011.5994498","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994498","url":null,"abstract":"Tunnel field effect transistors (TFET) have gained interest recently owing to their potential in achieving sub-kT/q steep switching slope, thus promising low Vcc operation[1–5]. Steep switching slope has already been demonstrated in Silicon TFET [2]. However, it has been theoretically shown and experimentally proved that Si or SixGe1−x based homo-junction or hetero-junction TFETs would not meet the drive current requirement for future low power high performance logic applications [3]. III–V based hetero-junction TFETs have shown promise to provide MOSFET like high drive currents at low operating Vcc while providing the sub-kT/q steep switching slope[1,4,5]. However, the device design demands extremely scaled EOT and ultra-thin body double-gate geometry in order to achieve the desired transistor performance [4]. In this paper, we discuss a vertical TFET fabrication process with self-aligned gate [6] which can ultimately lead to the ultra-thin double-gate device geometry in order to achieve the desired TFET performance.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114959543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994425
Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi
Germanium nanowires (GeNWs) of the group IV semiconductors could be one of the attractive candidates for electron-spin based quantum devices because of their long electron-spin coherence time. Besides, Ge has an advantage over Si in terms of the larger quantum effects due to the smaller effective mass. Single-electron transistors (SETs) are basic building blocks of such devices. To define the spin configuration in the dot, it is necessary to reach a few-electron regime or an even-odd regime where the single spin is realized for the odd number of electrons in the dot. So far, we have developed processes to fabricate SETs using n-type monocrystalline GeNWs with a back gate, and succeeded in observing the even-odd effect [1]. In this work, we have developed fabrication processes of the top-gate SETs to enhance the gating efficiency, and succeeded in reaching a few-electron regime.
{"title":"Top-gated single-electron transistor in germanium nanowires","authors":"Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi","doi":"10.1109/DRC.2011.5994425","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994425","url":null,"abstract":"Germanium nanowires (GeNWs) of the group IV semiconductors could be one of the attractive candidates for electron-spin based quantum devices because of their long electron-spin coherence time. Besides, Ge has an advantage over Si in terms of the larger quantum effects due to the smaller effective mass. Single-electron transistors (SETs) are basic building blocks of such devices. To define the spin configuration in the dot, it is necessary to reach a few-electron regime or an even-odd regime where the single spin is realized for the odd number of electrons in the dot. So far, we have developed processes to fabricate SETs using n-type monocrystalline GeNWs with a back gate, and succeeded in observing the even-odd effect [1]. In this work, we have developed fabrication processes of the top-gate SETs to enhance the gating efficiency, and succeeded in reaching a few-electron regime.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994518
D. Kalblein, B. Fenk, K. Hahn, U. Zschieschang, K. Kern, H. Klauk
Field-effect transistors (FETs) based on semiconducting nanowires are potentially useful to replace thin-film transistors (TFTs) in active-matrix displays, since the larger mobility and smaller footprint of nanowire FETs compared with a-Si:H and organic TFTs provide faster pixel charging and larger aperture ratio. Nanowire growth often requires high temperatures, but if the nanowires can be grown on a temperature-compatible substrate and then be transferred to the target substrate for FET fabrication, and if the temperature during FET fabrication is below ∼150 °C, nanoscale FETs can be fabricated on polymeric substrates for flexible displays.
{"title":"Aluminum top-gate ZnO nanowire transistors with improved transconductance","authors":"D. Kalblein, B. Fenk, K. Hahn, U. Zschieschang, K. Kern, H. Klauk","doi":"10.1109/DRC.2011.5994518","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994518","url":null,"abstract":"Field-effect transistors (FETs) based on semiconducting nanowires are potentially useful to replace thin-film transistors (TFTs) in active-matrix displays, since the larger mobility and smaller footprint of nanowire FETs compared with a-Si:H and organic TFTs provide faster pixel charging and larger aperture ratio. Nanowire growth often requires high temperatures, but if the nanowires can be grown on a temperature-compatible substrate and then be transferred to the target substrate for FET fabrication, and if the temperature during FET fabrication is below ∼150 °C, nanoscale FETs can be fabricated on polymeric substrates for flexible displays.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132628908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994441
A. Ajoy, K. Murali, S. Karmalkar, S. Laux
Over the last decade, Si1−xGex has increasingly been used as a channel material in MOSFETs. Though many studies have dealt with the real bandstructure of Si1−xGex, the effect of germanium mole fraction x on complex bandstructure has been unexplored. Complex bands fundamentally determine band to band tunneling (BTBT) current. For example, using the orientation dependent complex bandstructure of silicon [1], it has been shown [2] that the BTBT current in the [110] direction is an order of magnitude larger than that along the [100] direction. BTBT contributes significantly to off-current Ioff in conventional MOSFETs, via the mechanism of gate induced drain leakage (GIDL). Additionally, BTBT determines the on current Ion in tunneling FETs, which have been suggested as next generation devices. Further, BTBT is more dominant in Si1−xGex than silicon, owing to a narrower bandgap. In this work, we determine the orientation dependent complex bandstructure of Si1−xGex along common crystallographic directions and predict trends in BTBT current.
{"title":"Orientation dependent complex bandstructure of Si1−xGex alloys","authors":"A. Ajoy, K. Murali, S. Karmalkar, S. Laux","doi":"10.1109/DRC.2011.5994441","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994441","url":null,"abstract":"Over the last decade, Si<inf>1−x</inf>Ge<inf>x</inf> has increasingly been used as a channel material in MOSFETs. Though many studies have dealt with the real bandstructure of Si<inf>1−x</inf>Ge<inf>x</inf>, the effect of germanium mole fraction x on complex bandstructure has been unexplored. Complex bands fundamentally determine band to band tunneling (BTBT) current. For example, using the orientation dependent complex bandstructure of silicon [1], it has been shown [2] that the BTBT current in the [110] direction is an order of magnitude larger than that along the [100] direction. BTBT contributes significantly to off-current I<inf>off</inf> in conventional MOSFETs, via the mechanism of gate induced drain leakage (GIDL). Additionally, BTBT determines the on current I<inf>on</inf> in tunneling FETs, which have been suggested as next generation devices. Further, BTBT is more dominant in Si<inf>1−x</inf>Ge<inf>x</inf> than silicon, owing to a narrower bandgap. In this work, we determine the orientation dependent complex bandstructure of Si<inf>1−x</inf>Ge<inf>x</inf> along common crystallographic directions and predict trends in BTBT current.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994506
F. Medjdoub, M. Zegaoui, D. Ducatteau, N. Rolland, P. Rolland
AlN/GaN heterostructure is an ideal candidate to push the limits of microwave GaN-based devices owing to the maximum theoretical spontaneous and piezoelectric difference between the epitaxial AlN barrier and the underlying GaN layer. If the tricky growth conditions of this binary can be controlled, AlN/GaN HEMTs promise breakthrough performances, superior to any other III-V nitride-based heterostructure [1]. In particular, this structure should allow the extension of the GaN-based frequency operation due to the possibility to significantly reduce the gate length while maintaining an appropriate gate-to-channel aspect ratio to mitigate short channel effects. However, gate leakage current remains a serious issue with such ultrathin barrier heterostructure and gate dielectrics that often leads to device instability are generally used to overcome this problem. Furthermore, there is an increasing interest in the growth of GaN-on-Si substrates because of its low cost, large size, good thermal conductivity and the potential for integration with Si-based devices. In this work, we developed a novel AlN/GaN HEMT technology on Si substrate. The highest GaN-on-Si drain current density as well as a record transconductance together with excellent RF performance have been achieved. Additionally, AlN/GaN HEMT power measurements at 18 GHz have been performed for the first time. These results show the outstanding potential of this structure to extend GaN-on-Si performances to millimeter wave applications.
{"title":"First AlN/GaN HEMTs power measurement at 18 GHz on Silicon substrate","authors":"F. Medjdoub, M. Zegaoui, D. Ducatteau, N. Rolland, P. Rolland","doi":"10.1109/DRC.2011.5994506","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994506","url":null,"abstract":"AlN/GaN heterostructure is an ideal candidate to push the limits of microwave GaN-based devices owing to the maximum theoretical spontaneous and piezoelectric difference between the epitaxial AlN barrier and the underlying GaN layer. If the tricky growth conditions of this binary can be controlled, AlN/GaN HEMTs promise breakthrough performances, superior to any other III-V nitride-based heterostructure [1]. In particular, this structure should allow the extension of the GaN-based frequency operation due to the possibility to significantly reduce the gate length while maintaining an appropriate gate-to-channel aspect ratio to mitigate short channel effects. However, gate leakage current remains a serious issue with such ultrathin barrier heterostructure and gate dielectrics that often leads to device instability are generally used to overcome this problem. Furthermore, there is an increasing interest in the growth of GaN-on-Si substrates because of its low cost, large size, good thermal conductivity and the potential for integration with Si-based devices. In this work, we developed a novel AlN/GaN HEMT technology on Si substrate. The highest GaN-on-Si drain current density as well as a record transconductance together with excellent RF performance have been achieved. Additionally, AlN/GaN HEMT power measurements at 18 GHz have been performed for the first time. These results show the outstanding potential of this structure to extend GaN-on-Si performances to millimeter wave applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129931935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994513
R. Bijesh, I. Ok, M. Baykan, C. Hobbs, P. Majhi, R. Jammy, S. Datta
Experimental and theoretical hole mobility study in uniaxially strained (110)<110> Si0.75Ge0.25 pFINFETs shows that alloy scattering contributes only a small fraction of the overall mobility at 300K but plays a bigger role limiting 77K hole mobility. Increasing the Ge content to 50% increases the strain level. However, the extent of strain relaxation depends on the length of the fin. Fig. 10 shows the measured and projected hole mobility for SiGe FINFETs with 25% and 50% Ge mole fraction. Higher strain induced reduction of effective mass compensates for the increased interface charge density, Dit, in SSGOI0.5 pFINFET and alloy disorder and results in 157% increase in the hole mobility observed at Ns=1×1013 cm−2 and T=300K. Fig. 11 benchmarks the hole mobility in SSGOI0.25 and SSGOI0.5 pFINFETs as a function of electrical oxide thickness (TOXE) and shows its advantage over relaxed Ge channel MOSFETs. However strain relaxation for shorter length fins need to be addressed using careful layout techniques. High mobility combined with excellent short channel behavior make these devices a promising candidate for future technology node.
{"title":"Hole mobility enhancement in uniaxially strained SiGe FINFETs: Analysis and prospects","authors":"R. Bijesh, I. Ok, M. Baykan, C. Hobbs, P. Majhi, R. Jammy, S. Datta","doi":"10.1109/DRC.2011.5994513","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994513","url":null,"abstract":"Experimental and theoretical hole mobility study in uniaxially strained (110)<110> Si0.75Ge0.25 pFINFETs shows that alloy scattering contributes only a small fraction of the overall mobility at 300K but plays a bigger role limiting 77K hole mobility. Increasing the Ge content to 50% increases the strain level. However, the extent of strain relaxation depends on the length of the fin. Fig. 10 shows the measured and projected hole mobility for SiGe FINFETs with 25% and 50% Ge mole fraction. Higher strain induced reduction of effective mass compensates for the increased interface charge density, Dit, in SSGOI0.5 pFINFET and alloy disorder and results in 157% increase in the hole mobility observed at Ns=1×1013 cm−2 and T=300K. Fig. 11 benchmarks the hole mobility in SSGOI0.25 and SSGOI0.5 pFINFETs as a function of electrical oxide thickness (TOXE) and shows its advantage over relaxed Ge channel MOSFETs. However strain relaxation for shorter length fins need to be addressed using careful layout techniques. High mobility combined with excellent short channel behavior make these devices a promising candidate for future technology node.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994417
Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, S. Cai, K. J. Chen
Devices with steep subthreshold swing (SS) are of great interest and significance in view of increasing subthreshold leakage current with the continuous MOSFET scaling. The standby power dissipation has grown due to the nonscalability of the SS to below 60 mV/dec at room temperature (RT). To circumvent this obstacle, novel devices that employ various turn-on mechanisms have been proposed1–4. In this work, we report the observation of steep SS∼20 mV/dec in Schottky source/drain (SSD) Al2O3/InAlN/GaN MIS-HEMTs over a drain bias range of 0.1 to 5 V. The devices also feature high ION/IOFF ratio (∼109) and appreciable current drive of IDmax=230 mA/mm at room temperature. The devices are also characterized at elevated temperature (T) up to 155 °C. Steep SS lower than the theoretical diffusion limit is consistently observed over the testing temperature range. It is suggested that the steep switching behavior is obtained through the means of a dynamic de-trapping process at the Al2O3/InAlN interface. The dynamic de-trapping enables a dynamic negative shift in the threshold voltage during the gate upswing and effectively facilitates the formation of a sub-threshold swing as steep as 18 mV/dec.
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