Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129112
A. Tallarico, S. Reggiani, R. Depetro, G. Croce, E. Sangiorgi, C. Fiegna
Degradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization.
{"title":"Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors","authors":"A. Tallarico, S. Reggiani, R. Depetro, G. Croce, E. Sangiorgi, C. Fiegna","doi":"10.1109/IRPS45951.2020.9129112","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129112","url":null,"abstract":"Degradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114665735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128795
M. Hsieh, W. S. Chiang, Harry I. A. Chen, M. Z. Lin, M. J. Lin
In this paper, we demonstrated a robust design, test and screen methodology to achieve the high quality and reliability demand for automotive products. In design phase, a comprehensive aging signoff flow is proposed. By thorough consideration of device aging behavior, thermal distribution and process variation, design for reliability can be implemented through the well control of aging margin. The product with aging signoff has 75mV improvement in end-of-life guard band. To meet automotive product DPPM expectation, two approaches are exercised for DPPM reduction. 1) System-level test (SLT) is introduced for improving test coverage. By exercising the IC of a system as an integrated whole for its intended end-use application, the marginal defects which escapes from function test (FT) can be detected. Result shows over 100 DPPM could be screened out. 2) An early failure rate (EFR) estimation strategy by 3 steps dynamic voltage stress (DVS) is proposed. It enables screen condition determination for achieving DPPM target.
{"title":"Comprehensive Quality and Reliability Management for Automotive Product","authors":"M. Hsieh, W. S. Chiang, Harry I. A. Chen, M. Z. Lin, M. J. Lin","doi":"10.1109/IRPS45951.2020.9128795","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128795","url":null,"abstract":"In this paper, we demonstrated a robust design, test and screen methodology to achieve the high quality and reliability demand for automotive products. In design phase, a comprehensive aging signoff flow is proposed. By thorough consideration of device aging behavior, thermal distribution and process variation, design for reliability can be implemented through the well control of aging margin. The product with aging signoff has 75mV improvement in end-of-life guard band. To meet automotive product DPPM expectation, two approaches are exercised for DPPM reduction. 1) System-level test (SLT) is introduced for improving test coverage. By exercising the IC of a system as an integrated whole for its intended end-use application, the marginal defects which escapes from function test (FT) can be detected. Result shows over 100 DPPM could be screened out. 2) An early failure rate (EFR) estimation strategy by 3 steps dynamic voltage stress (DVS) is proposed. It enables screen condition determination for achieving DPPM target.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126239872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128866
Andreas Martin, A. Kamp
Plasma induced charging damage of MOS transistors originating from well charging (triple well or deep n-well configuration) is investigated for two different technologies. It is shown that the degradation on MOS transistors can impact the reliability of a product in comparison to earlier published data where a yield loss characteristic was reported on the basis of initially high MOS gate oxide leakage currents. For the first time a drift in MOS threshold voltage was recorded associated with well charging. Experimental data from this work and earlier published well charging results describe the same failure mechanism, but degradation characteristics are different, hence indicating the relevance of appropriate reliability investigations to ensure a robust product design according to the design for reliability strategy. It is demonstrated that a reliability stress on adequate product-relevant test structures is required for a necessary well charging assessment.A suitable protection method against well charging is described and implemented into a newly formulated well charging design rule which is practicable enough for implementation in electronic design automation tools. However a design rule checker for well charging requires a different concept than one for commonly known plasma induced charging on MOS gate electrodes.
{"title":"A New Implementation Approach for Reliability Design Rules against Plasma Induced Charging Damage from Well Configurations of Complex ICs","authors":"Andreas Martin, A. Kamp","doi":"10.1109/IRPS45951.2020.9128866","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128866","url":null,"abstract":"Plasma induced charging damage of MOS transistors originating from well charging (triple well or deep n-well configuration) is investigated for two different technologies. It is shown that the degradation on MOS transistors can impact the reliability of a product in comparison to earlier published data where a yield loss characteristic was reported on the basis of initially high MOS gate oxide leakage currents. For the first time a drift in MOS threshold voltage was recorded associated with well charging. Experimental data from this work and earlier published well charging results describe the same failure mechanism, but degradation characteristics are different, hence indicating the relevance of appropriate reliability investigations to ensure a robust product design according to the design for reliability strategy. It is demonstrated that a reliability stress on adequate product-relevant test structures is required for a necessary well charging assessment.A suitable protection method against well charging is described and implemented into a newly formulated well charging design rule which is practicable enough for implementation in electronic design automation tools. However a design rule checker for well charging requires a different concept than one for commonly known plasma induced charging on MOS gate electrodes.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125859123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129644
T. Uemura, Byungjin Chung, J. Jo, Hai Jiang, Yongsung Ji, T. Jeong, R. Ranjan, Youngin Park, K. Hong, Seungbae Lee, H. Rhee, S. Pae, Euncheol Lee, Jaehee Choi, Shotaro Ohnishi, Ken Machida
This paper investigates soft error in memories and logic circuits in 28 nm planar-FDSOI technology by neutron, alpha, proton, and gamma-ray irradiation tests, and compares with SER in bulk-FinFET. The comparison elucidates the different SER trends between planar-FDSOI and bulk-FinFET.
{"title":"Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET","authors":"T. Uemura, Byungjin Chung, J. Jo, Hai Jiang, Yongsung Ji, T. Jeong, R. Ranjan, Youngin Park, K. Hong, Seungbae Lee, H. Rhee, S. Pae, Euncheol Lee, Jaehee Choi, Shotaro Ohnishi, Ken Machida","doi":"10.1109/IRPS45951.2020.9129644","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129644","url":null,"abstract":"This paper investigates soft error in memories and logic circuits in 28 nm planar-FDSOI technology by neutron, alpha, proton, and gamma-ray irradiation tests, and compares with SER in bulk-FinFET. The comparison elucidates the different SER trends between planar-FDSOI and bulk-FinFET.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128325
D. Maldonado, J. Roldán, A. Roldán, F. Jiménez-Molinos, F. Hui, Y. Shi, X. Jing, Chao Wen, M. Lanza
Here we present a characterization study of Au/hBN/Au/Ti memristors when exposed to controlled magnetic field (MF) perpendicular to the device main vertical axis. The main switching parameters, i.e. set and reset voltages and currents, have been extracted and the influence of the MF on them (and on the resistive switching operation) has been analyzed. We observed that the set voltage values decrease with the MF, also the variability linked to the reset voltage is reduced. A similar effect is seen on the reset current, which shows a decrease due to the MF presence. These effects are linked to the reduction of the effective conductive filament section due to the influence of Lorentz force on the current lines.
{"title":"Influence of the magnetic field on dielectric breakdown in memristors based on h-BN stacks","authors":"D. Maldonado, J. Roldán, A. Roldán, F. Jiménez-Molinos, F. Hui, Y. Shi, X. Jing, Chao Wen, M. Lanza","doi":"10.1109/IRPS45951.2020.9128325","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128325","url":null,"abstract":"Here we present a characterization study of Au/hBN/Au/Ti memristors when exposed to controlled magnetic field (MF) perpendicular to the device main vertical axis. The main switching parameters, i.e. set and reset voltages and currents, have been extracted and the influence of the MF on them (and on the resistive switching operation) has been analyzed. We observed that the set voltage values decrease with the MF, also the variability linked to the reset voltage is reduced. A similar effect is seen on the reset current, which shows a decrease due to the MF presence. These effects are linked to the reduction of the effective conductive filament section due to the influence of Lorentz force on the current lines.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129351
Subrat Mishra, P. Weckx, Ji-Yung Lin, B. Kaczer, D. Linten, A. Spessot, F. Catthoor
A common approach to incorporate workload dependent aging in circuits is to use an effective stress time or so-called signal probability (SP) to calculate degradation under realistic workload scenarios. However, this approach is not fully physics-based and incurs erroneous estimation of degradation. Moreover, cycle-accurate (CA) simulations are computationally expensive. In this paper, a relatively fast yet accurate, adaptive waveform splitting (AWS) algorithm is proposed to enable fast calculation of workload-dependent device aging. The proposed algorithm has been adopted to perform aging estimation of large circuits under specific workload scenarios.
{"title":"Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS)","authors":"Subrat Mishra, P. Weckx, Ji-Yung Lin, B. Kaczer, D. Linten, A. Spessot, F. Catthoor","doi":"10.1109/IRPS45951.2020.9129351","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129351","url":null,"abstract":"A common approach to incorporate workload dependent aging in circuits is to use an effective stress time or so-called signal probability (SP) to calculate degradation under realistic workload scenarios. However, this approach is not fully physics-based and incurs erroneous estimation of degradation. Moreover, cycle-accurate (CA) simulations are computationally expensive. In this paper, a relatively fast yet accurate, adaptive waveform splitting (AWS) algorithm is proposed to enable fast calculation of workload-dependent device aging. The proposed algorithm has been adopted to perform aging estimation of large circuits under specific workload scenarios.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/irps45951.2020.9128312
Cheyun Lin, U. Avci, M. Blount, R. Grover, Jeffery Hicks, R. Kasim, A. Kundu, C. Pelto, C. Ryder, A. Schmitz, K. Sethi, D. Seghete, D. Towner, A. Welsh, J. Weber, C. Auth
We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO2-Al2O3 and HfO2-ZrO2 high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm2 and 52 fF/μm2 that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO2-ZrO2 capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm2 with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.
{"title":"Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process","authors":"Cheyun Lin, U. Avci, M. Blount, R. Grover, Jeffery Hicks, R. Kasim, A. Kundu, C. Pelto, C. Ryder, A. Schmitz, K. Sethi, D. Seghete, D. Towner, A. Welsh, J. Weber, C. Auth","doi":"10.1109/irps45951.2020.9128312","DOIUrl":"https://doi.org/10.1109/irps45951.2020.9128312","url":null,"abstract":"We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO<inf>2</inf>-Al<inf>2</inf>O<inf>3</inf> and HfO<inf>2</inf>-ZrO<inf>2</inf> high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm<sup>2</sup> and 52 fF/μm<sup>2</sup> that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO<inf>2</inf>-ZrO<inf>2</inf> capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm<sup>2</sup> with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127297343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128310
N. Choudhury, Uma Sharma, Huimei Zhou, R. Southwick, Miaomiao Wang, S. Mahapatra
An ultrafast (10ps delay) characterization method is used to measure threshold voltage shift (ΔVT) owing to Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) stress in N and P channel Gate All Around (GAA) NSFETs. ΔVT time kinetics at various gate bias (VG) and temperature (T) for BTI and at various VG and drain bias (VD) for HCD is analyzed. Contribution from Self Heat Effect (SHE) induced BTI to overall HCD is estimated under full VG/VD space and pure HCD contribution is determined.
{"title":"Analysis of BTI, SHE Induced BTI and HCD Under Full VG/VD Space in GAA Nano-Sheet N and P FETs","authors":"N. Choudhury, Uma Sharma, Huimei Zhou, R. Southwick, Miaomiao Wang, S. Mahapatra","doi":"10.1109/IRPS45951.2020.9128310","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128310","url":null,"abstract":"An ultrafast (10ps delay) characterization method is used to measure threshold voltage shift (ΔV<inf>T</inf>) owing to Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) stress in N and P channel Gate All Around (GAA) NSFETs. ΔV<inf>T</inf> time kinetics at various gate bias (V<inf>G</inf>) and temperature (T) for BTI and at various VG and drain bias (V<inf>D</inf>) for HCD is analyzed. Contribution from Self Heat Effect (SHE) induced BTI to overall HCD is estimated under full V<inf>G</inf>/V<inf>D</inf> space and pure HCD contribution is determined.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129216
C. Lo, T. Yeh, Wei-Chen Chen, H. Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu
In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest voltage (>30V) during NAND Flash programming [1]-[2]. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BVDSS) from virgin state is usually lower than that after stress, which is called the "walk-out" effect [3]-[4]. The walk-out effect can be recovered by a high-temperature baking, indicating it’s not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect [5]-[6]. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BVDSS with acceptable transistor performances.
{"title":"Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution","authors":"C. Lo, T. Yeh, Wei-Chen Chen, H. Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu","doi":"10.1109/IRPS45951.2020.9129216","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129216","url":null,"abstract":"In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest voltage (>30V) during NAND Flash programming [1]-[2]. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BVDSS) from virgin state is usually lower than that after stress, which is called the \"walk-out\" effect [3]-[4]. The walk-out effect can be recovered by a high-temperature baking, indicating it’s not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect [5]-[6]. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BVDSS with acceptable transistor performances.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126438524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128343
T. Zanotti, F. Puglisi, P. Pavan
The Logic-in-Memory paradigm is considered a promising solution for improving the energy efficiency and computing power of architectures aimed at low power and/or data-intensive applications. Among in-memory computing enabling technologies, emerging non-volatile memories (e.g., RRAMs) are promising as they offer BEOL integration and small feature size. Several studies have shown that IMPLY architectures based on RRAM devices and the material implication logic enable the efficient computation of logic operations using the RRAM device both as storing and computing element. However, RRAM devices non-idealities introduce important circuit reliability issues, that are frequently neglected, thus undermining the circuit functionality. In this work, we use a physics-based compact model calibrated on experimental data to simulate the IMPLY operation performed on a crossbar array including line parasitic effects and RRAM devices non-idealities. We then introduce a novel smart scheme, SIMPLY, and show the circuit reliability improvement.
{"title":"Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise","authors":"T. Zanotti, F. Puglisi, P. Pavan","doi":"10.1109/IRPS45951.2020.9128343","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128343","url":null,"abstract":"The Logic-in-Memory paradigm is considered a promising solution for improving the energy efficiency and computing power of architectures aimed at low power and/or data-intensive applications. Among in-memory computing enabling technologies, emerging non-volatile memories (e.g., RRAMs) are promising as they offer BEOL integration and small feature size. Several studies have shown that IMPLY architectures based on RRAM devices and the material implication logic enable the efficient computation of logic operations using the RRAM device both as storing and computing element. However, RRAM devices non-idealities introduce important circuit reliability issues, that are frequently neglected, thus undermining the circuit functionality. In this work, we use a physics-based compact model calibrated on experimental data to simulate the IMPLY operation performed on a crossbar array including line parasitic effects and RRAM devices non-idealities. We then introduce a novel smart scheme, SIMPLY, and show the circuit reliability improvement.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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