Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186196
A. Bass, T.T. Eyck
Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<>
输入/输出电路的设计，从真正的ECL电平转换到CMOS电平，而不带来负电源电压在芯片上讨论。仅使用+5 V和地消除了芯片上同时具有+5 V和-5 V引起的击穿和寄生MOSFET问题。这些电路为0.8 μ m BiCMOS门阵列提供ECL接口，并且比目前可用的其他转换器快得多。
{"title":"Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array","authors":"A. Bass, T.T. Eyck","doi":"10.1109/ASIC.1990.186196","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186196","url":null,"abstract":"Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"581 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186113
S. Glaser
The definition of very-high-speed integrated circuit (VHSIC) technology has changed over the last several years to encompass an entire system to IC design and manufacturing methodology supporting program lifecycle requirements. As the definition has changed, so has the source of VHSIC technology. It is no longer limited to the original VHSIC contractors. Some of the premier merchant ASIC suppliers have developed capabilities that address each of the VHSIC attributes, at a competitive cost and with superior service. The driving forces behind the changes in VHSIC, the requirements and applications of true VHSIC technology, and a dedicated military product line are described.<>
{"title":"'VHSIC' technology from a merchant ASIC supplier","authors":"S. Glaser","doi":"10.1109/ASIC.1990.186113","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186113","url":null,"abstract":"The definition of very-high-speed integrated circuit (VHSIC) technology has changed over the last several years to encompass an entire system to IC design and manufacturing methodology supporting program lifecycle requirements. As the definition has changed, so has the source of VHSIC technology. It is no longer limited to the original VHSIC contractors. Some of the premier merchant ASIC suppliers have developed capabilities that address each of the VHSIC attributes, at a competitive cost and with superior service. The driving forces behind the changes in VHSIC, the requirements and applications of true VHSIC technology, and a dedicated military product line are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186072
A. prophet
Three major forces at work in the ASIC markets are discussed: the increasing importance of foundries, the global regionalization of the ASIC markets, and the emerging role of multichip modules. It is pointed out that the economies of scale and comparative advantage will force the foundries to supply higher quality products, in near-state-of-the-art fabrication facilities with highly flexible processing. Moreover, the cost of these facilities is expected to rise rapidly, thus forcing the user to continue to use foundries instead of building fabrication facilities. It is also believed that the linkage between users and suppliers will shift away from the classical arm's length relationship to a partnership, where each party sees the other as an equal. The impact of regionalism on design and manufacture of ASICs and on the relationship of both processes to the ultimate user is considered. Multichip modules (MCMs) are a new wave in packaging technology consisting of a collection of multiple die mounted on a thin-film multilayer package. Some major applications of MCMs are identified.<>
{"title":"New rules, new markets, new skills: ASICS in the 90s","authors":"A. prophet","doi":"10.1109/ASIC.1990.186072","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186072","url":null,"abstract":"Three major forces at work in the ASIC markets are discussed: the increasing importance of foundries, the global regionalization of the ASIC markets, and the emerging role of multichip modules. It is pointed out that the economies of scale and comparative advantage will force the foundries to supply higher quality products, in near-state-of-the-art fabrication facilities with highly flexible processing. Moreover, the cost of these facilities is expected to rise rapidly, thus forcing the user to continue to use foundries instead of building fabrication facilities. It is also believed that the linkage between users and suppliers will shift away from the classical arm's length relationship to a partnership, where each party sees the other as an equal. The impact of regionalism on design and manufacture of ASICs and on the relationship of both processes to the ultimate user is considered. Multichip modules (MCMs) are a new wave in packaging technology consisting of a collection of multiple die mounted on a thin-film multilayer package. Some major applications of MCMs are identified.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186199
S. Tasker
The author describes how a multichip module (MCM) may be retargeted from one manufacturing technology to another during the physical layout. Some of the differences in manufacturing techniques of the MCM-C, MCM-L, and MCM-D and the effects that they have on the layout task are discussed. MCM-L uses a laminated circuit board process, MCM-C is a cofired ceramic process, and MCM-D is similar to an IC manufacturing process in which conductive material is deposited on to a silicon substrate. The system consists of both design and analysis tools. Automatic routing up to 48 signal layers and electrical analysis for reflections, crosstalk, and simple thermal analysis are described.<>
{"title":"Re-targetting manufacturing technologies in multichip module layout","authors":"S. Tasker","doi":"10.1109/ASIC.1990.186199","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186199","url":null,"abstract":"The author describes how a multichip module (MCM) may be retargeted from one manufacturing technology to another during the physical layout. Some of the differences in manufacturing techniques of the MCM-C, MCM-L, and MCM-D and the effects that they have on the layout task are discussed. MCM-L uses a laminated circuit board process, MCM-C is a cofired ceramic process, and MCM-D is similar to an IC manufacturing process in which conductive material is deposited on to a silicon substrate. The system consists of both design and analysis tools. Automatic routing up to 48 signal layers and electrical analysis for reflections, crosstalk, and simple thermal analysis are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133346895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186173
T.H. McFaul, K. Perrey
Maintaining accuracy during the rapid generation of a standard cell library is a problem in ASIC development. Errors can occur in all phases of library generation: design, characterization, modeling, and documentation. The integrated cell characterization system (iCCS), developed to automate the production of a standard cell library, is discussed. ICCS generates accurate models and documentation by simulating over a wider range of environmental conditions and removing human error.<>
{"title":"Characterizing a cell library using iCCS (ASIC design)","authors":"T.H. McFaul, K. Perrey","doi":"10.1109/ASIC.1990.186173","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186173","url":null,"abstract":"Maintaining accuracy during the rapid generation of a standard cell library is a problem in ASIC development. Errors can occur in all phases of library generation: design, characterization, modeling, and documentation. The integrated cell characterization system (iCCS), developed to automate the production of a standard cell library, is discussed. ICCS generates accurate models and documentation by simulating over a wider range of environmental conditions and removing human error.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186099
N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen
The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<>
{"title":"Superintegrated smart access controller","authors":"N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen","doi":"10.1109/ASIC.1990.186099","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186099","url":null,"abstract":"The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131310573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186090
G.K.D. Hu
A system that provides quick turnaround for ASIC feasibility evaluation and tradeoff for design, test, and manufacturability is described. During proposal or design phase, users can estimate ASIC size and performance for both new designs and technology migration, as the design architecture, system budget, user careabouts, ASIC technology, packaging, and other alternatives are selected.<>
{"title":"Quick turn around ASIC size estimation and tradeoff for new designs and technology migration using user driven careabouts","authors":"G.K.D. Hu","doi":"10.1109/ASIC.1990.186090","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186090","url":null,"abstract":"A system that provides quick turnaround for ASIC feasibility evaluation and tradeoff for design, test, and manufacturability is described. During proposal or design phase, users can estimate ASIC size and performance for both new designs and technology migration, as the design architecture, system budget, user careabouts, ASIC technology, packaging, and other alternatives are selected.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186123
Z. Navabi, J. Dube, A. Huang
Guidelines for the development of portable switch-level VHDL gate models that can be extracted from netlists or layout files are presented. Using these models, a simulation model for a cell-based design can be obtained. The VHDL descriptions of the gates will properly model timing and loading effects. Modeling techniques and procedures for assembling larger models are presented.<>
{"title":"Modeling strategy for post layout verification","authors":"Z. Navabi, J. Dube, A. Huang","doi":"10.1109/ASIC.1990.186123","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186123","url":null,"abstract":"Guidelines for the development of portable switch-level VHDL gate models that can be extracted from netlists or layout files are presented. Using these models, a simulation model for a cell-based design can be obtained. The VHDL descriptions of the gates will properly model timing and loading effects. Modeling techniques and procedures for assembling larger models are presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124931117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186098
E.J. Kramer, R. M. Lee
The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy reliance on a C model synthesizer, (2) behavioral modeling for design verification, (3) software generation of functional tests and automatic analysis of device operation, (4) BIST and other methods for improved fault coverage and, (5) effective use of the SUN workstation. Although some of these techniques are not new, how they were combined and applied was unusual. This resulted in significant design quality and schedule improvements.<>
{"title":"Putting it all together: using automated techniques for the design and test of large telecommunication devices","authors":"E.J. Kramer, R. M. Lee","doi":"10.1109/ASIC.1990.186098","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186098","url":null,"abstract":"The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy reliance on a C model synthesizer, (2) behavioral modeling for design verification, (3) software generation of functional tests and automatic analysis of device operation, (4) BIST and other methods for improved fault coverage and, (5) effective use of the SUN workstation. Although some of these techniques are not new, how they were combined and applied was unusual. This resulted in significant design quality and schedule improvements.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186079
O. Levia, R. Sullivan, J. Southard, R. McCann
Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesis process. Emphasis is placed on the input to the synthesis process (the design representation), the control a user has over the synthesis process, and how technology-specific information (library) is used in such a process. Examples from an existing logic synthesis system are used to clarify these points.<>
{"title":"Logic synthesis in a CAE design environment-a tutorial","authors":"O. Levia, R. Sullivan, J. Southard, R. McCann","doi":"10.1109/ASIC.1990.186079","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186079","url":null,"abstract":"Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesis process. Emphasis is placed on the input to the synthesis process (the design representation), the control a user has over the synthesis process, and how technology-specific information (library) is used in such a process. Examples from an existing logic synthesis system are used to clarify these points.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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