Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186173
T.H. McFaul, K. Perrey
Maintaining accuracy during the rapid generation of a standard cell library is a problem in ASIC development. Errors can occur in all phases of library generation: design, characterization, modeling, and documentation. The integrated cell characterization system (iCCS), developed to automate the production of a standard cell library, is discussed. ICCS generates accurate models and documentation by simulating over a wider range of environmental conditions and removing human error.<>
{"title":"Characterizing a cell library using iCCS (ASIC design)","authors":"T.H. McFaul, K. Perrey","doi":"10.1109/ASIC.1990.186173","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186173","url":null,"abstract":"Maintaining accuracy during the rapid generation of a standard cell library is a problem in ASIC development. Errors can occur in all phases of library generation: design, characterization, modeling, and documentation. The integrated cell characterization system (iCCS), developed to automate the production of a standard cell library, is discussed. ICCS generates accurate models and documentation by simulating over a wider range of environmental conditions and removing human error.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186164
P. Chatterjee, C. M. Brown, M. W. van der Kooi
A CAD system incorporating schematic capture, analog simulation, digital simulation, and layout utilizing a PC workstation platform is described. The single-layer metal programmable array consists of a CMOS logic core, an analog CMOS core, high-voltage DMOS FETs, bipolar devices, and interface devices. This combination of components and their applications presented various design constraints to incorporate into a single CAD system.<>
{"title":"A PC based CAD system for an analog/digital CMOS/DMOS/bipolar/smart power array","authors":"P. Chatterjee, C. M. Brown, M. W. van der Kooi","doi":"10.1109/ASIC.1990.186164","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186164","url":null,"abstract":"A CAD system incorporating schematic capture, analog simulation, digital simulation, and layout utilizing a PC workstation platform is described. The single-layer metal programmable array consists of a CMOS logic core, an analog CMOS core, high-voltage DMOS FETs, bipolar devices, and interface devices. This combination of components and their applications presented various design constraints to incorporate into a single CAD system.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126081022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186099
N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen
The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<>
{"title":"Superintegrated smart access controller","authors":"N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen","doi":"10.1109/ASIC.1990.186099","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186099","url":null,"abstract":"The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131310573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186151
Z. Ahmed, K. Rose
Increasingly, VLSI or ULSI designs involve the interconnection of complex macros to produce large-scale systems on a chip. The complexity of the macros and the lack of accessibility to the macros in a chip make efficient test methods essential. Existing ATPG programs flatten designs; this discards the testability information at the macro level. The extent to which macro specification can include testability information which will allow efficient generation of test patterns for assemblages of these macros is discussed. A method of constructing a graph model for a gate-level circuit is illustrated. The graph model can be used for test pattern generation. Experimental results on a set of benchmark circuits are presented. They demonstrate that an improvement in ATPG performance is achieved when the graph model is used instead of the flattened gate-level circuit.<>
{"title":"Hierarchical test generation for ASIC circuits using macro specification","authors":"Z. Ahmed, K. Rose","doi":"10.1109/ASIC.1990.186151","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186151","url":null,"abstract":"Increasingly, VLSI or ULSI designs involve the interconnection of complex macros to produce large-scale systems on a chip. The complexity of the macros and the lack of accessibility to the macros in a chip make efficient test methods essential. Existing ATPG programs flatten designs; this discards the testability information at the macro level. The extent to which macro specification can include testability information which will allow efficient generation of test patterns for assemblages of these macros is discussed. A method of constructing a graph model for a gate-level circuit is illustrated. The graph model can be used for test pattern generation. Experimental results on a set of benchmark circuits are presented. They demonstrate that an improvement in ATPG performance is achieved when the graph model is used instead of the flattened gate-level circuit.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186113
S. Glaser
The definition of very-high-speed integrated circuit (VHSIC) technology has changed over the last several years to encompass an entire system to IC design and manufacturing methodology supporting program lifecycle requirements. As the definition has changed, so has the source of VHSIC technology. It is no longer limited to the original VHSIC contractors. Some of the premier merchant ASIC suppliers have developed capabilities that address each of the VHSIC attributes, at a competitive cost and with superior service. The driving forces behind the changes in VHSIC, the requirements and applications of true VHSIC technology, and a dedicated military product line are described.<>
{"title":"'VHSIC' technology from a merchant ASIC supplier","authors":"S. Glaser","doi":"10.1109/ASIC.1990.186113","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186113","url":null,"abstract":"The definition of very-high-speed integrated circuit (VHSIC) technology has changed over the last several years to encompass an entire system to IC design and manufacturing methodology supporting program lifecycle requirements. As the definition has changed, so has the source of VHSIC technology. It is no longer limited to the original VHSIC contractors. Some of the premier merchant ASIC suppliers have developed capabilities that address each of the VHSIC attributes, at a competitive cost and with superior service. The driving forces behind the changes in VHSIC, the requirements and applications of true VHSIC technology, and a dedicated military product line are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186199
S. Tasker
The author describes how a multichip module (MCM) may be retargeted from one manufacturing technology to another during the physical layout. Some of the differences in manufacturing techniques of the MCM-C, MCM-L, and MCM-D and the effects that they have on the layout task are discussed. MCM-L uses a laminated circuit board process, MCM-C is a cofired ceramic process, and MCM-D is similar to an IC manufacturing process in which conductive material is deposited on to a silicon substrate. The system consists of both design and analysis tools. Automatic routing up to 48 signal layers and electrical analysis for reflections, crosstalk, and simple thermal analysis are described.<>
{"title":"Re-targetting manufacturing technologies in multichip module layout","authors":"S. Tasker","doi":"10.1109/ASIC.1990.186199","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186199","url":null,"abstract":"The author describes how a multichip module (MCM) may be retargeted from one manufacturing technology to another during the physical layout. Some of the differences in manufacturing techniques of the MCM-C, MCM-L, and MCM-D and the effects that they have on the layout task are discussed. MCM-L uses a laminated circuit board process, MCM-C is a cofired ceramic process, and MCM-D is similar to an IC manufacturing process in which conductive material is deposited on to a silicon substrate. The system consists of both design and analysis tools. Automatic routing up to 48 signal layers and electrical analysis for reflections, crosstalk, and simple thermal analysis are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133346895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186090
G.K.D. Hu
A system that provides quick turnaround for ASIC feasibility evaluation and tradeoff for design, test, and manufacturability is described. During proposal or design phase, users can estimate ASIC size and performance for both new designs and technology migration, as the design architecture, system budget, user careabouts, ASIC technology, packaging, and other alternatives are selected.<>
{"title":"Quick turn around ASIC size estimation and tradeoff for new designs and technology migration using user driven careabouts","authors":"G.K.D. Hu","doi":"10.1109/ASIC.1990.186090","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186090","url":null,"abstract":"A system that provides quick turnaround for ASIC feasibility evaluation and tradeoff for design, test, and manufacturability is described. During proposal or design phase, users can estimate ASIC size and performance for both new designs and technology migration, as the design architecture, system budget, user careabouts, ASIC technology, packaging, and other alternatives are selected.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186072
A. prophet
Three major forces at work in the ASIC markets are discussed: the increasing importance of foundries, the global regionalization of the ASIC markets, and the emerging role of multichip modules. It is pointed out that the economies of scale and comparative advantage will force the foundries to supply higher quality products, in near-state-of-the-art fabrication facilities with highly flexible processing. Moreover, the cost of these facilities is expected to rise rapidly, thus forcing the user to continue to use foundries instead of building fabrication facilities. It is also believed that the linkage between users and suppliers will shift away from the classical arm's length relationship to a partnership, where each party sees the other as an equal. The impact of regionalism on design and manufacture of ASICs and on the relationship of both processes to the ultimate user is considered. Multichip modules (MCMs) are a new wave in packaging technology consisting of a collection of multiple die mounted on a thin-film multilayer package. Some major applications of MCMs are identified.<>
{"title":"New rules, new markets, new skills: ASICS in the 90s","authors":"A. prophet","doi":"10.1109/ASIC.1990.186072","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186072","url":null,"abstract":"Three major forces at work in the ASIC markets are discussed: the increasing importance of foundries, the global regionalization of the ASIC markets, and the emerging role of multichip modules. It is pointed out that the economies of scale and comparative advantage will force the foundries to supply higher quality products, in near-state-of-the-art fabrication facilities with highly flexible processing. Moreover, the cost of these facilities is expected to rise rapidly, thus forcing the user to continue to use foundries instead of building fabrication facilities. It is also believed that the linkage between users and suppliers will shift away from the classical arm's length relationship to a partnership, where each party sees the other as an equal. The impact of regionalism on design and manufacture of ASICs and on the relationship of both processes to the ultimate user is considered. Multichip modules (MCMs) are a new wave in packaging technology consisting of a collection of multiple die mounted on a thin-film multilayer package. Some major applications of MCMs are identified.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186105
Y. Shibata, H. Funatsu, Y. Ishida, J. Yoshida
This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.<>
{"title":"A development system for an SRAM-based user-reprogrammable gate array","authors":"Y. Shibata, H. Funatsu, Y. Ishida, J. Yoshida","doi":"10.1109/ASIC.1990.186105","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186105","url":null,"abstract":"This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"30 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114050056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186179
R. Chrusciel
Some of the benefits of customer- and application-specific characterization of ASICs are discussed. The author discusses why ASIC device performance is characterized. An example of characterization data is presented for a CMOS gate array. The benefits of having this data are given. A cost analysis of using contract test engineering services to provide this data is presented.<>
{"title":"Characterization of ASIC performance via application specific test engineering","authors":"R. Chrusciel","doi":"10.1109/ASIC.1990.186179","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186179","url":null,"abstract":"Some of the benefits of customer- and application-specific characterization of ASICs are discussed. The author discusses why ASIC device performance is characterized. An example of characterization data is presented for a CMOS gate array. The benefits of having this data are given. A cost analysis of using contract test engineering services to provide this data is presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116000010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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