Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186073
C. Messenger
The task of device qualification becomes more arduous when the process is applied to application-specific integrated circuits (ASICs) where quick turn-around and low volumes are involved. These problems have been addressed by developing a process oriented system where the disciplines of design, fabrication, assembly, and test for a given technology are certified and qualified instead to individual devices. This approach, defined in MIL-I-38535 General Specifications for Integrated Circuits Manufacturing, is an outgrowth of the RADC Generic Qualification Program. Manufacturers who successfully complete the requirements will be listed on a qualified manufacturer's listing (QML) and all products built and tested on the QML flow will be qualified for use in military systems. The QML requirements address all types of integrated circuits. Issues of certifying testability/fault coverage capabilities, cell libraries, design and electrical rules, and design flow procedures are detailed. The concept is being expanded to encompass linear design, space-critical, and radiation-hardened requirements and GaAs fabrication, design, and test procedures.<>
{"title":"Qualified manufacturer's list (QML)-a new approach for qualifying ASICs","authors":"C. Messenger","doi":"10.1109/ASIC.1990.186073","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186073","url":null,"abstract":"The task of device qualification becomes more arduous when the process is applied to application-specific integrated circuits (ASICs) where quick turn-around and low volumes are involved. These problems have been addressed by developing a process oriented system where the disciplines of design, fabrication, assembly, and test for a given technology are certified and qualified instead to individual devices. This approach, defined in MIL-I-38535 General Specifications for Integrated Circuits Manufacturing, is an outgrowth of the RADC Generic Qualification Program. Manufacturers who successfully complete the requirements will be listed on a qualified manufacturer's listing (QML) and all products built and tested on the QML flow will be qualified for use in military systems. The QML requirements address all types of integrated circuits. Issues of certifying testability/fault coverage capabilities, cell libraries, design and electrical rules, and design flow procedures are detailed. The concept is being expanded to encompass linear design, space-critical, and radiation-hardened requirements and GaAs fabrication, design, and test procedures.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186148
G. O'Donoghue, M. Mallinson, P. Holloway
A MOSFET input amplifier with variable gain from 0 to 42 dB and fixed bandwidth at all closed-loop gains is described. Designed for a system where phase match at all gains is the dominant design goal, this amplifier adapts its open-loop gain crossover point to keep a constant closed-loop gain. This is done by controlling an active matrix of PMOS input devices which simultaneously achieves the constant phase characteristic and optimizes the noise and offset performance. Eight such amplifiers are implemented on a single chip with more than 100 dB of isolation between each amplifier and a power supply rejection ratio (PSRR) of more than 70 dB from 0 to 30 kHz.<>
{"title":"A novel programmable gain amplifier","authors":"G. O'Donoghue, M. Mallinson, P. Holloway","doi":"10.1109/ASIC.1990.186148","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186148","url":null,"abstract":"A MOSFET input amplifier with variable gain from 0 to 42 dB and fixed bandwidth at all closed-loop gains is described. Designed for a system where phase match at all gains is the dominant design goal, this amplifier adapts its open-loop gain crossover point to keep a constant closed-loop gain. This is done by controlling an active matrix of PMOS input devices which simultaneously achieves the constant phase characteristic and optimizes the noise and offset performance. Eight such amplifiers are implemented on a single chip with more than 100 dB of isolation between each amplifier and a power supply rejection ratio (PSRR) of more than 70 dB from 0 to 30 kHz.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186201
Z. Navabi, J. Spillane
Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification.<>
{"title":"Templates for synthesis from VHDL","authors":"Z. Navabi, J. Spillane","doi":"10.1109/ASIC.1990.186201","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186201","url":null,"abstract":"Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133983758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186115
E.H. Warshawsky
The nature of the problem confronting the armed services in their quest to gain control of the rapidly increasing costs associated with the proliferation of processors in military systems is identified and the cost impact associated with design, development, integration, and support of these processors is described. The two most powerful factors influencing contractor/designers selection of the optimal processors to fulfil their systems requirements are addressed, and the impact of emerging ASIC technology is identified. The system tools which could solve the problem of selection and rapid assessment of the suitability and relative worth of competing processor candidates in meeting mission requirements are described.<>
{"title":"ASIC technology and the selection of processors for DoD systems","authors":"E.H. Warshawsky","doi":"10.1109/ASIC.1990.186115","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186115","url":null,"abstract":"The nature of the problem confronting the armed services in their quest to gain control of the rapidly increasing costs associated with the proliferation of processors in military systems is identified and the cost impact associated with design, development, integration, and support of these processors is described. The two most powerful factors influencing contractor/designers selection of the optimal processors to fulfil their systems requirements are addressed, and the impact of emerging ASIC technology is identified. The system tools which could solve the problem of selection and rapid assessment of the suitability and relative worth of competing processor candidates in meeting mission requirements are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186146
B. Graindourze, H. Casier
SBIMOS tools for mixed analog/digital applications are discussed. This 40-V BiCMOS technology, together with the design system and the libraries, supports the integration of high-performance analog/digital in an ASIC at a low semicustom cost. This is illustrated by showing some standard cells followed by a compiled filter and an integrated circuit.<>
{"title":"Mixed analog/digital in a mixed bipolar/MOS technology","authors":"B. Graindourze, H. Casier","doi":"10.1109/ASIC.1990.186146","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186146","url":null,"abstract":"SBIMOS tools for mixed analog/digital applications are discussed. This 40-V BiCMOS technology, together with the design system and the libraries, supports the integration of high-performance analog/digital in an ASIC at a low semicustom cost. This is illustrated by showing some standard cells followed by a compiled filter and an integrated circuit.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121337844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186196
A. Bass, T.T. Eyck
Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<>
输入/输出电路的设计，从真正的ECL电平转换到CMOS电平，而不带来负电源电压在芯片上讨论。仅使用+5 V和地消除了芯片上同时具有+5 V和-5 V引起的击穿和寄生MOSFET问题。这些电路为0.8 μ m BiCMOS门阵列提供ECL接口，并且比目前可用的其他转换器快得多。
{"title":"Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array","authors":"A. Bass, T.T. Eyck","doi":"10.1109/ASIC.1990.186196","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186196","url":null,"abstract":"Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"581 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186143
P. Fasang
Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<>
{"title":"Simulation considerations for analog-digital ASICs","authors":"P. Fasang","doi":"10.1109/ASIC.1990.186143","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186143","url":null,"abstract":"Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116590483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186163
A. Gibbons, J. Tou
In order to succeed in the ASIC business, time to market for a new product is a high priority. To increase productivity and to decrease human error, a macro CAD system has been developed. The system is an integrated piece of software that consists of eight separate modules operating under a run-time system controller. A test vector set representing all possible input patterns is generated and simulated from both digital and analog standpoints. The results are compared to verify logic functionality and then used to extract critical timing parameters.<>
{"title":"A unified macro CAD system","authors":"A. Gibbons, J. Tou","doi":"10.1109/ASIC.1990.186163","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186163","url":null,"abstract":"In order to succeed in the ASIC business, time to market for a new product is a high priority. To increase productivity and to decrease human error, a macro CAD system has been developed. The system is an integrated piece of software that consists of eight separate modules operating under a run-time system controller. A test vector set representing all possible input patterns is generated and simulated from both digital and analog standpoints. The results are compared to verify logic functionality and then used to extract critical timing parameters.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122845097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186119
R.J. Hasslen, N. Zafar
ASIC in-circuit emulation technology for validation of embedded core ASICs in target systems is described. The emulation system contains an array of reprogrammable logic devices. Any ASIC vendor netlist can be accepted by the software. It is automatically partitioned, placed, and routed on the array of reprogrammable logic devices, called the emulation modules. The system creates a gate-by-gate, wire-by-wire replica of an ASIC design onto real hardware. In-circuit interface cables connect the functional image of the ASIC to the target system. This allows the designer to plug the ASIC design into the target system prior to having silicon built. The advantage is validation of the system design with full software and applications before actually committing to silicon. This makes design tradeoffs possible at an earlier stage. The built-in logic analyzer allows the designer to debug the ASIC design while running in-circuit, much like a microprocessor in-circuit emulator.<>
{"title":"A validation strategy for embedded core ASICs","authors":"R.J. Hasslen, N. Zafar","doi":"10.1109/ASIC.1990.186119","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186119","url":null,"abstract":"ASIC in-circuit emulation technology for validation of embedded core ASICs in target systems is described. The emulation system contains an array of reprogrammable logic devices. Any ASIC vendor netlist can be accepted by the software. It is automatically partitioned, placed, and routed on the array of reprogrammable logic devices, called the emulation modules. The system creates a gate-by-gate, wire-by-wire replica of an ASIC design onto real hardware. In-circuit interface cables connect the functional image of the ASIC to the target system. This allows the designer to plug the ASIC design into the target system prior to having silicon built. The advantage is validation of the system design with full software and applications before actually committing to silicon. This makes design tradeoffs possible at an earlier stage. The built-in logic analyzer allows the designer to debug the ASIC design while running in-circuit, much like a microprocessor in-circuit emulator.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186123
Z. Navabi, J. Dube, A. Huang
Guidelines for the development of portable switch-level VHDL gate models that can be extracted from netlists or layout files are presented. Using these models, a simulation model for a cell-based design can be obtained. The VHDL descriptions of the gates will properly model timing and loading effects. Modeling techniques and procedures for assembling larger models are presented.<>
{"title":"Modeling strategy for post layout verification","authors":"Z. Navabi, J. Dube, A. Huang","doi":"10.1109/ASIC.1990.186123","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186123","url":null,"abstract":"Guidelines for the development of portable switch-level VHDL gate models that can be extracted from netlists or layout files are presented. Using these models, a simulation model for a cell-based design can be obtained. The VHDL descriptions of the gates will properly model timing and loading effects. Modeling techniques and procedures for assembling larger models are presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124931117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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