Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186128
S.-L.L. Lu
It is pointed out that as complexity increases other methodologies beside the conventional approach to ASIC development should be considered. One approach available to ASIC designers is the silicon foundry service-the MOSIS service. This incremental approach has been practised by software engineers for many years. By adopting the same methodology, it may help ASIC development be more top-down and modular. It may also shorten the design cycle as well as reduce development cost.<>
{"title":"The incremental versus the conventional approach to ASIC development-why use MOSIS to develop ASIC?","authors":"S.-L.L. Lu","doi":"10.1109/ASIC.1990.186128","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186128","url":null,"abstract":"It is pointed out that as complexity increases other methodologies beside the conventional approach to ASIC development should be considered. One approach available to ASIC designers is the silicon foundry service-the MOSIS service. This incremental approach has been practised by software engineers for many years. By adopting the same methodology, it may help ASIC development be more top-down and modular. It may also shorten the design cycle as well as reduce development cost.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129421708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186174
W. Agatstein, K. McFaul, P. Themins
The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated.<>
{"title":"Validating an ASIC standard cell library","authors":"W. Agatstein, K. McFaul, P. Themins","doi":"10.1109/ASIC.1990.186174","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186174","url":null,"abstract":"The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129200831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186158
H. Tenhunen, T. Korpiharju
The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<>
{"title":"ASIC education at Tampere University of Technology","authors":"H. Tenhunen, T. Korpiharju","doi":"10.1109/ASIC.1990.186158","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186158","url":null,"abstract":"The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186156
D.M. Wu, J.W. Davis, N. Thoma
A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A high percentage of defects can be detected through the XOR gate designed for testing nonorthogonal faults.<>
{"title":"Design and test strategy for differential cascode voltage switch circuits","authors":"D.M. Wu, J.W. Davis, N. Thoma","doi":"10.1109/ASIC.1990.186156","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186156","url":null,"abstract":"A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A high percentage of defects can be detected through the XOR gate designed for testing nonorthogonal faults.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186155
C. Stroud, A. Barbour
Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<>
{"title":"Reliability, testability and yield of majority voting VLSI","authors":"C. Stroud, A. Barbour","doi":"10.1109/ASIC.1990.186155","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186155","url":null,"abstract":"Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186132
Tzyh-Yung Wuu, J. Pi, S.-L.L. Lu
A simple circuit specification language, NetList/sup +/, for rapid turn-around cell-based ASIC prototyping is discussed. By using NetList/sup +/, uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an easy interfacing method between design specification and independent CAD tools so that a simple description can be used for various tools.<>
{"title":"NetList/sup +/: a simple language for fast ASIC prototyping","authors":"Tzyh-Yung Wuu, J. Pi, S.-L.L. Lu","doi":"10.1109/ASIC.1990.186132","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186132","url":null,"abstract":"A simple circuit specification language, NetList/sup +/, for rapid turn-around cell-based ASIC prototyping is discussed. By using NetList/sup +/, uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an easy interfacing method between design specification and independent CAD tools so that a simple description can be used for various tools.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116423652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186160
H. Kanbara
KUE-CHIP (Kyoto University Education CHIP), an 8-bit microprocessor designed for LSI design courses at universities, is described. KUE-CHIP is useful for helping students understand how hardware operates in a microprocessor chip. KUE-CHIP was developed using commercial ASIC technology, It was found that KUE-CHIP was small scale and easily testable but had fundamental functions of commercial microprocessors.<>
{"title":"KUE-CHIP: a microprocessor for education of computer architecture and LSI design","authors":"H. Kanbara","doi":"10.1109/ASIC.1990.186160","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186160","url":null,"abstract":"KUE-CHIP (Kyoto University Education CHIP), an 8-bit microprocessor designed for LSI design courses at universities, is described. KUE-CHIP is useful for helping students understand how hardware operates in a microprocessor chip. KUE-CHIP was developed using commercial ASIC technology, It was found that KUE-CHIP was small scale and easily testable but had fundamental functions of commercial microprocessors.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186179
R. Chrusciel
Some of the benefits of customer- and application-specific characterization of ASICs are discussed. The author discusses why ASIC device performance is characterized. An example of characterization data is presented for a CMOS gate array. The benefits of having this data are given. A cost analysis of using contract test engineering services to provide this data is presented.<>
{"title":"Characterization of ASIC performance via application specific test engineering","authors":"R. Chrusciel","doi":"10.1109/ASIC.1990.186179","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186179","url":null,"abstract":"Some of the benefits of customer- and application-specific characterization of ASICs are discussed. The author discusses why ASIC device performance is characterized. An example of characterization data is presented for a CMOS gate array. The benefits of having this data are given. A cost analysis of using contract test engineering services to provide this data is presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116000010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186105
Y. Shibata, H. Funatsu, Y. Ishida, J. Yoshida
This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.<>
{"title":"A development system for an SRAM-based user-reprogrammable gate array","authors":"Y. Shibata, H. Funatsu, Y. Ishida, J. Yoshida","doi":"10.1109/ASIC.1990.186105","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186105","url":null,"abstract":"This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"30 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114050056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186078
R. Sparkes
Developments in the area of integrated circuit design methods and computer-aided design tools used in high-frequency (>100 MHz) bipolar arrays are discussed. The developments that occurred in digital integrated circuit design in the areas of simulation, modeling, critiquing, layout, verification, and testing are outlined. From this outline, the ways bipolar analog engineers adapted to these developments are discussed.<>
{"title":"An overview of the design methods and tools used in bipolar analog arrays","authors":"R. Sparkes","doi":"10.1109/ASIC.1990.186078","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186078","url":null,"abstract":"Developments in the area of integrated circuit design methods and computer-aided design tools used in high-frequency (>100 MHz) bipolar arrays are discussed. The developments that occurred in digital integrated circuit design in the areas of simulation, modeling, critiquing, layout, verification, and testing are outlined. From this outline, the ways bipolar analog engineers adapted to these developments are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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