Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186158
H. Tenhunen, T. Korpiharju
The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<>
{"title":"ASIC education at Tampere University of Technology","authors":"H. Tenhunen, T. Korpiharju","doi":"10.1109/ASIC.1990.186158","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186158","url":null,"abstract":"The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186132
Tzyh-Yung Wuu, J. Pi, S.-L.L. Lu
A simple circuit specification language, NetList/sup +/, for rapid turn-around cell-based ASIC prototyping is discussed. By using NetList/sup +/, uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an easy interfacing method between design specification and independent CAD tools so that a simple description can be used for various tools.<>
{"title":"NetList/sup +/: a simple language for fast ASIC prototyping","authors":"Tzyh-Yung Wuu, J. Pi, S.-L.L. Lu","doi":"10.1109/ASIC.1990.186132","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186132","url":null,"abstract":"A simple circuit specification language, NetList/sup +/, for rapid turn-around cell-based ASIC prototyping is discussed. By using NetList/sup +/, uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an easy interfacing method between design specification and independent CAD tools so that a simple description can be used for various tools.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116423652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186098
E.J. Kramer, R. M. Lee
The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy reliance on a C model synthesizer, (2) behavioral modeling for design verification, (3) software generation of functional tests and automatic analysis of device operation, (4) BIST and other methods for improved fault coverage and, (5) effective use of the SUN workstation. Although some of these techniques are not new, how they were combined and applied was unusual. This resulted in significant design quality and schedule improvements.<>
{"title":"Putting it all together: using automated techniques for the design and test of large telecommunication devices","authors":"E.J. Kramer, R. M. Lee","doi":"10.1109/ASIC.1990.186098","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186098","url":null,"abstract":"The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy reliance on a C model synthesizer, (2) behavioral modeling for design verification, (3) software generation of functional tests and automatic analysis of device operation, (4) BIST and other methods for improved fault coverage and, (5) effective use of the SUN workstation. Although some of these techniques are not new, how they were combined and applied was unusual. This resulted in significant design quality and schedule improvements.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186128
S.-L.L. Lu
It is pointed out that as complexity increases other methodologies beside the conventional approach to ASIC development should be considered. One approach available to ASIC designers is the silicon foundry service-the MOSIS service. This incremental approach has been practised by software engineers for many years. By adopting the same methodology, it may help ASIC development be more top-down and modular. It may also shorten the design cycle as well as reduce development cost.<>
{"title":"The incremental versus the conventional approach to ASIC development-why use MOSIS to develop ASIC?","authors":"S.-L.L. Lu","doi":"10.1109/ASIC.1990.186128","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186128","url":null,"abstract":"It is pointed out that as complexity increases other methodologies beside the conventional approach to ASIC development should be considered. One approach available to ASIC designers is the silicon foundry service-the MOSIS service. This incremental approach has been practised by software engineers for many years. By adopting the same methodology, it may help ASIC development be more top-down and modular. It may also shorten the design cycle as well as reduce development cost.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129421708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186160
H. Kanbara
KUE-CHIP (Kyoto University Education CHIP), an 8-bit microprocessor designed for LSI design courses at universities, is described. KUE-CHIP is useful for helping students understand how hardware operates in a microprocessor chip. KUE-CHIP was developed using commercial ASIC technology, It was found that KUE-CHIP was small scale and easily testable but had fundamental functions of commercial microprocessors.<>
{"title":"KUE-CHIP: a microprocessor for education of computer architecture and LSI design","authors":"H. Kanbara","doi":"10.1109/ASIC.1990.186160","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186160","url":null,"abstract":"KUE-CHIP (Kyoto University Education CHIP), an 8-bit microprocessor designed for LSI design courses at universities, is described. KUE-CHIP is useful for helping students understand how hardware operates in a microprocessor chip. KUE-CHIP was developed using commercial ASIC technology, It was found that KUE-CHIP was small scale and easily testable but had fundamental functions of commercial microprocessors.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186155
C. Stroud, A. Barbour
Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<>
{"title":"Reliability, testability and yield of majority voting VLSI","authors":"C. Stroud, A. Barbour","doi":"10.1109/ASIC.1990.186155","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186155","url":null,"abstract":"Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186079
O. Levia, R. Sullivan, J. Southard, R. McCann
Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesis process. Emphasis is placed on the input to the synthesis process (the design representation), the control a user has over the synthesis process, and how technology-specific information (library) is used in such a process. Examples from an existing logic synthesis system are used to clarify these points.<>
{"title":"Logic synthesis in a CAE design environment-a tutorial","authors":"O. Levia, R. Sullivan, J. Southard, R. McCann","doi":"10.1109/ASIC.1990.186079","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186079","url":null,"abstract":"Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesis process. Emphasis is placed on the input to the synthesis process (the design representation), the control a user has over the synthesis process, and how technology-specific information (library) is used in such a process. Examples from an existing logic synthesis system are used to clarify these points.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186156
D.M. Wu, J.W. Davis, N. Thoma
A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A high percentage of defects can be detected through the XOR gate designed for testing nonorthogonal faults.<>
{"title":"Design and test strategy for differential cascode voltage switch circuits","authors":"D.M. Wu, J.W. Davis, N. Thoma","doi":"10.1109/ASIC.1990.186156","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186156","url":null,"abstract":"A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A high percentage of defects can be detected through the XOR gate designed for testing nonorthogonal faults.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186174
W. Agatstein, K. McFaul, P. Themins
The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated.<>
{"title":"Validating an ASIC standard cell library","authors":"W. Agatstein, K. McFaul, P. Themins","doi":"10.1109/ASIC.1990.186174","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186174","url":null,"abstract":"The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129200831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186202
R. Puri, M. Hasan
A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<>
{"title":"PLASMA: a FSM design kernel","authors":"R. Puri, M. Hasan","doi":"10.1109/ASIC.1990.186202","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186202","url":null,"abstract":"A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121631485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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