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2006 Asia-Pacific Microwave Conference最新文献

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Embedding of short-open calibration technique in commercial MoM simulators for parameter extraction of planar integrated circuits 在商用MoM模拟器中嵌入短开式标定技术,用于平面集成电路参数提取
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429792
Liang Han, K. Wu, W. Hong, Lin Li, Xiaoping Chen
In this paper, the short-open calibration (SOC) technique, which was originally proposed, developed and self-contained in a research-oriented full-wave method of moments (MoM) simulator, is imbedded for the first time in a commercial simulator for the modeling and parameter extraction of planar integrated circuits and discontinuities. The SOC technique requires only two standards, namely short and open standards, which can be easily realized in commercial MoM simulators. By removing inherent numerical noise and errors, accurate equivalent circuit model of the circuits can be extracted and developed. Two examples are presented to verify the effectiveness of the proposed method in conjunction with a commercial package of choice.
本文首次将最初在研究型全波矩量法(MoM)模拟器中提出、发展并独立包含的短开式校准(SOC)技术嵌入到商用模拟器中,用于平面集成电路和不连续结构的建模和参数提取。SOC技术只需要两个标准,即短标准和开放标准,可以很容易地在商用MoM模拟器中实现。通过消除固有的数值噪声和误差,可以提取和推导出精确的等效电路模型。给出了两个例子来验证所提出的方法与所选择的商业软件包的有效性。
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引用次数: 7
A novel compact defected ground structure (DGS) low pass filter 一种新型紧凑缺陷接地结构(DGS)低通滤波器
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429623
A. Mohan, A. Biswas
This paper introduces new compact defected ground structure (DGS). The equivalent circuit parameters have been extracted using circuit analysis. The proposed DGS has smallest rectangular occupying area and it is 15.3% more compact than the previously reported structure in the literature. A novel low pass filter has been designed using the etched radial slot and the proposed DGS. The LPF have sharp rejection in the stop band.
介绍了一种新型致密缺陷地基结构(DGS)。利用电路分析方法提取了等效电路参数。所提出的DGS具有最小的矩形占用面积,比文献中先前报道的结构紧凑15.3%。利用蚀刻径向槽和所提出的DGS设计了一种新型低通滤波器。LPF在停止带有明显的抑制。
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引用次数: 1
Measurements of a compact surface wave launcher array with application to single frequency beam steering leaky wave antennas 应用于单频波束导向漏波天线的紧凑型表面波发射阵列的测量
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429541
A. Freundorfer, M. Bekheit, Y. Antar
Surface wave launchers have been used to feed leaky wave antennae. We present here for the first time measured results of a two element CPW-fed surface wave launcher array. It was shown at 22 GHz that this array can beam steer the surface wave 40deg. Array fabrication, measurement set-up and signal processing will also be described in the paper.
表面波发射器已经被用来给漏波天线供电。本文首次给出了一种双单元cpw馈电表面波发射阵列的测量结果。结果表明,在22ghz时,该阵列可以将表面波引导40度。本文还将介绍阵列的制作、测量设置和信号处理。
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引用次数: 4
Development of a pogo pin assembly and via design for multi-gigabit interfaces on automated test equipment 弹簧脚组件的开发和自动化测试设备上多千兆接口的设计
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429444
H. Barnes, J. Moreira, H. Ossoinig, M. Wollitzer, T. Schmid, Ming Tsai
I/O cells operating up to 10 Gb/s, are now becoming standard blocks in complex integrated circuits (ICs). Integration of these multiple I/O cells in conjunction with other cores (e.g. mixed-signal) and higher power requirements has increased the pin count for some devices to above one thousand pins. This presents tough challenges for the automated test equipment (ATE) industry, in terms of developing solutions to address the data rate and routing density. This paper demonstrates a novel approach for designing a high density Pogo pin transition to a multilayer planar PCB structure that achieves not only the required 10 Gb/s performance but also maintains the necessary density, and cost requirements that are inherent to an ATE solution.
运行速度高达10gb /s的I/O单元现在正在成为复杂集成电路(ic)的标准模块。将这些多个I/O单元与其他核心(例如混合信号)和更高的功率要求相结合,使某些设备的引脚数增加到1000个引脚以上。这对自动化测试设备(ATE)行业提出了严峻的挑战,需要开发解决方案来解决数据速率和路由密度问题。本文展示了一种设计高密度Pogo引脚过渡到多层平面PCB结构的新方法,该方法不仅实现了所需的10gb /s性能,而且保持了ATE解决方案固有的必要密度和成本要求。
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引用次数: 20
Single-stage, high efficiency, 26-watt power amplifier using SiC LE-MESFET 单级、高效率、26瓦功率放大器,采用SiC LE-MESFET
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429458
S. Azam, R. Jonsson, Q. Wahab
This paper describes a single-stage 26 W negative feedback power amplifier, covering the frequency range 200-500 MHz using a 6 mm gate width SiC lateral epitaxy MESFET. Typical results at 50 V drain bias for the whole band are, around 22 dB power gain, around 43 dBm output power, minimum power added efficiency at P1 dB is 47% at 200 MHz and maximum 60% at 500 MHz and the IMD3 level at 10 dB back-off from P1 dB is below -45 dBc. The results at 60 V drain bias at 500 MHz are, 24.9 dB power gain, 44.15 dBm output power (26 W) and 66% PAE.
本文介绍了一种单级26w负反馈功率放大器,使用6 mm门宽的SiC横向外延MESFET,覆盖200-500 MHz的频率范围。在50 V漏极偏置下,整个频段的典型结果是,功率增益约为22 dB,输出功率约为43 dBm, P1 dB的最小功率增加效率在200 MHz时为47%,在500 MHz时为60%,10 dB时的IMD3电平从P1 dB返回低于-45 dBc。结果表明,在500 MHz、60 V漏极偏置时,功率增益为24.9 dB,输出功率为44.15 dBm (26 W), PAE为66%。
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引用次数: 8
A low noise bulk-coupled colpitts CMOS quadrature VCO 一种低噪声体耦合CMOS正交压控振荡器
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429579
Yi-Hsien Cho, F. Chang, Ming-Fong Lei, Ming-Da Tsai, Hong-Yeh Chang, Huei Wang
This paper proposes a quadrature voltage-controlled oscillator (QVCO) using 0.18-mum 1P6M standard CMOS process. The QVCO is realized by combining two differential oscillators via the bulk terminals. Using this approach, we can reduce the power dissipation and remove the noise from the additional coupling transistors compared with conventional QVCOs. To improve the phase noise, the oscillator is composed of Colpitts topology for lower phase noise than its cross-coupled counterpart. Moreover, the Colpitts oscillator adopts only PMOS to achieve a better phase noise performance because PMOS has less 1/f noise than NMOS. The VCO operates from 4.9 to 5.5 GHz with more than 11% tuning range. The measured phase noise at 600-kHz offset is -117 dBc/Hz at 5.2 GHz. The QVCO dissipates 10.8 mW at 1.8 V and achieves a good FOM of 185 dB.
本文提出了一种采用0.18 μ m 1P6M标准CMOS工艺的正交压控振荡器(QVCO)。QVCO是由两个差分振荡器通过本体端子组合而成的。与传统的qvco相比,利用这种方法可以降低功耗并消除额外耦合晶体管带来的噪声。为了改善相位噪声,该振荡器采用Colpitts拓扑结构,相位噪声比交叉耦合振荡器低。此外,由于PMOS比NMOS具有更小的1/f噪声,因此Colpitts振荡器只采用PMOS以获得更好的相位噪声性能。VCO工作在4.9至5.5 GHz,调谐范围超过11%。在5.2 GHz时,测量到的600 khz偏置相位噪声为-117 dBc/Hz。QVCO在1.8 V时的功耗为10.8 mW, FOM为185 dB。
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引用次数: 16
Monolithic integration of microstrip line couplers for automotive radar applications at 77 GHz using a Si-HBT technology 采用Si-HBT技术的77 GHz汽车雷达应用微带线耦合器的单片集成
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429538
M. Hartmann, K. Seemann, H. Jager, E. Kolmhofer, R. Weigel
A branch-line, rat-race and a reduced-size branch-line coupler have been realized in a modern SiGe:C bipolar technology for application in automotive radar systems at 77 GHz. The paper describes the design methodology of passive circuits on lossy Si-based substrate up to 110 GHz and gives measurement results of the manufactured circuits.
采用现代SiGe:C双极技术,在77 GHz的汽车雷达系统中实现了分支线、老鼠赛跑和缩小尺寸的分支线耦合器。本文介绍了110 GHz有耗硅基衬底无源电路的设计方法,并给出了所制电路的测量结果。
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引用次数: 6
An ultra-low voltage UWB CMOS low noise amplifier 一种超低电压UWB CMOS低噪声放大器
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429429
Y. Yu, Y.‐J.E. Chen, D. Heo
This paper presents an ultra-low voltage UWB LNA in a commercial 0.18mum CMOS technology. The technique of inductive degeneration is used in a two-stage conventional distributed amplifier to achieve broadband and low noise. The common source single-stage amplifier is cascaded to the conventional distributed amplifier to improve the gain at high frequency. The measured gain of the integrated LNA is 10dB with the 3dB bandwidth from 2.7 to 9.1 GHz. The average noise figure is 4.65dB and the IIP3 is OdBm. Operated at 0.6V, the UWB CMOS LNA consumes 7mW.
本文提出了一种采用商用0.18 μ m CMOS技术的超低电压超宽带LNA。在两级传统分布式放大器中采用感应退化技术,实现了宽带和低噪声。为了提高高频增益,将共源单级放大器级联到传统的分布式放大器上。集成LNA的测量增益为10dB, 3dB带宽为2.7 ~ 9.1 GHz。平均噪声系数为4.65dB, IIP3为OdBm。工作电压为0.6V, UWB CMOS LNA功耗为7mW。
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引用次数: 10
Vibration modal analysis used finite element method of microwave amplitude equalizer 微波振幅均衡器的振动模态分析采用有限元法
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429619
Yang Mingshan, D. Xiaoyan, Z. Dewei, Niu Zhongxia
Based on the theory of vibration modal analysis, first 5 natural vibration frequencies and their mode shapes were calculated with ANSYS finite element analysis software. Their stress distributions of some modes, where cracks are formed easily to make microwave equalizer invalidation, were analyzed also. And, the reasons of phase noise, which influence the electric parameter characters of equalizer, induced by random vibration of the equalizer were explained.
基于振动模态分析理论,利用ANSYS有限元分析软件计算了前5个固有振动频率及其模态振型。分析了易产生裂纹使微波均衡器失效的几种模式的应力分布。分析了均衡器随机振动引起的相位噪声对均衡器电参数特性影响的原因。
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引用次数: 0
Low loss planar dielectric waveguide filter with cross coupling using LTCC technology at 60GHz band 采用LTCC技术的60GHz交叉耦合低损耗平面介质波导滤波器
Pub Date : 2006-12-01 DOI: 10.1109/APMC.2006.4429625
D. Jun, Hea Cheon Kim, Hyun-Kyu Yu
This paper proposes a filter with on transmission zero based on a combination of a vertically stacked and a horizontally arranged planar dielectric waveguide with cross coupling and low insertion loss were developed for 60 GHz band applications. The fabricated BPF exhibited one transmission zero at the higher frequency side of the pass band due to the post gap coupled waveguide. At the center operation frequency of 57.7 GHz, the 20 dB bandwidth of the BPF is 1.0 GHz, which is almost 2% of the center operation frequency, and the insertion loss is 1.12 dB. One transmission zero reach approximately 25 dB at 59.0 GHz. Unlike shifted frequency, demanded specifications were satisfied with the measured result.
本文提出了一种基于交叉耦合和低插入损耗的垂直堆叠和水平排列平面介质波导组合的无传输零滤波器,用于60 GHz频段。由于后隙耦合波导的存在,所制备的BPF在通频带的高频侧呈现出一个传输零。在中心工作频率为57.7 GHz时,BPF的20 dB带宽为1.0 GHz,几乎为中心工作频率的2%,插入损耗为1.12 dB。在59.0 GHz时,一次传输零达到约25 dB。与移频不同,测量结果满足要求的规格。
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引用次数: 1
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2006 Asia-Pacific Microwave Conference
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