Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532094
Y. J. Huang, S. Chung, H. Y. Lee, Y. S. Chen, F. Chen, P. Gu, M. Tsai
The voltage ramping rate during the forming and set-reset process is strongly related to the formation of soft-breakdown (SBD) paths. In this paper, we examined the effect of two different operation methods in RRAM, including sweep and pulse modes. The RTN analysis has been utilized to examine their influences on the SBD paths. For the first time, we found a different behavior of the RTN currents generated by two different modes of operation. Results show that more SBD paths are created during the pulse mode which led to the instability of switched resistance, and induced the erratic bit during the readout of RRAM.
{"title":"The physical insights into an abnormal erratic behavior in the resistance random access memory","authors":"Y. J. Huang, S. Chung, H. Y. Lee, Y. S. Chen, F. Chen, P. Gu, M. Tsai","doi":"10.1109/IRPS.2013.6532094","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532094","url":null,"abstract":"The voltage ramping rate during the forming and set-reset process is strongly related to the formation of soft-breakdown (SBD) paths. In this paper, we examined the effect of two different operation methods in RRAM, including sweep and pulse modes. The RTN analysis has been utilized to examine their influences on the SBD paths. For the first time, we found a different behavior of the RTN currents generated by two different modes of operation. Results show that more SBD paths are created during the pulse mode which led to the instability of switched resistance, and induced the erratic bit during the readout of RRAM.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127424523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532038
Y.-H. Huang, L. Leu, C. C. Liu, Y. Lee, J. Wang, A. Mehta, K. Wu, Hui-Ting Lu, P. Su, Jui-Ping Chiang, H. Chou, Y. Jong, H. Tuan
In this paper, we investigate hot carrier injection (HCI) stress induced self-heating behavior for high-voltage n-type Lateral-Diffused-MOSFET (NLDMOS) multi-finger devices. A NMOS device with more poly fingers, for the first time, is found to suffer more threshold voltage drift (ΔVt) but less linear current drift (ΔIdlin) under HCI stress at high gate and drain voltages. The experiment of monitoring device temperature is carried out and TCAD simulations are performed to investigate the physical mechanisms. The effect of poly gate finger numbers (PGFN) is attributed to higher lattice temperature with more PGFN, resulting in higher electrical field in the channel region and lower electrical field in the drift region. HCI behavior in ΔVt and ΔIdlin for different PGFN devices at various ambient temperatures are verified by TCAD simulation. In addition, the effect of PGFN on AC HCI stress and DC HCI Safe-Operation-Area (SOA) are studied. All the experimental findings can be well explained by the effect of self-heating during HCI stress mode.
{"title":"Investigation of self-heating induced hot-carrier-injection stress behavior in high-voltage power devices","authors":"Y.-H. Huang, L. Leu, C. C. Liu, Y. Lee, J. Wang, A. Mehta, K. Wu, Hui-Ting Lu, P. Su, Jui-Ping Chiang, H. Chou, Y. Jong, H. Tuan","doi":"10.1109/IRPS.2013.6532038","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532038","url":null,"abstract":"In this paper, we investigate hot carrier injection (HCI) stress induced self-heating behavior for high-voltage n-type Lateral-Diffused-MOSFET (NLDMOS) multi-finger devices. A NMOS device with more poly fingers, for the first time, is found to suffer more threshold voltage drift (ΔVt) but less linear current drift (ΔIdlin) under HCI stress at high gate and drain voltages. The experiment of monitoring device temperature is carried out and TCAD simulations are performed to investigate the physical mechanisms. The effect of poly gate finger numbers (PGFN) is attributed to higher lattice temperature with more PGFN, resulting in higher electrical field in the channel region and lower electrical field in the drift region. HCI behavior in ΔVt and ΔIdlin for different PGFN devices at various ambient temperatures are verified by TCAD simulation. In addition, the effect of PGFN on AC HCI stress and DC HCI Safe-Operation-Area (SOA) are studied. All the experimental findings can be well explained by the effect of self-heating during HCI stress mode.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127632755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531943
C. Ma, H. Mattausch, M. Miyake, T. Iizuka, M. Miura-Mattausch, K. Matsuzawa, S. Yamaguchi, T. Hoshida, M. Imade, R. Koh, T. Arakawa, J. He
A compact reliability model is reported, which includes both the channel hot carrier (CHC) and the negative bias thermal instability (NBTI) effects in p-MOSFETs. The developed compact NBTI model, which describes both interface-state generation and hole-trapping mechanisms, is further improved by considering additionally the impact of the drain bias Vds. With increased Vds, the NBTI effect is weakened due to the reduction of the vertical gate oxide field, and the CHC effect is enhanced by the increased lateral channel electric field. Therefore, the threshold voltage is observed to decrease in the low Vds regime, and then increases again in the high Vds regime. Such “turn-around” characteristic is correctly modeled using the improved compact NBTI model. Implementation of this reliability model into the surface-potential-based compact model HiSIM enables accurate prediction of the CHC enhanced NBTI degradation for wide ranges of time duration and bias conditions. This allows real-time simulation for the circuit-performance degradation occurring during actual circuit operation.
{"title":"Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation","authors":"C. Ma, H. Mattausch, M. Miyake, T. Iizuka, M. Miura-Mattausch, K. Matsuzawa, S. Yamaguchi, T. Hoshida, M. Imade, R. Koh, T. Arakawa, J. He","doi":"10.1109/IRPS.2013.6531943","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531943","url":null,"abstract":"A compact reliability model is reported, which includes both the channel hot carrier (CHC) and the negative bias thermal instability (NBTI) effects in p-MOSFETs. The developed compact NBTI model, which describes both interface-state generation and hole-trapping mechanisms, is further improved by considering additionally the impact of the drain bias Vds. With increased Vds, the NBTI effect is weakened due to the reduction of the vertical gate oxide field, and the CHC effect is enhanced by the increased lateral channel electric field. Therefore, the threshold voltage is observed to decrease in the low Vds regime, and then increases again in the high Vds regime. Such “turn-around” characteristic is correctly modeled using the improved compact NBTI model. Implementation of this reliability model into the surface-potential-based compact model HiSIM enables accurate prediction of the CHC enhanced NBTI degradation for wide ranges of time duration and bias conditions. This allows real-time simulation for the circuit-performance degradation occurring during actual circuit operation.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128147134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532009
P. Hacke, R. Smith, K. Terwilliger, S. Glick, D. Jordan, S. Johnston, M. Kempe, S. Kurtz
Potential-induced degradation in conventional p-type silicon-based photovoltaic solar cell modules is described as a failure mechanism involving positive ion migration, understood to be primarily Na+, drifting from the glass to the cells in negative-voltage arrays. Acceleration factors for this mechanism are determined for silicon photovoltaic modules by comparing the module power during degradation outdoors to that in accelerated testing at three temperatures and 85% relative humidity. A lognormal analysis is applied to the accelerated lifetime test data considering failure at 80% of the initial module power. Activation energy of 0.73 eV for the rate of failure is determined for the chamber testing at the constant relative humidity, and the probability of module failure at an arbitrary temperature is predicted. Estimation of module power in-situ in the environmental chamber is achieved using dark I-V measurements transformed by superposition. By this means, the power of the degrading module can be semi-continuously determined so that statistical data for multiple modules undergoing potential-induced degradation can be easily and accurately obtained.
{"title":"Acceleration factor determination for potential-induced degradation in crystalline silicon PV modules","authors":"P. Hacke, R. Smith, K. Terwilliger, S. Glick, D. Jordan, S. Johnston, M. Kempe, S. Kurtz","doi":"10.1109/IRPS.2013.6532009","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532009","url":null,"abstract":"Potential-induced degradation in conventional p-type silicon-based photovoltaic solar cell modules is described as a failure mechanism involving positive ion migration, understood to be primarily Na+, drifting from the glass to the cells in negative-voltage arrays. Acceleration factors for this mechanism are determined for silicon photovoltaic modules by comparing the module power during degradation outdoors to that in accelerated testing at three temperatures and 85% relative humidity. A lognormal analysis is applied to the accelerated lifetime test data considering failure at 80% of the initial module power. Activation energy of 0.73 eV for the rate of failure is determined for the chamber testing at the constant relative humidity, and the probability of module failure at an arbitrary temperature is predicted. Estimation of module power in-situ in the environmental chamber is achieved using dark I-V measurements transformed by superposition. By this means, the power of the degrading module can be semi-continuously determined so that statistical data for multiple modules undergoing potential-induced degradation can be easily and accurately obtained.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532081
Hu Wenke, Guo Fujun
Based on the analysis of field customer failure feedback data over years, it is found almost 50% of the chip failure in board-level is EOS (electrical over stress) issue. Hence it is very common chip failure mode. From board-level point of view, EOS can destroy a semiconductor chip in many ways, resulting in observable and different failure attributes. Thus it is really challenging to identify and find the root cause when it happens at board-level. Also, EOS burns up the chip, and can be caused by several additional factors at board level. It makes EOS event become more complex for investigation and analysis. In this paper, from several case studies, we can classify EOS issues are due to “chip undetectable weakness”, “board-level application” or “board environment” and summarized few conclusions for chip EOS issue.
{"title":"Chip EOS issue analysis in board-level application","authors":"Hu Wenke, Guo Fujun","doi":"10.1109/IRPS.2013.6532081","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532081","url":null,"abstract":"Based on the analysis of field customer failure feedback data over years, it is found almost 50% of the chip failure in board-level is EOS (electrical over stress) issue. Hence it is very common chip failure mode. From board-level point of view, EOS can destroy a semiconductor chip in many ways, resulting in observable and different failure attributes. Thus it is really challenging to identify and find the root cause when it happens at board-level. Also, EOS burns up the chip, and can be caused by several additional factors at board level. It makes EOS event become more complex for investigation and analysis. In this paper, from several case studies, we can classify EOS issues are due to “chip undetectable weakness”, “board-level application” or “board environment” and summarized few conclusions for chip EOS issue.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131280108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532005
W. Choi, P. Jain, C. Kim
An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.
{"title":"An array-based circuit for characterizing latent Plasma-Induced Damage","authors":"W. Choi, P. Jain, C. Kim","doi":"10.1109/IRPS.2013.6532005","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532005","url":null,"abstract":"An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125290512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532100
G. Navarro, A. Persico, E. Henaff, F. Aussenac, Pierre Noé, C. Jahan, L. Perniola, V. Sousa, E. Vianello, B. D. Salvo
We present for the first time, the effects of SiO2-doping in GeTe-based Phase-Change Memory (PCM) technology. We demonstrate a 50% RESET power reduction correlated with the enhanced thermal and electrical efficiency of the cell by SiO2-doping. Moreover we show the possibility to engineer the threshold voltage (VTH) of the cell at high operating temperature, thanks to the changed crystallization dynamics induced by SiO2 doping into GeTe.
{"title":"Electrical performances of SiO2-doped GeTe for phase-change memory applications","authors":"G. Navarro, A. Persico, E. Henaff, F. Aussenac, Pierre Noé, C. Jahan, L. Perniola, V. Sousa, E. Vianello, B. D. Salvo","doi":"10.1109/IRPS.2013.6532100","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532100","url":null,"abstract":"We present for the first time, the effects of SiO2-doping in GeTe-based Phase-Change Memory (PCM) technology. We demonstrate a 50% RESET power reduction correlated with the enhanced thermal and electrical efficiency of the cell by SiO2-doping. Moreover we show the possibility to engineer the threshold voltage (VTH) of the cell at high operating temperature, thanks to the changed crystallization dynamics induced by SiO2 doping into GeTe.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131840794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531977
C. Miccoli, J. Barber, C. M. Compagnoni, G. M. Paolucci, J. Kessenich, A. Lacaita, A. Spinelli, R. Koval, A. Goda
We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.
{"title":"Resolving discrete emission events: A new perspective for detrapping investigation in NAND Flash memories","authors":"C. Miccoli, J. Barber, C. M. Compagnoni, G. M. Paolucci, J. Kessenich, A. Lacaita, A. Spinelli, R. Koval, A. Goda","doi":"10.1109/IRPS.2013.6531977","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531977","url":null,"abstract":"We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131789876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532045
L. Liyanage, Xiangyu Chen, Hai Wei, Hong-Yu Chen, S. Mitra, H. Wong
Graphene and carbon nanotubes (CNTs) have gained significant attention due to their potential applications in high performance electronics. In order to replace or integrate the current silicon based technology with carbon based electronics one should study the reliability of those devices to understand the feasibility of their applications. In this report we present the reliability of CVD synthesized graphene for transistor interconnects and also investigate the reliability of a metal-oxide based CNT doping technique that is an active area of research in the current CNT community.
{"title":"Reliability of graphene interconnects and n-type doping of carbon nanotube transistors","authors":"L. Liyanage, Xiangyu Chen, Hai Wei, Hong-Yu Chen, S. Mitra, H. Wong","doi":"10.1109/IRPS.2013.6532045","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532045","url":null,"abstract":"Graphene and carbon nanotubes (CNTs) have gained significant attention due to their potential applications in high performance electronics. In order to replace or integrate the current silicon based technology with carbon based electronics one should study the reliability of those devices to understand the feasibility of their applications. In this report we present the reliability of CVD synthesized graphene for transistor interconnects and also investigate the reliability of a metal-oxide based CNT doping technique that is an active area of research in the current CNT community.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128367174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532080
Linjun Cao, P. Ho, P. Justison
Electromigration (EM) reliability of Cu interconnects for the 28 nm node with Mn doping was studied by investigating the effects of line width and length on void formation kinetics, EM lifetime and statistics. Failure modes and mass transport mechanism responsible for EM degradation of CuMn interconnects were examined. Although immortality was not observed, EM lifetime of short lines was significantly improved together with a reduction in lifetime deviation. This is attributed to the effectiveness of Mn in repairing process defects, particularly for via-related void formation in V1M2 electron flow direction.
{"title":"Electromigration reliability of Mn-doped Cu interconnects for the 28 nm technology","authors":"Linjun Cao, P. Ho, P. Justison","doi":"10.1109/IRPS.2013.6532080","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532080","url":null,"abstract":"Electromigration (EM) reliability of Cu interconnects for the 28 nm node with Mn doping was studied by investigating the effects of line width and length on void formation kinetics, EM lifetime and statistics. Failure modes and mass transport mechanism responsible for EM degradation of CuMn interconnects were examined. Although immortality was not observed, EM lifetime of short lines was significantly improved together with a reduction in lifetime deviation. This is attributed to the effectiveness of Mn in repairing process defects, particularly for via-related void formation in V1M2 electron flow direction.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131089471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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