Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532013
M. Takenaka, Rui Zhang, S. Takagi
In this paper, we have discussed the fundamental properties of the germanium oxides formed by thermal oxidation and plasma post-oxidation as interfacial layers for Ge MOSFETs. The germanium oxides form high-quality Ge MOS interface with interface trap density of around 1011 cm-2eV-1. High-mobility Ge n-MOSFETs and p-MOSFETs have successfully been demonstrated even with EOT of less than 0.8 nm, exhibiting that the germanium oxides are the most promising interfacial layers for future Ge CMOS.
{"title":"MOS interface engineering for high-mobility Ge CMOS","authors":"M. Takenaka, Rui Zhang, S. Takagi","doi":"10.1109/IRPS.2013.6532013","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532013","url":null,"abstract":"In this paper, we have discussed the fundamental properties of the germanium oxides formed by thermal oxidation and plasma post-oxidation as interfacial layers for Ge MOSFETs. The germanium oxides form high-quality Ge MOS interface with interface trap density of around 1011 cm-2eV-1. High-mobility Ge n-MOSFETs and p-MOSFETs have successfully been demonstrated even with EOT of less than 0.8 nm, exhibiting that the germanium oxides are the most promising interfacial layers for future Ge CMOS.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129422908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531970
T. Kauerauf, Anna Branka, Giuseppe Sorrentino, Philippe Roussel, Steven Demuynck, K. Croes, Karim Mercha, Jürgen Bömmels, T. Zsolt, kei, Guido Groeseneken, Imec Kapeldreef
From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.
{"title":"Reliability of MOL local interconnects","authors":"T. Kauerauf, Anna Branka, Giuseppe Sorrentino, Philippe Roussel, Steven Demuynck, K. Croes, Karim Mercha, Jürgen Bömmels, T. Zsolt, kei, Guido Groeseneken, Imec Kapeldreef","doi":"10.1109/IRPS.2013.6531970","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531970","url":null,"abstract":"From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133435421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532077
Ki-Don Lee
VIATOP (VT), Aluminum Via connecting the bond pad and the Top Copper level, is the critical component for Bond Pad (BP) Electromigration (EM) in advanced technology nodes, where a smaller VT or its array is employed for maximum chip-scaling. In this study, we evaluated BP EM using various dimensions of VT, investigated the scaling effect, and proposed a BP EM model for current crowding & reservoir effect in the VT.
{"title":"Electromigration in advanced Bond Pad structures","authors":"Ki-Don Lee","doi":"10.1109/IRPS.2013.6532077","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532077","url":null,"abstract":"VIATOP (VT), Aluminum Via connecting the bond pad and the Top Copper level, is the critical component for Bond Pad (BP) Electromigration (EM) in advanced technology nodes, where a smaller VT or its array is employed for maximum chip-scaling. In this study, we evaluated BP EM using various dimensions of VT, investigated the scaling effect, and proposed a BP EM model for current crowding & reservoir effect in the VT.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532048
F. Souchon, B. Reig, C. Dieppedale, L. Thouy, A. Koszewski, H. Sibuet, G. Papaioannou
Dielectric charging and contact degradations are the two major challenges to improve the lifetime of series ohmic electrostatic MEMS switches. This paper details our approach and our main results to overcome the failures due to dielectric charging. We introduce a time predictive model for charge accumulation that we use as a design tool for reliability. The key parameters are listed and a new switch design is proposed to reduce the charging: the dielectric materials between the actuation electrodes are removed as much as possible. This dielectric-free design gives remarkable results in terms of dielectric charging sensitivity: the pull-in voltage decreases a little bit at initial times, and remains steady for longer time. The second major challenge, that remains to be considered, deals with the contact reliability. For that purpose, gold and ruthenium contacts have been investigated under several operating conditions. Gold contacts give good results in cold switching conditions whereas ruthenium suffers from surface contamination which increases quickly the contact resistance. In hot switching conditions, both materials are sensitive to material transfer mechanism, the failure rate being proportional to the open circuit voltage. Nevertheless, ruthenium seems more resistant to a material transfer than gold, and offers performances acceptable for some specific applications. A hermetic packaging at wafer level should allow to improve the contact reliability thanks to an efficient management of the surface contamination issue.
{"title":"Key improvements of the MEMS switch lifetime thanks to a dielectric-free design and contact reliability investigations in hot/cold switching operations","authors":"F. Souchon, B. Reig, C. Dieppedale, L. Thouy, A. Koszewski, H. Sibuet, G. Papaioannou","doi":"10.1109/IRPS.2013.6532048","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532048","url":null,"abstract":"Dielectric charging and contact degradations are the two major challenges to improve the lifetime of series ohmic electrostatic MEMS switches. This paper details our approach and our main results to overcome the failures due to dielectric charging. We introduce a time predictive model for charge accumulation that we use as a design tool for reliability. The key parameters are listed and a new switch design is proposed to reduce the charging: the dielectric materials between the actuation electrodes are removed as much as possible. This dielectric-free design gives remarkable results in terms of dielectric charging sensitivity: the pull-in voltage decreases a little bit at initial times, and remains steady for longer time. The second major challenge, that remains to be considered, deals with the contact reliability. For that purpose, gold and ruthenium contacts have been investigated under several operating conditions. Gold contacts give good results in cold switching conditions whereas ruthenium suffers from surface contamination which increases quickly the contact resistance. In hot switching conditions, both materials are sensitive to material transfer mechanism, the failure rate being proportional to the open circuit voltage. Nevertheless, ruthenium seems more resistant to a material transfer than gold, and offers performances acceptable for some specific applications. A hermetic packaging at wafer level should allow to improve the contact reliability thanks to an efficient management of the surface contamination issue.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531982
K. Miyaji, D. Kobayashi, K. Takeuchi, S. Miyano
Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.
{"title":"Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor","authors":"K. Miyaji, D. Kobayashi, K. Takeuchi, S. Miyano","doi":"10.1109/IRPS.2013.6531982","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531982","url":null,"abstract":"Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128636029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532090
A. Cismaru, A. Muller, F. Comanescu, M. Purica, A. Stefanescu, A. Dinescu, G. Konstantinidis, A. Stavrinidis
The morphological analysis is targeted towards a better understanding of the reliability of GaN membranes obtained by micromachining of GaN/Si. These membranes are used as support for devices like FBARs or backside-illuminated UV photodetectors. The deflection analysis is performed on 0.4 μm GaN thin membranes. As result of our investigations, focused on deflection and stress distribution in the membrane, further reducing of membrane thickness, to improve devices' electrical performances, is possible without affecting their reliability.
{"title":"Morphological analysis of GaN membranes obtained by micromachining of GaN/Si","authors":"A. Cismaru, A. Muller, F. Comanescu, M. Purica, A. Stefanescu, A. Dinescu, G. Konstantinidis, A. Stavrinidis","doi":"10.1109/IRPS.2013.6532090","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532090","url":null,"abstract":"The morphological analysis is targeted towards a better understanding of the reliability of GaN membranes obtained by micromachining of GaN/Si. These membranes are used as support for devices like FBARs or backside-illuminated UV photodetectors. The deflection analysis is performed on 0.4 μm GaN thin membranes. As result of our investigations, focused on deflection and stress distribution in the membrane, further reducing of membrane thickness, to improve devices' electrical performances, is possible without affecting their reliability.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133500298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532003
P. Lu, K. Jenkins
A circuit for long-term measurement of bias temperature instability (BTI) degradation is described. It is an entirely on-chip measurement circuit, which reports measurements periodically with a digital output. Implemented on IBM's z196 Enterprise systems, it can be used to monitor long-term degradation under real-use conditions. Over 500 days worth of ring oscillator degradation data from customer systems are presented. The importance of using a reference oscillator to measure performance degradation in the field, where the supply voltage and temperature can vary dynamically, is shown.
{"title":"A built-in BTI monitor for long-term data collection in IBM microprocessors","authors":"P. Lu, K. Jenkins","doi":"10.1109/IRPS.2013.6532003","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532003","url":null,"abstract":"A circuit for long-term measurement of bias temperature instability (BTI) degradation is described. It is an entirely on-chip measurement circuit, which reports measurements periodically with a digital output. Implemented on IBM's z196 Enterprise systems, it can be used to monitor long-term degradation under real-use conditions. Over 500 days worth of ring oscillator degradation data from customer systems are presented. The importance of using a reference oscillator to measure performance degradation in the field, where the supply voltage and temperature can vary dynamically, is shown.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133543685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532039
A. Bayerl, M. Porti, J. Martín-Martínez, M. Lanza, R. Rodríguez, V. Velayudhan, E. Amat, M. Nafría, X. Aymerich, M. B. González, E. Simoen
In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC) stressed MOSFETs have been investigated at the nanoscale with a Conductive Atomic Force Microscope (CAFM). For the first time, by measuring on the bare oxide, the CAFM has allowed evaluation of the degradation induced along the channel by a previous CHC stress. In particular, higher gate leakage was measured close to source and drain, which has been related to NBTI and CHC degradation, respectively.
{"title":"Channel hot-carriers degradation in MOSFETs: A conductive AFM study at the nanoscale","authors":"A. Bayerl, M. Porti, J. Martín-Martínez, M. Lanza, R. Rodríguez, V. Velayudhan, E. Amat, M. Nafría, X. Aymerich, M. B. González, E. Simoen","doi":"10.1109/IRPS.2013.6532039","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532039","url":null,"abstract":"In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC) stressed MOSFETs have been investigated at the nanoscale with a Conductive Atomic Force Microscope (CAFM). For the first time, by measuring on the bare oxide, the CAFM has allowed evaluation of the degradation induced along the channel by a previous CHC stress. In particular, higher gate leakage was measured close to source and drain, which has been related to NBTI and CHC degradation, respectively.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532087
E. Bury, B. Kaczer, H. Arimura, M. T. Luque, L. Ragnarsson, P. Roussel, A. Veloso, S. Chew, M. Togo, T. Schram, G. Groeseneken
CMOS device improvements have recently been achieved by aggressive scaling of effective oxide thickness (EOT) in Gate First (GF) integration schemes using interfacial layer scavenging. Along with this scaling comes, however, a challenging reliability penalty. Therefore, to decrease the turnaround time of experimental gate stacks, we demonstrate a technique to quantitatively evaluate the long-term bias temperature instability (BTI) behavior of gate stacks on capacitors instead of transistors. We prove that this technique yields comparable results as standard extended measure-stress-measure (eMSM) IV-BTI measurements. Subsequently, we demonstrate in such a short turnaround time experiment that we can achieve scavenging in a Gate Last (GL) processing scheme. Finally, by benefitting from our proposed technique, we conclude that our Gate Last stacks are still more susceptible to BTI than our Gate First stacks with similar EOT.
近年来，利用界面层清除技术在栅极优先(GF)集成方案中有效氧化层厚度(EOT)的积极缩放已经实现了CMOS器件的改进。然而，伴随这种扩展而来的是具有挑战性的可靠性损失。因此，为了减少实验门堆的循环时间，我们展示了一种定量评估电容而不是晶体管上门堆的长期偏置温度不稳定性(BTI)行为的技术。我们证明该技术与标准扩展测量-应力测量(eMSM) IV-BTI测量结果相当。随后，我们在如此短的周转时间实验中证明，我们可以在Gate Last (GL)处理方案中实现清除。最后，从我们提出的技术中获益，我们得出结论，我们的门最后堆栈仍然比具有类似EOT的门第一堆栈更容易受到BTI的影响。
{"title":"Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization","authors":"E. Bury, B. Kaczer, H. Arimura, M. T. Luque, L. Ragnarsson, P. Roussel, A. Veloso, S. Chew, M. Togo, T. Schram, G. Groeseneken","doi":"10.1109/IRPS.2013.6532087","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532087","url":null,"abstract":"CMOS device improvements have recently been achieved by aggressive scaling of effective oxide thickness (EOT) in Gate First (GF) integration schemes using interfacial layer scavenging. Along with this scaling comes, however, a challenging reliability penalty. Therefore, to decrease the turnaround time of experimental gate stacks, we demonstrate a technique to quantitatively evaluate the long-term bias temperature instability (BTI) behavior of gate stacks on capacitors instead of transistors. We prove that this technique yields comparable results as standard extended measure-stress-measure (eMSM) IV-BTI measurements. Subsequently, we demonstrate in such a short turnaround time experiment that we can achieve scavenging in a Gate Last (GL) processing scheme. Finally, by benefitting from our proposed technique, we conclude that our Gate Last stacks are still more susceptible to BTI than our Gate First stacks with similar EOT.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532110
Y. Ren, L. Chen, S. Shi, G. Guo, R. Feng, S. Wen, R. Wong, N. V. van Vonno, B. Bhuva
Pulsed X-rays were used to perform Single-Event Transient (SET) measurements on a COTS DC/DC PWM controller. The results were consistent with those of the previous heavy ion and pulsed laser testings, which indicates that the pulsed X-ray technique is a complementary tool to investigate SET. However, there are some limitations, such as low energy absorption of X-rays in silicon and total ionizing dose (TID) effects due to the X-ray irradiation, which need to be considered during X-ray applications.
{"title":"Single-event transient measurement on a DC/DC PWM controller using Pulsed X-ray technique","authors":"Y. Ren, L. Chen, S. Shi, G. Guo, R. Feng, S. Wen, R. Wong, N. V. van Vonno, B. Bhuva","doi":"10.1109/IRPS.2013.6532110","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532110","url":null,"abstract":"Pulsed X-rays were used to perform Single-Event Transient (SET) measurements on a COTS DC/DC PWM controller. The results were consistent with those of the previous heavy ion and pulsed laser testings, which indicates that the pulsed X-ray technique is a complementary tool to investigate SET. However, there are some limitations, such as low energy absorption of X-rays in silicon and total ionizing dose (TID) effects due to the X-ray irradiation, which need to be considered during X-ray applications.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129663641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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