Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00173
Jen-Hsien Wong, Nan-Yi Wu, W. Lai, Dao-Long Chen, Tang-Yuan Chen, Chung-Hao Chen, Yi-Hsien Wu, Yung-shun Chang, C. Kao, D. Tarng, Teck Chong Lee, C. Hung
As the advanced packaging technology is required to fulfill digitalized industry with big data, such as high performance computing (HPC), data center server, router, and switcher applications. Due to the hunger from above market needs, great interests were induced by both research institutes and industry. Multiple chiplets integration can provide design flexibility, high performance and power efficiency. Therefore, advanced package technology is needed for this application. Chip-last FOCoS, one of the best options, is developed as advanced packaging technology to enable different functional chiplets within a single package. This technology can improve yield, performance and cost to shorten the time to market. The package warpage control is very challenging in assembly of larger fan-out package with multi-chip integration. The redistribution layer (RDL) trace broken risk is also key issue to influence package reliability in thermal cycling test (TCT). High CTE-mismatch effect was significantly occurred at die to die (D2D) gap. The RDL trace stress is more sensitive to material properties, process flow and geometric structure due to complex multi-layer structure in several materials. It is a tougher job to minimize RDL trace stress under each process limitation. In this paper, the RDL trace stress is compared in detail to trace layout, line/spaces (L/S), D2D gap distance and trace location at room temperature (RT) and high temperature (HT). The results indicate that the trace layout design and trace location play critical roles to enhance reliability performance.
{"title":"Warpage and RDL Stress Analysis in Large Fan-Out Package with Multi-Chiplet Integration","authors":"Jen-Hsien Wong, Nan-Yi Wu, W. Lai, Dao-Long Chen, Tang-Yuan Chen, Chung-Hao Chen, Yi-Hsien Wu, Yung-shun Chang, C. Kao, D. Tarng, Teck Chong Lee, C. Hung","doi":"10.1109/ectc51906.2022.00173","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00173","url":null,"abstract":"As the advanced packaging technology is required to fulfill digitalized industry with big data, such as high performance computing (HPC), data center server, router, and switcher applications. Due to the hunger from above market needs, great interests were induced by both research institutes and industry. Multiple chiplets integration can provide design flexibility, high performance and power efficiency. Therefore, advanced package technology is needed for this application. Chip-last FOCoS, one of the best options, is developed as advanced packaging technology to enable different functional chiplets within a single package. This technology can improve yield, performance and cost to shorten the time to market. The package warpage control is very challenging in assembly of larger fan-out package with multi-chip integration. The redistribution layer (RDL) trace broken risk is also key issue to influence package reliability in thermal cycling test (TCT). High CTE-mismatch effect was significantly occurred at die to die (D2D) gap. The RDL trace stress is more sensitive to material properties, process flow and geometric structure due to complex multi-layer structure in several materials. It is a tougher job to minimize RDL trace stress under each process limitation. In this paper, the RDL trace stress is compared in detail to trace layout, line/spaces (L/S), D2D gap distance and trace location at room temperature (RT) and high temperature (HT). The results indicate that the trace layout design and trace location play critical roles to enhance reliability performance.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130063390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00010
Yoon-Yi Hwang, S. Moon, Seungki Nam, Jeong HoonAhn
In this work, we propose a novel chiplet platform for 2.5D/3D IC Integration. Given specific design requirements, the Samsung chipletadvanced platform engine (SCAPE) can provide an integrated image of suitable advanced packaging solutionsfrom multi-chip module (MCM) or 2.5D silicon interposer or 3D stacked structures, taking into account the evaluation metrics (performance, power and area: PPA) of system and die-to-die (D2D) interconnect. It can also project an optimal design balance between system performance and cost which is closely related to die size. In a chiplet design perspective, multiple solutions for various specifications may be presented simply, but the architecture-based optimal integrated solution can be allowed only right after performance and cost are thoroughly understood. For that purpose, reference architectures are proposed to be analyzed in terms of power, area and latency at the same bandwidth requirement. As the MCM, 2.5D and 3D structures in sequence shorten the D2D distance, it can mitigate the design overhead for chiplet implementation by reducing the interface IP area and required power consumption. In terms of power and area overhead when compared to a 2D monolithic design, for homogeneously split dies, MCM, 2.5D and 3D design cases show that additional power increase 2.1%, 1.1% and 0.04% respectively and show that additional area increase by 5.6%, 2.4% and 2.4% in a HPC/AI case with 450mm2 diesize. In addition, two best heterogeneous practices are created and analyzed. From the experiments, it clearly shows that 3D face-to-face (F2F) structure is the best option with obvious metrics including system power overhead of 0.11% and system area overhead of 1.9% increase for a bandwidth-centric system with 340W and 700mm2like GPU/NPU from MCM, 2.5D and 3D package candidates. Moreover, in the other latency-centric system with150W and 420mm2 like CPU, it can be seen that 3D F2F case with 25μm μ-bump pitchworks up to 12.5X TBps areal BW density and 80μm C4bump pitch also work up to 8.5X W/mm2 areal power density due to their physical limitation. With respect to power and signal integrity (PSI) of interface elements under various packaging candidates, this work is helpful to understand which chiplet configuration is the best option with obvious metrics and physical limitations of advanced packages, and the need to improve interfaces such as μ-bump or C4bump especially in 3D stacked ICs. We also completed a hierarchical impact diagram of configured systems considering the overhead of interface/TSV itself, die split, test circuitry, and P&R affected by the existence of TSVs. Therefore, in considering the movement toward the era of beyond Moore's Law in the performance-/cost-driven semiconductor industry, this work is expected to serve as a future chiplet reference platform which can provide differentiating solutions for quick adoption of designs.
{"title":"Chiplet-based System PSI Optimization for 2.5D/3D Advanced Packaging Implementation","authors":"Yoon-Yi Hwang, S. Moon, Seungki Nam, Jeong HoonAhn","doi":"10.1109/ectc51906.2022.00010","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00010","url":null,"abstract":"In this work, we propose a novel chiplet platform for 2.5D/3D IC Integration. Given specific design requirements, the Samsung chipletadvanced platform engine (SCAPE) can provide an integrated image of suitable advanced packaging solutionsfrom multi-chip module (MCM) or 2.5D silicon interposer or 3D stacked structures, taking into account the evaluation metrics (performance, power and area: PPA) of system and die-to-die (D2D) interconnect. It can also project an optimal design balance between system performance and cost which is closely related to die size. In a chiplet design perspective, multiple solutions for various specifications may be presented simply, but the architecture-based optimal integrated solution can be allowed only right after performance and cost are thoroughly understood. For that purpose, reference architectures are proposed to be analyzed in terms of power, area and latency at the same bandwidth requirement. As the MCM, 2.5D and 3D structures in sequence shorten the D2D distance, it can mitigate the design overhead for chiplet implementation by reducing the interface IP area and required power consumption. In terms of power and area overhead when compared to a 2D monolithic design, for homogeneously split dies, MCM, 2.5D and 3D design cases show that additional power increase 2.1%, 1.1% and 0.04% respectively and show that additional area increase by 5.6%, 2.4% and 2.4% in a HPC/AI case with 450mm2 diesize. In addition, two best heterogeneous practices are created and analyzed. From the experiments, it clearly shows that 3D face-to-face (F2F) structure is the best option with obvious metrics including system power overhead of 0.11% and system area overhead of 1.9% increase for a bandwidth-centric system with 340W and 700mm2like GPU/NPU from MCM, 2.5D and 3D package candidates. Moreover, in the other latency-centric system with150W and 420mm2 like CPU, it can be seen that 3D F2F case with 25μm μ-bump pitchworks up to 12.5X TBps areal BW density and 80μm C4bump pitch also work up to 8.5X W/mm2 areal power density due to their physical limitation. With respect to power and signal integrity (PSI) of interface elements under various packaging candidates, this work is helpful to understand which chiplet configuration is the best option with obvious metrics and physical limitations of advanced packages, and the need to improve interfaces such as μ-bump or C4bump especially in 3D stacked ICs. We also completed a hierarchical impact diagram of configured systems considering the overhead of interface/TSV itself, die split, test circuitry, and P&R affected by the existence of TSVs. Therefore, in considering the movement toward the era of beyond Moore's Law in the performance-/cost-driven semiconductor industry, this work is expected to serve as a future chiplet reference platform which can provide differentiating solutions for quick adoption of designs.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00172
Yu-Chin Lee, Chia-Yu Chen, Kuo-Shen Chen, Jen-Hsien Wong, W. Lai, Tang-Yuan Chen, Dao-Long Chen, D. Tarng
Fan-out packaging has been treated as one of the most capable wafer-level packaging scheme but it usually accompanies with significant wafer warpage. In particular, asymmetric warping is frequently reported to cause numerous severe problems and should be properly resolved. Traditionally, full scale finite element simulations are usually used for addressing the needs and for providing possible engineering solutions. However, its case-by-case nature and enormous computational effort usually make it extremely inefficient for performing full scale simulation at the early design evaluation stage, where efficient semi-analytical or efficient numerical models should be used. In this work, full fan-out structures are firstly simplified into bi-layer equivalent structures and both the semi-analytical bifurcation temperature and post-bifurcation warpage predictions are then developed based on their original ideal analytical form for counting the needs in engineering applications. Through the comparison and correction using 3D finite element simulations, the developed models should be effective for providing trend and parameter- dependent predictions. Finally, essential preparations on building process emulator for chip-first or -last processes are presented to serve as the benchmarks for evaluating the performance of subsequent simplified process emulator in packaging warpage analyses.
{"title":"Effective Computational Models for Addressing Asymmetric Warping of Fan-Out Reconstituted Wafer Packaging","authors":"Yu-Chin Lee, Chia-Yu Chen, Kuo-Shen Chen, Jen-Hsien Wong, W. Lai, Tang-Yuan Chen, Dao-Long Chen, D. Tarng","doi":"10.1109/ectc51906.2022.00172","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00172","url":null,"abstract":"Fan-out packaging has been treated as one of the most capable wafer-level packaging scheme but it usually accompanies with significant wafer warpage. In particular, asymmetric warping is frequently reported to cause numerous severe problems and should be properly resolved. Traditionally, full scale finite element simulations are usually used for addressing the needs and for providing possible engineering solutions. However, its case-by-case nature and enormous computational effort usually make it extremely inefficient for performing full scale simulation at the early design evaluation stage, where efficient semi-analytical or efficient numerical models should be used. In this work, full fan-out structures are firstly simplified into bi-layer equivalent structures and both the semi-analytical bifurcation temperature and post-bifurcation warpage predictions are then developed based on their original ideal analytical form for counting the needs in engineering applications. Through the comparison and correction using 3D finite element simulations, the developed models should be effective for providing trend and parameter- dependent predictions. Finally, essential preparations on building process emulator for chip-first or -last processes are presented to serve as the benchmarks for evaluating the performance of subsequent simplified process emulator in packaging warpage analyses.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132445063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00189
P. Lall, Jinesh Narangaparambil, Scott Miller
Realization of flexible hybrid electronics using additively printed circuits requires the development of component attachment methods with low-temperature processing. Additive electronics may be fabricated on a variety of substrates including Polyimide, PET, PEN. While polyimide may be processed at normal reflow temperatures, thermally stabilized PET and PEN require a peak processing temperature less than 150 °C. A number of new solder materials have emerged capable of being processed at temperatures in the range of 130-150 °C. Low-temperature processing has additional benefits of lower warpage, lower energy consumption and lower carbon footprint. In this paper, the process-performance-reliability relationships have been studied for Sn-Bi-Ag and Sn-In solders on additively printed copper metallization. Process-recipes have been developed for direct write additive printer for fabrication of single layer and multilayer flexible circuits. Copper ink is a good and cost-effective alternative to silver ink, but its use has lagged owing to an increased propensity for oxidation. In this paper, photonic curing has been used to sinter copper ink to make the traces conductive. The method flashes high energy light that sinter metal particles instantaneously and the temperature of the substrate remains low. The effect of the different photonic sintering profiles on the mechanical and electrical properties of the printed traces has been studied. Electrical and mechanical performance has been studied through characterization of the frequency-performance of low-pass filters, high-pass filters and amplifiers fabricated using surface mount components on additively printed metallization. Reliability and the performance degradation of the additively printed circuits has been quantified in flex-to-install applications. In addition, SEM/EDAX has been used to study the intermetallics at the interface of LTS and additively printed circuits.
{"title":"Process-Reliability Relationships of SnBiAg and SnIn Solders for Component Attachment on Flexible Direct-Write Additive Circuits in Wearable Applications","authors":"P. Lall, Jinesh Narangaparambil, Scott Miller","doi":"10.1109/ectc51906.2022.00189","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00189","url":null,"abstract":"Realization of flexible hybrid electronics using additively printed circuits requires the development of component attachment methods with low-temperature processing. Additive electronics may be fabricated on a variety of substrates including Polyimide, PET, PEN. While polyimide may be processed at normal reflow temperatures, thermally stabilized PET and PEN require a peak processing temperature less than 150 °C. A number of new solder materials have emerged capable of being processed at temperatures in the range of 130-150 °C. Low-temperature processing has additional benefits of lower warpage, lower energy consumption and lower carbon footprint. In this paper, the process-performance-reliability relationships have been studied for Sn-Bi-Ag and Sn-In solders on additively printed copper metallization. Process-recipes have been developed for direct write additive printer for fabrication of single layer and multilayer flexible circuits. Copper ink is a good and cost-effective alternative to silver ink, but its use has lagged owing to an increased propensity for oxidation. In this paper, photonic curing has been used to sinter copper ink to make the traces conductive. The method flashes high energy light that sinter metal particles instantaneously and the temperature of the substrate remains low. The effect of the different photonic sintering profiles on the mechanical and electrical properties of the printed traces has been studied. Electrical and mechanical performance has been studied through characterization of the frequency-performance of low-pass filters, high-pass filters and amplifiers fabricated using surface mount components on additively printed metallization. Reliability and the performance degradation of the additively printed circuits has been quantified in flex-to-install applications. In addition, SEM/EDAX has been used to study the intermetallics at the interface of LTS and additively printed circuits.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00265
Xiaowu Zhang, Yong Han, G. Tang, Haoran Chen, B. L. Lau
In this paper, we present design and development of advanced liquid cooling solution enabling high energy efficiency and low cooling cost. This is a multi-scale thermal solution including chip level, server level and cabinet level. At chip level, cooling modules with Si-based jet impingement micro-coolers have been developed for the main heat source cooling, such as server processors. In other words, the cooling modules are mounted on the top of server processors for direct liquid cooling. At server level, multiple mini cooling modules have been developed for main heaters in each server. Multiple mini heat exchangers of compact size and high heat transfer rate have been implemented on the board. Micro-scale heat transfer enhancement structures have been designed for liquid-to-liquid mini heat exchanger. In this cooling system, the need for air conditioner cooling is eliminated for energy saving. Smart energy management has been performed in the cabinet to control multiple cooling modules and mini heat exchangers, based on the real time temperature monitor. The energy consumption required for cooling system is further reduced, while maintaining appropriate heat removal capability for the servers.
{"title":"Development of Advanced Liquid Cooling Solution on Data Centre Cooling","authors":"Xiaowu Zhang, Yong Han, G. Tang, Haoran Chen, B. L. Lau","doi":"10.1109/ectc51906.2022.00265","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00265","url":null,"abstract":"In this paper, we present design and development of advanced liquid cooling solution enabling high energy efficiency and low cooling cost. This is a multi-scale thermal solution including chip level, server level and cabinet level. At chip level, cooling modules with Si-based jet impingement micro-coolers have been developed for the main heat source cooling, such as server processors. In other words, the cooling modules are mounted on the top of server processors for direct liquid cooling. At server level, multiple mini cooling modules have been developed for main heaters in each server. Multiple mini heat exchangers of compact size and high heat transfer rate have been implemented on the board. Micro-scale heat transfer enhancement structures have been designed for liquid-to-liquid mini heat exchanger. In this cooling system, the need for air conditioner cooling is eliminated for energy saving. Smart energy management has been performed in the cabinet to control multiple cooling modules and mini heat exchangers, based on the real time temperature monitor. The energy consumption required for cooling system is further reduced, while maintaining appropriate heat removal capability for the servers.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131022130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00122
R. Chen, Justin H. Chow, S. Sitaraman
This paper investigated and compared the damage evolution of four types of double-sided copper conductors under the adaptive curvature flexure test. The crack initiation and propagation processes were inspected three-dimensionally in different stages of the test. The resistance change profiles related to different crack levels were identified.Thin-film conductors continue to play an important role in flexible electronics, and thus, the performance and reliability of such conductors under mechanical loading such as stretch, bend, and twist need to be studied through experiments as well as simulations. This paper focuses on the damage evolution of the thin-film conductors under cyclic bending. Four types of double-sided copper conductors: straight trace without coverlay, straight trace with coverlay, notched trace without coverlay, and notched trace with coverlay on multi-layer substrates were studied in this work. The adaptive curvature flexure test method, which is suitable for thin-film bending, was employed in this work. Adaptive curvature flexure test is one where the flexible substrate with its trace is positioned between two parallel plates, and the parallel plates are moved relative to each other such that the gap distance between the parallel plates changes in one of the configurations of the adaptive curvature flexure test. Different strain levels can be achieved easily in such an adaptive curvature flexure test by controlling the gap distance between the parallel plates. By subjecting flexible substrates with thin traces to such bend tests, the fatigue life of the specimen was determined for different magnitudes of strain ranges. The results were then compared among the four types of traces. Specimens were designed such that the traces were placed on both sides of the substrate so that the one of the traces would undergo tensile straining, while the other one would undergo compressive straining. It was shown that the fatigue life was highly dependent on the magnitude of strain range, and that the trace on the compressive side failed sooner than that on the tensile side. The failed specimens were examined in a microscope at different number of cycles. Also, the resistance of the traces, which is directly related to the reliability of thin-film traces, was monitored in-situ during bending. The resistance change with the strain range change as well as the resistance progression with the number of cycles in tensile as well as compressive mode were determined, and such information is then used to create failure prediction models for thin-film conductors on flexible substrates.
{"title":"Damage Evolution of Double-Sided Copper Conductor on Multi-layer Flexible Substrate Under Bending","authors":"R. Chen, Justin H. Chow, S. Sitaraman","doi":"10.1109/ectc51906.2022.00122","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00122","url":null,"abstract":"This paper investigated and compared the damage evolution of four types of double-sided copper conductors under the adaptive curvature flexure test. The crack initiation and propagation processes were inspected three-dimensionally in different stages of the test. The resistance change profiles related to different crack levels were identified.Thin-film conductors continue to play an important role in flexible electronics, and thus, the performance and reliability of such conductors under mechanical loading such as stretch, bend, and twist need to be studied through experiments as well as simulations. This paper focuses on the damage evolution of the thin-film conductors under cyclic bending. Four types of double-sided copper conductors: straight trace without coverlay, straight trace with coverlay, notched trace without coverlay, and notched trace with coverlay on multi-layer substrates were studied in this work. The adaptive curvature flexure test method, which is suitable for thin-film bending, was employed in this work. Adaptive curvature flexure test is one where the flexible substrate with its trace is positioned between two parallel plates, and the parallel plates are moved relative to each other such that the gap distance between the parallel plates changes in one of the configurations of the adaptive curvature flexure test. Different strain levels can be achieved easily in such an adaptive curvature flexure test by controlling the gap distance between the parallel plates. By subjecting flexible substrates with thin traces to such bend tests, the fatigue life of the specimen was determined for different magnitudes of strain ranges. The results were then compared among the four types of traces. Specimens were designed such that the traces were placed on both sides of the substrate so that the one of the traces would undergo tensile straining, while the other one would undergo compressive straining. It was shown that the fatigue life was highly dependent on the magnitude of strain range, and that the trace on the compressive side failed sooner than that on the tensile side. The failed specimens were examined in a microscope at different number of cycles. Also, the resistance of the traces, which is directly related to the reliability of thin-film traces, was monitored in-situ during bending. The resistance change with the strain range change as well as the resistance progression with the number of cycles in tensile as well as compressive mode were determined, and such information is then used to create failure prediction models for thin-film conductors on flexible substrates.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00088
J. Hong, Su Chang Lee, S. Han, S. Oh, Sang Sik Park, Hyeong Mun Kang, Won Keun Kim, K. Kim, D. Oh
A typical stack bonding process of HBM core dies is 1) lamination of nonconductive film (NCF) over the bumps of core dies, 2) thermal compression bonding (TC bonding) of core dies, and 3) molding EMC around stacked dies. The main advantage of TC bonding is being able to control joint void by pre-filling the bump area with NCF lamination prior to reflow. TC bonding, however, has a fillet at the die joint gap edge and unfilled gap risk at the die corner need to be controlled, in turn, the flow in TC Bonding process. We put much of our effort to improve the accuracy of NCF flow simulation to understand the mechanism for fillet shape formation and to help the development of material and bonding process.To simulate the NCF flow in TC Bonding for stacking dies, we must acquire the viscosity profile during process in temperature and time scale, process pressure and initial shape of the laminated NCF surface. However, TC Bonding equipment has high temperature and rate of temperature rise comparing with the conventional rheometer for the high viscosity such as NCF, rheometer data is not adequate for our simulation and to describe the NCF surface evolution at the die joint gap edge in simulation, we must consider two phase flow and NCF Zone which is very high aspect ratio comparing the thickness with size. Using commercial code, we need to use the volume of fraction (VOF) model with billions mesh but it needs several month to solve the NCF fillet shape under single condition.In our study, we set up the methodology for NCF viscosity profile during the die stacking process from the pressure and monitoring the joint gap height, and to define the surface shape of the laminated NCF, we trying to find out the relationship between the NCF height and the bump density of the laminated face. After then, we establish the in-house simulation code based on Hele-Shaw flow formulation and we can diminish the calculation time dramatically to several minutes. Finally we verify and find out the fillet shape over the conditions of the process pressure and NCF viscosity and suggest a bump layout design for the optimized fillet shape.
{"title":"Novel method for NCF flow simulation in HBM thermal compression bonding process to optimize the NCF shape","authors":"J. Hong, Su Chang Lee, S. Han, S. Oh, Sang Sik Park, Hyeong Mun Kang, Won Keun Kim, K. Kim, D. Oh","doi":"10.1109/ectc51906.2022.00088","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00088","url":null,"abstract":"A typical stack bonding process of HBM core dies is 1) lamination of nonconductive film (NCF) over the bumps of core dies, 2) thermal compression bonding (TC bonding) of core dies, and 3) molding EMC around stacked dies. The main advantage of TC bonding is being able to control joint void by pre-filling the bump area with NCF lamination prior to reflow. TC bonding, however, has a fillet at the die joint gap edge and unfilled gap risk at the die corner need to be controlled, in turn, the flow in TC Bonding process. We put much of our effort to improve the accuracy of NCF flow simulation to understand the mechanism for fillet shape formation and to help the development of material and bonding process.To simulate the NCF flow in TC Bonding for stacking dies, we must acquire the viscosity profile during process in temperature and time scale, process pressure and initial shape of the laminated NCF surface. However, TC Bonding equipment has high temperature and rate of temperature rise comparing with the conventional rheometer for the high viscosity such as NCF, rheometer data is not adequate for our simulation and to describe the NCF surface evolution at the die joint gap edge in simulation, we must consider two phase flow and NCF Zone which is very high aspect ratio comparing the thickness with size. Using commercial code, we need to use the volume of fraction (VOF) model with billions mesh but it needs several month to solve the NCF fillet shape under single condition.In our study, we set up the methodology for NCF viscosity profile during the die stacking process from the pressure and monitoring the joint gap height, and to define the surface shape of the laminated NCF, we trying to find out the relationship between the NCF height and the bump density of the laminated face. After then, we establish the in-house simulation code based on Hele-Shaw flow formulation and we can diminish the calculation time dramatically to several minutes. Finally we verify and find out the fillet shape over the conditions of the process pressure and NCF viscosity and suggest a bump layout design for the optimized fillet shape.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131317646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00347
K. Shie, Dinh-Phuc Tran, A. Gusak, K. Tu, Hung-Che Liu, Chih Chen
A simple bonding model is proposed to correlate the bonding time with some parameters such as surface roughness, temperature, pressure, and grain boundary diffusivity. The theoretical bonding time is defined as the time required for the bonding area to reach 95% of the surface area. Cu-Cu direct bonding is accomplished through the surface creep mechanism, which are divided into four stages, surface contact and plastic deformation, isolated void and grain boundary formation, interfacial void ripening, and interface elimination by grain growth. In this study, we established a surface creep model for the second bonding stage. The driving force is a pressure gradient, which triggers Cu atoms to fill voids at the bonding interface via grain boundary and surface diffusion. This is driven by the release of Gibbs free energy in the system. We took the critical parameters, including surface roughness, bonding temperature, and pressure into account of the model. Using such a kinetic model, we are able to estimate the theoretical bonding time as functions of surface roughness, grain boundary diffusivity, temperature, and pressure. The results indicate that surface roughness and orientation play critical roles on the bonding time. The theoretic bonding time is estimated as 104 s for the Cu films with a surface roughness of 10 nm bonded at 200 °C and 0.5 MPa. As the surface roughness is reduced to 1.0 nm, a bonding time of 10 s is predicted.
{"title":"Modeling of Cu-Cu Thermal Compression Bonding","authors":"K. Shie, Dinh-Phuc Tran, A. Gusak, K. Tu, Hung-Che Liu, Chih Chen","doi":"10.1109/ectc51906.2022.00347","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00347","url":null,"abstract":"A simple bonding model is proposed to correlate the bonding time with some parameters such as surface roughness, temperature, pressure, and grain boundary diffusivity. The theoretical bonding time is defined as the time required for the bonding area to reach 95% of the surface area. Cu-Cu direct bonding is accomplished through the surface creep mechanism, which are divided into four stages, surface contact and plastic deformation, isolated void and grain boundary formation, interfacial void ripening, and interface elimination by grain growth. In this study, we established a surface creep model for the second bonding stage. The driving force is a pressure gradient, which triggers Cu atoms to fill voids at the bonding interface via grain boundary and surface diffusion. This is driven by the release of Gibbs free energy in the system. We took the critical parameters, including surface roughness, bonding temperature, and pressure into account of the model. Using such a kinetic model, we are able to estimate the theoretical bonding time as functions of surface roughness, grain boundary diffusivity, temperature, and pressure. The results indicate that surface roughness and orientation play critical roles on the bonding time. The theoretic bonding time is estimated as 104 s for the Cu films with a surface roughness of 10 nm bonded at 200 °C and 0.5 MPa. As the surface roughness is reduced to 1.0 nm, a bonding time of 10 s is predicted.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131324767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00234
Allison T. Osmanson, Y. Kim, C. Kim, P. Thompson, Qiao Chen, Sylvester Ankamah-Kusi
Recent electromigration (EM) testing of wafer-level chip scale packages (WCSPs) under various duty factors (DFs) or pulse "on"/"off" ratio, of low-frequency pulsed-direct current (pulsed-DC) conditions have uncovered the in-tandem failure mechanisms which occur during pulsed-DC EM testing: 1) classical EM failure by voiding; 2) thermal fatigue; and 3) creep ratcheting. Cross-sectional scanning electron microscope (SEM) failure analysis of samples tested under a high DF pulsed-DC testing condition revealed crack propagation in addition to EM voiding near the interface between the device under test (DUT) solder bump and the Cu under bump metallization (UBM) layer. The crack and void suggest that significant plastic deformation by, dislocation gliding and thus dislocation multiplication, and strain hardening occur with fluctuating temperature and stress during pulse "on" and "off" cycles. Under the right conditions, material which undergoes a significant amount of strain hardening becomes susceptible to fatigue failure even with a small amount of cyclic stress. The stress fluctuation combined with these microscopic mechanisms lead to thermal fatigue, which, combined with the classical EM failure mechanism, enhances the EM failure kinetics. The EM acceleration causes these samples to have shorter mean-time-to-failure (MTTF) than samples tested under DC. Meanwhile, samples tested under low DF pulsed-DC conditions showed failure features by creep ratcheting and had far longer MTTF than the predicted based on the classic cumulative damage model. Cross-sectional SEM failure analysis of samples tested under a low DF pulsed-DC condition uncovered features of creep ratcheting failure, evidenced by squeezed out or displaced solder material from the solder bump. It is hypothesized that until failure by creep ratcheting occurs, the relatively extended relaxation time allowed in low DF pulsed-DC conditions allow dynamic recrystallization, which releases the driving force for the fatigue by nucleating deformation free grains, to occur. The predicted reason why this mechanism is observed in low DF pulsed-DC conditions instead of fatigue, as compared to high DF pulsed-DC conditions, is that dynamic recrystallization mechanism requires more time to dominate than the fatigue crack propagation mechanism. The two mechanisms are essentially believed to compete with one another, and the primary condition which allows one failure mechanism to dominate over the other is the DF, which dictates the "on" vs. "off" time. The finite element method (FEM) of the stress associated with thermal fatigue and creep mechanisms is implemented to investigate these three phenomena. Findings of this research are discussed and presented in this study.
{"title":"Observation of Fatigue and Creep Ratcheting Failure in Solder Joints under Pulsed Direct Current Electromigration Testing","authors":"Allison T. Osmanson, Y. Kim, C. Kim, P. Thompson, Qiao Chen, Sylvester Ankamah-Kusi","doi":"10.1109/ectc51906.2022.00234","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00234","url":null,"abstract":"Recent electromigration (EM) testing of wafer-level chip scale packages (WCSPs) under various duty factors (DFs) or pulse \"on\"/\"off\" ratio, of low-frequency pulsed-direct current (pulsed-DC) conditions have uncovered the in-tandem failure mechanisms which occur during pulsed-DC EM testing: 1) classical EM failure by voiding; 2) thermal fatigue; and 3) creep ratcheting. Cross-sectional scanning electron microscope (SEM) failure analysis of samples tested under a high DF pulsed-DC testing condition revealed crack propagation in addition to EM voiding near the interface between the device under test (DUT) solder bump and the Cu under bump metallization (UBM) layer. The crack and void suggest that significant plastic deformation by, dislocation gliding and thus dislocation multiplication, and strain hardening occur with fluctuating temperature and stress during pulse \"on\" and \"off\" cycles. Under the right conditions, material which undergoes a significant amount of strain hardening becomes susceptible to fatigue failure even with a small amount of cyclic stress. The stress fluctuation combined with these microscopic mechanisms lead to thermal fatigue, which, combined with the classical EM failure mechanism, enhances the EM failure kinetics. The EM acceleration causes these samples to have shorter mean-time-to-failure (MTTF) than samples tested under DC. Meanwhile, samples tested under low DF pulsed-DC conditions showed failure features by creep ratcheting and had far longer MTTF than the predicted based on the classic cumulative damage model. Cross-sectional SEM failure analysis of samples tested under a low DF pulsed-DC condition uncovered features of creep ratcheting failure, evidenced by squeezed out or displaced solder material from the solder bump. It is hypothesized that until failure by creep ratcheting occurs, the relatively extended relaxation time allowed in low DF pulsed-DC conditions allow dynamic recrystallization, which releases the driving force for the fatigue by nucleating deformation free grains, to occur. The predicted reason why this mechanism is observed in low DF pulsed-DC conditions instead of fatigue, as compared to high DF pulsed-DC conditions, is that dynamic recrystallization mechanism requires more time to dominate than the fatigue crack propagation mechanism. The two mechanisms are essentially believed to compete with one another, and the primary condition which allows one failure mechanism to dominate over the other is the DF, which dictates the \"on\" vs. \"off\" time. The finite element method (FEM) of the stress associated with thermal fatigue and creep mechanisms is implemented to investigate these three phenomena. Findings of this research are discussed and presented in this study.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129031866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00252
P. Lall, Padmanava Choudhury, A. Pandurangan
Automotive advanced driver-assistance systems (ADAS) require the use of high I/O ball-grid array architectures including flip-chip ball-grid arrays (FCBGAs) in underhood environments. Drive-critical functions enabled by electronics include lane-departure warning systems, collision-avoidance systems, driver-alertness monitoring, park and drive assist systems, adaptive cruise-control, and semi-autonomous navigation. Electronics in underhood applications may be mounted on-engine, on-transmission, on firewall or on wheel-well where the temperature may be in the neighborhood of 150-200 °C. FCBGAs require the use of underfills to provide supplemental restraints for the flip-chip bumps to achieve the needed thermo-mechanical reliability. Current modeling methods lack foundational interface material-data for assessment of fracture at the substrate-UF and chip-UF in thermal cycling, monotonic loading, or mechanical fatigue. In this paper, the effect of sustained high temperature operation on the interfacial fracture toughness of the chip-underfill and substrate-underfill interface has been examined under both monotonic loads and fatigue loads. Bi-material specimen have been fabricated to study the interfacial fracture toughness of the interfaces after sustained high-temperature exposure. The measurements have been used to extract the fracture toughness values as a function of duration of sustained operation at high temperature. Paris’s Power Law parameters have been extracted for both the substrate-UF interface and the chip-UF interface.
{"title":"Sustained High Temperature Fracture Toughness Evolution of Chip-UF and Substrate-UF Interfaces in FCBGAs for Automotive Applications","authors":"P. Lall, Padmanava Choudhury, A. Pandurangan","doi":"10.1109/ectc51906.2022.00252","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00252","url":null,"abstract":"Automotive advanced driver-assistance systems (ADAS) require the use of high I/O ball-grid array architectures including flip-chip ball-grid arrays (FCBGAs) in underhood environments. Drive-critical functions enabled by electronics include lane-departure warning systems, collision-avoidance systems, driver-alertness monitoring, park and drive assist systems, adaptive cruise-control, and semi-autonomous navigation. Electronics in underhood applications may be mounted on-engine, on-transmission, on firewall or on wheel-well where the temperature may be in the neighborhood of 150-200 °C. FCBGAs require the use of underfills to provide supplemental restraints for the flip-chip bumps to achieve the needed thermo-mechanical reliability. Current modeling methods lack foundational interface material-data for assessment of fracture at the substrate-UF and chip-UF in thermal cycling, monotonic loading, or mechanical fatigue. In this paper, the effect of sustained high temperature operation on the interfacial fracture toughness of the chip-underfill and substrate-underfill interface has been examined under both monotonic loads and fatigue loads. Bi-material specimen have been fabricated to study the interfacial fracture toughness of the interfaces after sustained high-temperature exposure. The measurements have been used to extract the fracture toughness values as a function of duration of sustained operation at high temperature. Paris’s Power Law parameters have been extracted for both the substrate-UF interface and the chip-UF interface.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125515259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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