Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00312
Rick Ye, E. Chen, W. Teng, Andrew Kang, Yu-Po Wang
The dielectrics material of flip-chip ball grid arrays, Ajinomoto build-up film (ABF), crack root cause and methods to prevent it were studied. The ABF crack was observed after dielectrics lamination and laser via de-smear process. An internal stress from substrate material CTE mismatch and shrinkage during cooling, which is the ABF crack root cause. The factors affecting the ABF stress were also studied, it was found that ABF thickness and residual Cu rate of substrate pattern are the key factors to the ABF stress. Strategies of decreasing the thermal stress stored and releasing the stored stress to prevent ABF crack were demonstrated through process DOE.
{"title":"Study of Parameter Tuning for the Curing Condition on ABF Type for Large FCBGA Package","authors":"Rick Ye, E. Chen, W. Teng, Andrew Kang, Yu-Po Wang","doi":"10.1109/ectc51906.2022.00312","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00312","url":null,"abstract":"The dielectrics material of flip-chip ball grid arrays, Ajinomoto build-up film (ABF), crack root cause and methods to prevent it were studied. The ABF crack was observed after dielectrics lamination and laser via de-smear process. An internal stress from substrate material CTE mismatch and shrinkage during cooling, which is the ABF crack root cause. The factors affecting the ABF stress were also studied, it was found that ABF thickness and residual Cu rate of substrate pattern are the key factors to the ABF stress. Strategies of decreasing the thermal stress stored and releasing the stored stress to prevent ABF crack were demonstrated through process DOE.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00367
Xiao-Yong Han, Wei Wang, Yufeng Jin
Silicon-based fan-out package is an important Fan-Out Wafer Level Packaging (FOWLP) approach. However, there is usually a height difference between the chip surface and the substrate surface, which influences the reliability of the (redistributed layer) RDL lines connecting the chip and supporting substrate. In this paper, numerical simulation was used to study the von-Mises stress of Re-distributed layer (RDL) under different designs. The influence of dielectric materials, wiring strategies, gap width, chip thickness and other factors on the reliability of the RDL was carefully studied to find out the main influencing factors. The results indicated the gap width was the most important factor to affect the stress of a silicon-based fan-out package. In addition, a test structure was designed and a 5μm wide RDL was successfully prepared to verify the feasibility of the present approach.
{"title":"Influence of height difference between chip and substrate on RDL in silicon-based fan-out package","authors":"Xiao-Yong Han, Wei Wang, Yufeng Jin","doi":"10.1109/ectc51906.2022.00367","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00367","url":null,"abstract":"Silicon-based fan-out package is an important Fan-Out Wafer Level Packaging (FOWLP) approach. However, there is usually a height difference between the chip surface and the substrate surface, which influences the reliability of the (redistributed layer) RDL lines connecting the chip and supporting substrate. In this paper, numerical simulation was used to study the von-Mises stress of Re-distributed layer (RDL) under different designs. The influence of dielectric materials, wiring strategies, gap width, chip thickness and other factors on the reliability of the RDL was carefully studied to find out the main influencing factors. The results indicated the gap width was the most important factor to affect the stress of a silicon-based fan-out package. In addition, a test structure was designed and a 5μm wide RDL was successfully prepared to verify the feasibility of the present approach.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00337
Po Yuan Su, D. Ho, Jacy Pu, Yu Po Wang
Since its introduction in the 1960s, high performance computing (HPC) has made enormous contribution to scientific, engineering and industrial competitiveness as well as other goverment missions. High data rate with high speed transmission has been required for networking and high performance computing application, the chip size and package design has been become larger and larger. Accompanied by the big size design with package, the physical limits has the high cost for the advanced silicon node. The demand for higher functionality devices drives integration technologies to overcome limitations in Moore’s Law. Heterogeneous integration is the one of technologies to meet high performance computing application standards using high bandwidth and Input/Output (I/O) density. The split die of integration in package is the best solution to increase gross die with wafer good yield rate for cost efficiency, and Fan-out Embedded Bridge (FO-EB) Package would be the best representative for HPC and Networking application.The FO-EB is meaning spilt dies with embedded bridge die in fan out package which Inter Connect Die (ICD) become silicon bridge die to do the communications for high electrical performance purpose. Comparing with 2.5D package and FO-MCM package, FO-EB package warpage not only close with 2.5D package, but also better than FO-MCM (Fan-out Multi Chip Module) package. Besides, the electrical performance for high bandwidth memory as good as 2.5D package and FO-MCM package. The FO-EB package has integrated silicon ICD which means provide interconnections between spilt dies with short distance and the package model is more flexable than 2.5D package. That is why FO-EB would be the better choice for HPC and Networking application.The reason we choose FO-EB because it can contribute the same electrical performance to 2.5D package with FO-MCM package and the package warpgae well to be controlled. In this paper, we like to discuss a designed to evaluate the FO-EB and do the measurement comparsion for the warpage, and do the electrical preformance comparsion for the 2.5D, FO-EB and FO-MCM packages. Finally, this paper will find out the chiplets Integrated solution with FO-EB Package in HPC and Networking Application.
自20世纪60年代推出以来，高性能计算(HPC)为科学、工程和工业竞争力以及其他政府任务做出了巨大贡献。网络和高性能计算应用对高数据速率和高速传输的要求越来越高，芯片尺寸和封装设计也越来越大。伴随着封装的大尺寸设计，先进硅节点的物理限制具有高成本。对更高功能设备的需求推动集成技术克服摩尔定律的限制。异构集成是一种利用高带宽和I/O密度来满足高性能计算应用标准的技术。集成在封装中的分体式芯片是提高总晶片成品率和成本效率的最佳解决方案，而扇出嵌入式桥(FO-EB)封装将是高性能计算和网络应用的最佳代表。FO-EB是指在扇形封装中嵌入桥接模的溢出模，其中互连模(ICD)成为硅桥接模，用于高电气性能目的的通信。与2.5D封装和FO-MCM封装相比，FO-EB封装的翘曲度不仅接近2.5D封装，而且优于FO-MCM (Fan-out Multi Chip Module)封装。此外，高带宽存储器的电气性能可媲美2.5D封装和FO-MCM封装。FO-EB封装集成了硅ICD，这意味着在分散的模具之间提供短距离的互连，封装模型比2.5D封装更灵活。这就是为什么FO-EB将是高性能计算和网络应用程序的更好选择。我们之所以选择FO-EB，是因为它可以提供与FO-MCM封装相同的2.5D封装电气性能，并且封装翘曲易于控制。在本文中，我们将讨论一种用于评估FO-EB的设计，并对翘曲进行测量比较，并对2.5D, FO-EB和FO-MCM封装进行电气性能比较。最后，本文将探索FO-EB封装在高性能计算和网络应用中的小芯片集成解决方案。
{"title":"Chiplets Integrated Solution with FO-EB Package in HPC and Networking Application","authors":"Po Yuan Su, D. Ho, Jacy Pu, Yu Po Wang","doi":"10.1109/ectc51906.2022.00337","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00337","url":null,"abstract":"Since its introduction in the 1960s, high performance computing (HPC) has made enormous contribution to scientific, engineering and industrial competitiveness as well as other goverment missions. High data rate with high speed transmission has been required for networking and high performance computing application, the chip size and package design has been become larger and larger. Accompanied by the big size design with package, the physical limits has the high cost for the advanced silicon node. The demand for higher functionality devices drives integration technologies to overcome limitations in Moore’s Law. Heterogeneous integration is the one of technologies to meet high performance computing application standards using high bandwidth and Input/Output (I/O) density. The split die of integration in package is the best solution to increase gross die with wafer good yield rate for cost efficiency, and Fan-out Embedded Bridge (FO-EB) Package would be the best representative for HPC and Networking application.The FO-EB is meaning spilt dies with embedded bridge die in fan out package which Inter Connect Die (ICD) become silicon bridge die to do the communications for high electrical performance purpose. Comparing with 2.5D package and FO-MCM package, FO-EB package warpage not only close with 2.5D package, but also better than FO-MCM (Fan-out Multi Chip Module) package. Besides, the electrical performance for high bandwidth memory as good as 2.5D package and FO-MCM package. The FO-EB package has integrated silicon ICD which means provide interconnections between spilt dies with short distance and the package model is more flexable than 2.5D package. That is why FO-EB would be the better choice for HPC and Networking application.The reason we choose FO-EB because it can contribute the same electrical performance to 2.5D package with FO-MCM package and the package warpgae well to be controlled. In this paper, we like to discuss a designed to evaluate the FO-EB and do the measurement comparsion for the warpage, and do the electrical preformance comparsion for the 2.5D, FO-EB and FO-MCM packages. Finally, this paper will find out the chiplets Integrated solution with FO-EB Package in HPC and Networking Application.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115964006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00363
Dylan Richmond, E. Enakerakpo, M. Alhendi, Peter McClure, M. Poliks
Damage and defects that occur in printed circuit board assembly (PCBA) often lead to the disposal of expensive components. In cases where laminate and circuitry have been removed, traditional repairs in the manufacturing process have not been able to return devices into service. This study examines the use of aerosol jet printing (AJP) and traditional engineering fluid dispensing (EFD) as methods to service repairs of damaged PCBAs.Surface mount component failures on PCBAs may occur as a result of a bad solder joint or problems with the component. In order to salvage such a PCBA, the component must be physically removed from the board and a new be attached. During the removal of PCBA components, pad cratering may occur, where the pad and laminate are damaged/removed along with the component. This leaves behind a crater in place of the pad, rendering the board unrepairable and thus, unusable. Trace damage is another common failure in PCBs. A repair to either sort of damage often requires reconnections of intricate circuitry to be made. Trace repair has traditionally been serviced by soldering a wire between the undamaged regions, rerouting the connection. In the case of fine conductive traces, as seen in devices which are becoming smaller as heterogeneous packaging innovations continue to progress, traditional methods will not be able to service this sort of damage.Aerosol jet printing, a direct-write additive manufacturing process commonly used in flexible hybrid electronics, could save expensive PCBs by repairing cratered pads and damaged traces. The use of AJP has been successful in repairing damaged modules, however the process has not been optimized for general repairs on FR4. The use of AJP and EFD to repair damaged circuitry on FR4 laminate and to fill pad craters with copper nanoparticle ink is demonstrated. Copper ink structures are uniformly sintered to achieve a solderable surface and good adhesion to the exposed laminate and remaining copper on the PCB. Processing conditions and methods to minimize voiding, cracking, and oxidation are discussed. The confined dimensions of the craters bring additional challenges to printing and curing as large structures are desired, but require tailored drying and sintering schedules to ensure good adhesion and minimize voids.
{"title":"Methods of Printing Copper for PCB Repair","authors":"Dylan Richmond, E. Enakerakpo, M. Alhendi, Peter McClure, M. Poliks","doi":"10.1109/ectc51906.2022.00363","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00363","url":null,"abstract":"Damage and defects that occur in printed circuit board assembly (PCBA) often lead to the disposal of expensive components. In cases where laminate and circuitry have been removed, traditional repairs in the manufacturing process have not been able to return devices into service. This study examines the use of aerosol jet printing (AJP) and traditional engineering fluid dispensing (EFD) as methods to service repairs of damaged PCBAs.Surface mount component failures on PCBAs may occur as a result of a bad solder joint or problems with the component. In order to salvage such a PCBA, the component must be physically removed from the board and a new be attached. During the removal of PCBA components, pad cratering may occur, where the pad and laminate are damaged/removed along with the component. This leaves behind a crater in place of the pad, rendering the board unrepairable and thus, unusable. Trace damage is another common failure in PCBs. A repair to either sort of damage often requires reconnections of intricate circuitry to be made. Trace repair has traditionally been serviced by soldering a wire between the undamaged regions, rerouting the connection. In the case of fine conductive traces, as seen in devices which are becoming smaller as heterogeneous packaging innovations continue to progress, traditional methods will not be able to service this sort of damage.Aerosol jet printing, a direct-write additive manufacturing process commonly used in flexible hybrid electronics, could save expensive PCBs by repairing cratered pads and damaged traces. The use of AJP has been successful in repairing damaged modules, however the process has not been optimized for general repairs on FR4. The use of AJP and EFD to repair damaged circuitry on FR4 laminate and to fill pad craters with copper nanoparticle ink is demonstrated. Copper ink structures are uniformly sintered to achieve a solderable surface and good adhesion to the exposed laminate and remaining copper on the PCB. Processing conditions and methods to minimize voiding, cracking, and oxidation are discussed. The confined dimensions of the craters bring additional challenges to printing and curing as large structures are desired, but require tailored drying and sintering schedules to ensure good adhesion and minimize voids.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An encapsulated sample with high flexibility was demonstrated in this work, which decreased 99.98% of rigidity and had also passed through workability, reliability, and flexible endurance qualifications. This breakthrough has dramatically changed our traditional concept from rigid encapsulation to flexible encapsulation and provides more opportunities for assembly industry. Flexible encapsulation technology which is flexible, bendable, twistable, rollable and foldable had passed through reliability and severe flexible endurance tests. First of all, the flexible encapsulation material decrease 99.98% of rigidity and modulus compared to traditional EMC, which offers an opportunity for the encapsulated product to become flexible even after assembly. In addition, the flexible encapsulation material has good workability and can become massively productive by simple process within assembly industry. Furthermore, the flexibly encapsulated product had passed through several reliability challenges, such as six times multi-reflow with peak temperature of 260°C, preconditioning level 3 (168hours, 30°C, 60% room humidity), and temperature humidity test (THT) with strict condition (192hours, 85°C, 85% room humidity). Last but not least, the encapsulated product overcame the flexible endurance test (folding, rolling and twisting 100,000 cycles) which is impossible to be tested using traditionally encapsulated product.
{"title":"Demonstration of flexible encapsulation in assembly industry","authors":"Chao-Wei Liu, Ming-Hung Chen, Tun-Ching Pi, Jen-Chieh Kao, Yung-I Yeh","doi":"10.1109/ectc51906.2022.00161","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00161","url":null,"abstract":"An encapsulated sample with high flexibility was demonstrated in this work, which decreased 99.98% of rigidity and had also passed through workability, reliability, and flexible endurance qualifications. This breakthrough has dramatically changed our traditional concept from rigid encapsulation to flexible encapsulation and provides more opportunities for assembly industry. Flexible encapsulation technology which is flexible, bendable, twistable, rollable and foldable had passed through reliability and severe flexible endurance tests. First of all, the flexible encapsulation material decrease 99.98% of rigidity and modulus compared to traditional EMC, which offers an opportunity for the encapsulated product to become flexible even after assembly. In addition, the flexible encapsulation material has good workability and can become massively productive by simple process within assembly industry. Furthermore, the flexibly encapsulated product had passed through several reliability challenges, such as six times multi-reflow with peak temperature of 260°C, preconditioning level 3 (168hours, 30°C, 60% room humidity), and temperature humidity test (THT) with strict condition (192hours, 85°C, 85% room humidity). Last but not least, the encapsulated product overcame the flexible endurance test (folding, rolling and twisting 100,000 cycles) which is impossible to be tested using traditionally encapsulated product.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134143301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00125
M. Woehrmann, P. Mackowiak, M. Schiffer, K. Lang, M. Schneider-Ramelow
Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface’s fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.
{"title":"A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications","authors":"M. Woehrmann, P. Mackowiak, M. Schiffer, K. Lang, M. Schneider-Ramelow","doi":"10.1109/ectc51906.2022.00125","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00125","url":null,"abstract":"Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface’s fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133920780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Via-less interconnects are an interesting solution for communicating vertically across the interposer core instead of using through package vias. These interconnects could potentially reduce the cost and complexity of the fabrication of the inter-poser. In this paper, we discuss and compare the performance of wireless interconnects in glass using two different dielectric materials with the same stack-up: where one of the dielectrics is a dry film, Ajinomoto Build-up Film (ABF) GL102 and the other is a low-loss photo-imageable liquid dielectric material from JSR Corp. over a frequency range from 40-170 GHz. The stack-up is made up of 100 μm of glass (EN-A1) from AGC Inc. with 15 μm of the said dielectrics on either side of the glass. The paper characterizes the performance of the interconnects with an alignment offset from the top to the bottom layer. We use semi additive process (SAP) to form high precision redistribution layers (RDL), as compared to subtractive etching and printing techniques. As the probe pads are present on either side of the glass panel, we use L-2L de-embedding technique to extract the characteristics of a single via-less interconnect.
{"title":"Demonstration and Comparison of Vertical Via-less Interconnects in Laminated Glass Panels from 40-170 GHz","authors":"Lakshmi Narasimha Vijay Kumar, K. Moon, Madhavan Swaminathan, Kimiyuki Kanno, Hirokazu Ito, Taku Ogawa, Koichi Hasegawa","doi":"10.1109/ectc51906.2022.00360","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00360","url":null,"abstract":"Via-less interconnects are an interesting solution for communicating vertically across the interposer core instead of using through package vias. These interconnects could potentially reduce the cost and complexity of the fabrication of the inter-poser. In this paper, we discuss and compare the performance of wireless interconnects in glass using two different dielectric materials with the same stack-up: where one of the dielectrics is a dry film, Ajinomoto Build-up Film (ABF) GL102 and the other is a low-loss photo-imageable liquid dielectric material from JSR Corp. over a frequency range from 40-170 GHz. The stack-up is made up of 100 μm of glass (EN-A1) from AGC Inc. with 15 μm of the said dielectrics on either side of the glass. The paper characterizes the performance of the interconnects with an alignment offset from the top to the bottom layer. We use semi additive process (SAP) to form high precision redistribution layers (RDL), as compared to subtractive etching and printing techniques. As the probe pads are present on either side of the glass panel, we use L-2L de-embedding technique to extract the characteristics of a single via-less interconnect.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134172019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00105
A. Horibe, Takahito Watanabe, Chinami Marushima, H. Mori, S. Kohara, R. Yu, M. Bergendahl, T. Magbitang, R. Wojtecki, D. Taneja, M. Godard, Claudia Cristina Barrera Pulido, I. de Sousa, K. Sikka, T. Hisada
Direct Bonded Heterogeneous Integrated (DBHi) silicon-bridge packages use known standard bond and assembly processes but require special considerations with regards to the selection of bonding materials for the bridge chip. The DBHi chip-bridge subassemblies are prepared using thermocompression bonding (TCB) with non conductive paste (NCP). In this study, we identified that the NCP encapsulated micro joints in the DBHi silicon-bridge structure are under a unique stress condition through assembling experiments and thermomechanical analysis. We evaluated and compared the properties of different NCP materials using the test vehicles specially designed to emulate the unique stress condition. We demonstrated a reliable micro solder joint structure by selecting a NCP material showing optimal chemical reaction processes and by methodically designing the bonding conditions to mitigate the fracture failures of the solder joints in the DBHi silicon-bridge.
{"title":"Characterization of Non-Conductive Paste Materials (NCP) for Thermocompression Bonding in a Direct Bonded Heterogeneously Integrated (DBHi) Si- Bridge Package","authors":"A. Horibe, Takahito Watanabe, Chinami Marushima, H. Mori, S. Kohara, R. Yu, M. Bergendahl, T. Magbitang, R. Wojtecki, D. Taneja, M. Godard, Claudia Cristina Barrera Pulido, I. de Sousa, K. Sikka, T. Hisada","doi":"10.1109/ectc51906.2022.00105","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00105","url":null,"abstract":"Direct Bonded Heterogeneous Integrated (DBHi) silicon-bridge packages use known standard bond and assembly processes but require special considerations with regards to the selection of bonding materials for the bridge chip. The DBHi chip-bridge subassemblies are prepared using thermocompression bonding (TCB) with non conductive paste (NCP). In this study, we identified that the NCP encapsulated micro joints in the DBHi silicon-bridge structure are under a unique stress condition through assembling experiments and thermomechanical analysis. We evaluated and compared the properties of different NCP materials using the test vehicles specially designed to emulate the unique stress condition. We demonstrated a reliable micro solder joint structure by selecting a NCP material showing optimal chemical reaction processes and by methodically designing the bonding conditions to mitigate the fracture failures of the solder joints in the DBHi silicon-bridge.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00237
J. Ha, Chongyang Cai, Pengcheng Yin, Yangyang Lai, K. Pan, Junbo Yang, Seungbae Park
This study is attempted to correlate between solder joint shape and fatigue life in experimental and numerical approaches. The test assemblies consisting of R1005 (1.0 × 0.5 mm) and R0402 (0.4 × 0.2 mm) soldered with SAC 305 solder material are subjected to thermal shock loading (-55 °C to 150 °C, dwell time 3 min, 6 cycles per hour). In an effort to analyze the effect of solder joint shape on fatigue life, the test assemblies are printed with different solder paste volume which induces variations in solder joint shape. The variations observed on the solder volumes generated are categorized as concave, straight, tiny convex, and convex symmetrically which are essentially achieved using stencils with different opening sizes. Another variation that is induced artificially is having unsymmetrical solder paste volume on two copper pads of a single component. Group of passive components which induces variations in solder joint shape symmetry or asymmetry are monitored to measure the resistances during thermal shock test.
{"title":"Shape Dependency of Fatigue Life in Solder Joints of Chip Resistors","authors":"J. Ha, Chongyang Cai, Pengcheng Yin, Yangyang Lai, K. Pan, Junbo Yang, Seungbae Park","doi":"10.1109/ectc51906.2022.00237","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00237","url":null,"abstract":"This study is attempted to correlate between solder joint shape and fatigue life in experimental and numerical approaches. The test assemblies consisting of R1005 (1.0 × 0.5 mm) and R0402 (0.4 × 0.2 mm) soldered with SAC 305 solder material are subjected to thermal shock loading (-55 °C to 150 °C, dwell time 3 min, 6 cycles per hour). In an effort to analyze the effect of solder joint shape on fatigue life, the test assemblies are printed with different solder paste volume which induces variations in solder joint shape. The variations observed on the solder volumes generated are categorized as concave, straight, tiny convex, and convex symmetrically which are essentially achieved using stencils with different opening sizes. Another variation that is induced artificially is having unsymmetrical solder paste volume on two copper pads of a single component. Group of passive components which induces variations in solder joint shape symmetry or asymmetry are monitored to measure the resistances during thermal shock test.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00176
S. Liang, Gene Y. Wu, K. Yee, C. T. Wang, Ji James Cui, Douglas C. H. Yu
High Performance Computing (HPC) system integration has gained significant growth momentum with ever-increasing demands on data transfer bandwidth and computing performance in support of data center and high-end server for 5G and AI applications. Advanced AI computing system with a high energy efficient performance (EEP) and a wide interconnect bandwidth is highly desirable. Moore’s Law continues to push transistor scaling to improve power consumption and computing performance with both architecture and materials innovations. To sustain cost and performance benefits with economics of scale, semiconductor technology innovations have been accelerated from system scaling perspective, leveraging chiplets partition and 2D/3D reintegration, by enabling ultra-fine pitch 3DIC inter-chip stack.3DFabric™ system integration platform provides a full spectrum of advanced system integration technologies including 3DIC stacking (aka SoIC™), advanced packaging technologies (aka CoWoS and InFO) with advanced wafer node technology to unlock customer innovations for the next generation HPC. System on Integrated Chips (SoIC™) is a fronted-end 3D inter-chip stacking technology to achieve high interconnect density and high bandwidth with high energy efficiency. Scaling down in the SoIC bonding pitch is desirable to continuously improve EEP, interconnect density, data bandwidth and system form factor in 3D chiplets integration. There are many factors affecting the SoIC chip-on-wafer bonding quality, such as chip size, chip thickness, process thermal budget, metal density, warpage control, wafer dicing quality, surface treatment conditions, bond tool accuracy and particle control. Insightful understanding of advanced node wafer, process tools, materials, design enablement and good process control are essential to achieve 3D ultra-fine pitch SoIC bond with high yield and high reliability.In this paper, we present for the first time a 3um bond pitch, face-to-face, chip-on-wafer SoIC integration study with low thermal budget. Test vehicle chips in this study are 6 x 6 mm2 in size, with full array interconnects. Daisy chains and Kelvin structure are built-in for chip level leakage test and resistance measurement. Electrical yield validation by wafer acceptance test (WAT) is used for process stability check. EEP analysis, Cu compressive stress prediction and chip level reliability test are also addressed in this study.
高性能计算(High Performance Computing, HPC)系统集成获得显著增长势头，支持5G和人工智能应用的数据中心和高端服务器，对数据传输带宽和计算性能的需求不断提高。具有高能效(EEP)和宽互连带宽的先进人工智能计算系统是非常可取的。摩尔定律继续推动晶体管的缩放，通过架构和材料的创新来提高功耗和计算性能。为了保持规模经济的成本和性能优势，半导体技术创新已经从系统扩展的角度加速，通过实现超细间距3DIC芯片间堆栈，利用小芯片分区和2D/3D整合。3DFabric™系统集成平台提供了全方位的先进系统集成技术，包括3DIC堆叠(又名SoIC™)，先进的封装技术(又名CoWoS和InFO)与先进的晶圆节点技术，以解锁客户的创新下一代高性能计算。系统集成芯片(SoIC™)是一种前端3D芯片间堆叠技术，可实现高互连密度、高带宽和高能效。在3D小芯片集成中，减小SoIC键合间距是不断提高EEP、互连密度、数据带宽和系统外形因子的理想选择。影响SoIC片上键合质量的因素有很多，如芯片尺寸、芯片厚度、工艺热预算、金属密度、翘曲控制、晶圆切割质量、表面处理条件、键合工具精度和颗粒控制。对先进节点晶圆、工艺工具、材料、设计支持和良好的工艺控制的深刻理解是实现高良率和高可靠性的3D超细间距SoIC键合的必要条件。在本文中，我们首次提出了一个3um键距、面对面、低热预算的片上SoIC集成研究。本研究中测试车辆芯片的尺寸为6 x 6 mm2，具有全阵列互连。菊花链和开尔文结构内置芯片级泄漏测试和电阻测量。通过晶圆验收试验(WAT)进行的电气良率验证用于工艺稳定性检查。本文还对电阻抗分析、铜压应力预测和芯片级可靠性试验进行了研究。
{"title":"High Performance and Energy Efficient Computing with Advanced SoIC™ Scaling","authors":"S. Liang, Gene Y. Wu, K. Yee, C. T. Wang, Ji James Cui, Douglas C. H. Yu","doi":"10.1109/ectc51906.2022.00176","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00176","url":null,"abstract":"High Performance Computing (HPC) system integration has gained significant growth momentum with ever-increasing demands on data transfer bandwidth and computing performance in support of data center and high-end server for 5G and AI applications. Advanced AI computing system with a high energy efficient performance (EEP) and a wide interconnect bandwidth is highly desirable. Moore’s Law continues to push transistor scaling to improve power consumption and computing performance with both architecture and materials innovations. To sustain cost and performance benefits with economics of scale, semiconductor technology innovations have been accelerated from system scaling perspective, leveraging chiplets partition and 2D/3D reintegration, by enabling ultra-fine pitch 3DIC inter-chip stack.3DFabric™ system integration platform provides a full spectrum of advanced system integration technologies including 3DIC stacking (aka SoIC™), advanced packaging technologies (aka CoWoS and InFO) with advanced wafer node technology to unlock customer innovations for the next generation HPC. System on Integrated Chips (SoIC™) is a fronted-end 3D inter-chip stacking technology to achieve high interconnect density and high bandwidth with high energy efficiency. Scaling down in the SoIC bonding pitch is desirable to continuously improve EEP, interconnect density, data bandwidth and system form factor in 3D chiplets integration. There are many factors affecting the SoIC chip-on-wafer bonding quality, such as chip size, chip thickness, process thermal budget, metal density, warpage control, wafer dicing quality, surface treatment conditions, bond tool accuracy and particle control. Insightful understanding of advanced node wafer, process tools, materials, design enablement and good process control are essential to achieve 3D ultra-fine pitch SoIC bond with high yield and high reliability.In this paper, we present for the first time a 3um bond pitch, face-to-face, chip-on-wafer SoIC integration study with low thermal budget. Test vehicle chips in this study are 6 x 6 mm2 in size, with full array interconnects. Daisy chains and Kelvin structure are built-in for chip level leakage test and resistance measurement. Electrical yield validation by wafer acceptance test (WAT) is used for process stability check. EEP analysis, Cu compressive stress prediction and chip level reliability test are also addressed in this study.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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