Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00256
F. Che, Yeow Chon Ong, H. Ng, L. Pan, Christopher D. Glancey, K. Sinha, Richard Fan
First failure (FF) fatigue life model of lead-free solder is not available from literature, especially for package used in mobile application. In this study, fatigue life model for FF prediction under temperature cycling test has been developed for low-Ag content solder joint used in board level assembly through reliability test and finite element analysis and simulation. The developed life model is validated and has a good accuracy with +/-20% error between prediction and physical testing data. Volume selection is discussed for better understanding the failure mode and site. Relationship between FF and characteristic life is also studied.
{"title":"Development on Fatigue Life Model of Lead-Free Solder for First Failure Prediction","authors":"F. Che, Yeow Chon Ong, H. Ng, L. Pan, Christopher D. Glancey, K. Sinha, Richard Fan","doi":"10.1109/ectc51906.2022.00256","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00256","url":null,"abstract":"First failure (FF) fatigue life model of lead-free solder is not available from literature, especially for package used in mobile application. In this study, fatigue life model for FF prediction under temperature cycling test has been developed for low-Ag content solder joint used in board level assembly through reliability test and finite element analysis and simulation. The developed life model is validated and has a good accuracy with +/-20% error between prediction and physical testing data. Volume selection is discussed for better understanding the failure mode and site. Relationship between FF and characteristic life is also studied.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00055
Je-An Yu, Dongsu Kim, Insub Han, J. Yook
In this work, we propose a Ni-Zn ferrite core embedding process in a photosensitive glass substrate and demonstrate the design and fabrication of substrate embedded inductors and integrated voltage regulators (IVRs) using the substrate embedded ferrite cores. We developed a ferrite core embedding process inside a vertical cavity of a photosensitive glass substrate, so that ferrite core solenoid inductors can be embedded in the substrate. The measured inductance, DC resistance and Q-factor of a 1600μm × 1500μm ferrite core inductor were 209nH, 240mOhm, 15.8 at 18.2Mhz respectively. And a 920μm × 1050μm inductor has inductance of 252nH, DC resistance of 663mOhm, and Q-factor of 16.6 at 20Mhz. The power conversion efficiency of an integrated voltage regulator module was measured up to 85.2%.
{"title":"Demonstration of Substrate Embedded Ni-Zn Ferrite Core Solenoid Inductors Using a Photosensitive Glass Substrate","authors":"Je-An Yu, Dongsu Kim, Insub Han, J. Yook","doi":"10.1109/ectc51906.2022.00055","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00055","url":null,"abstract":"In this work, we propose a Ni-Zn ferrite core embedding process in a photosensitive glass substrate and demonstrate the design and fabrication of substrate embedded inductors and integrated voltage regulators (IVRs) using the substrate embedded ferrite cores. We developed a ferrite core embedding process inside a vertical cavity of a photosensitive glass substrate, so that ferrite core solenoid inductors can be embedded in the substrate. The measured inductance, DC resistance and Q-factor of a 1600μm × 1500μm ferrite core inductor were 209nH, 240mOhm, 15.8 at 18.2Mhz respectively. And a 920μm × 1050μm inductor has inductance of 252nH, DC resistance of 663mOhm, and Q-factor of 16.6 at 20Mhz. The power conversion efficiency of an integrated voltage regulator module was measured up to 85.2%.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00320
V. S. Bhaskar, Jong Ming Chinq, Kazunori Yamamoto, G. Tang
In this paper, electrical design and modeling of silicon carbide power modules for inverter applications are discussed. A 6-in-l silicon carbide MOSFET power module is proposed, and its package is described and analyzed. The electrical design and modeling are done using Ansys Q3D simulation to extract the parasitic inductances and capacitances. The computed power loop inductance is 6.21 nH, gate loop inductance is 1.94 nH, while the parasitic capacitance is 29.98 pF.
{"title":"Electrical Design and Modeling of Silicon Carbide Power Modules for Inverter Applications","authors":"V. S. Bhaskar, Jong Ming Chinq, Kazunori Yamamoto, G. Tang","doi":"10.1109/ectc51906.2022.00320","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00320","url":null,"abstract":"In this paper, electrical design and modeling of silicon carbide power modules for inverter applications are discussed. A 6-in-l silicon carbide MOSFET power module is proposed, and its package is described and analyzed. The electrical design and modeling are done using Ansys Q3D simulation to extract the parasitic inductances and capacitances. The computed power loop inductance is 6.21 nH, gate loop inductance is 1.94 nH, while the parasitic capacitance is 29.98 pF.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"92 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114318402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00338
F. Libsch, H. Mori, X. Gu
The focus of this work encompasses signal integrity (SI) design and analysis in hybrid integration of the latest generation of High Bandwidth Memory (HBM2E) onto the latest generation high density Organic Package now capable of 1.5um line and space interconnects. In this paper, for the first time, we design and analyze the whole system HBM2E link budget components on latest generation high density Organic Package where the methodology details all the interconnect signal uncertainties.
{"title":"Signal Integrity Design and Analysis with Link Budget Results of HBM2E Module on Latest High Density Organic Laminate","authors":"F. Libsch, H. Mori, X. Gu","doi":"10.1109/ectc51906.2022.00338","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00338","url":null,"abstract":"The focus of this work encompasses signal integrity (SI) design and analysis in hybrid integration of the latest generation of High Bandwidth Memory (HBM2E) onto the latest generation high density Organic Package now capable of 1.5um line and space interconnects. In this paper, for the first time, we design and analyze the whole system HBM2E link budget components on latest generation high density Organic Package where the methodology details all the interconnect signal uncertainties.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00239
T. Uhrmann, B. Povazay, T. Zenger, Bemd Thallner, R. Holly, Bozena Matuskova Lednicka, Mario Reybrouck, Niels Van Herck, Bart Persijn, D. Janssen, S. Vanclooster, Stef Heirbaut
The updated roadmap for advanced packaging shows an increased need for denser next-generation heterogeneous integration designs. With the goal of further reducing the currently achieved via diameters in critical dielectric layers tailored for FOWLP, we evaluated high performing polyimide (PI) and polybenzoxazole (PBO) materials using a maskless exposure lithography system that enables instant design changes.
{"title":"Optimization of PI & PBO Layers Lithography Process for High Density Fan-Out Wafer Level Packaging & Next Generation Heterogeneous Integration Applications Employing Digitally Driven Maskless Lithography","authors":"T. Uhrmann, B. Povazay, T. Zenger, Bemd Thallner, R. Holly, Bozena Matuskova Lednicka, Mario Reybrouck, Niels Van Herck, Bart Persijn, D. Janssen, S. Vanclooster, Stef Heirbaut","doi":"10.1109/ectc51906.2022.00239","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00239","url":null,"abstract":"The updated roadmap for advanced packaging shows an increased need for denser next-generation heterogeneous integration designs. With the goal of further reducing the currently achieved via diameters in critical dielectric layers tailored for FOWLP, we evaluated high performing polyimide (PI) and polybenzoxazole (PBO) materials using a maskless exposure lithography system that enables instant design changes.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00349
L. Wai, Kazunori Yamamoto, G. Tang, Jacob Jordon Soh
The process development of a novel pressure-assist pates for high performance silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) was carried out. In this study, high shear strength on silver sintered die attach layer can be achieved. Interconnect process developed for gate pad (pad size = 0.8mm x 0.5mm) and source pad (pad size= 1.04mmx3.97mm) with copper clips and tin antimony (SnSb) solder passed the criteria of power cycling test. Highly densify silver sintered layer can be achieved by pressure-laser sintering process for pressure-assist type silver sintering paste.
{"title":"Pressure-assist Silver Sintering Paste for SiC Power Device Attachment on Lead Frame Based Package","authors":"L. Wai, Kazunori Yamamoto, G. Tang, Jacob Jordon Soh","doi":"10.1109/ectc51906.2022.00349","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00349","url":null,"abstract":"The process development of a novel pressure-assist pates for high performance silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) was carried out. In this study, high shear strength on silver sintered die attach layer can be achieved. Interconnect process developed for gate pad (pad size = 0.8mm x 0.5mm) and source pad (pad size= 1.04mmx3.97mm) with copper clips and tin antimony (SnSb) solder passed the criteria of power cycling test. Highly densify silver sintered layer can be achieved by pressure-laser sintering process for pressure-assist type silver sintering paste.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00150
Yihang Chu, Yamini Kotriwar, Ethan Kepros, Brian Wright, P. Chahal
This paper investigates the use of additive manufacturing (AM) for the fabrication of hollow or air substrate integrated waveguides (SIW or reduced height waveguides). The method relies on additive manufacturing (3-D fabrication) using a simple resin printer. A bandpass filter and a slot antenna working in the X-band are demonstrated. The simulation and measured results match closely and show that low-cost table top resin printers can fabricate microwave passive components with good performance.
{"title":"X-band Passive Circuits Using 3-D Printed Hollow Substrate Integrated Waveguides","authors":"Yihang Chu, Yamini Kotriwar, Ethan Kepros, Brian Wright, P. Chahal","doi":"10.1109/ectc51906.2022.00150","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00150","url":null,"abstract":"This paper investigates the use of additive manufacturing (AM) for the fabrication of hollow or air substrate integrated waveguides (SIW or reduced height waveguides). The method relies on additive manufacturing (3-D fabrication) using a simple resin printer. A bandpass filter and a slot antenna working in the X-band are demonstrated. The simulation and measured results match closely and show that low-cost table top resin printers can fabricate microwave passive components with good performance.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00067
N. P. Gaunkar, G. Dogiamis, T. Kamgaing, A. Elsherbini, J. Swan
A multi-layer, organic, low-loss flip-chip chip-scale package (FCCSP) for sub-THz applications has been developed and validated with on-package passive structures operating in the frequency band of 100 GHz to 140 GHz. The designed package co-integrates an electromagnetic wave launcher, a dual band multiplexer and a wideband through package transition. The wave launcher includes two rectangular patches separated by dielectric layers and supports a radiation bandwidth of 40 GHz. It has a return loss better than 10 dB in the designed bandwidth and an insertion loss between 1 to 1.5 dB. The on-package multiplexer (diplexer) combines two bandpass hairpin resonator filters. The two filters are designed to have a minimum bandwidth of 12 GHz each. The designed diplexer also has a return loss better than 10 dB and an insertion loss between 4 to 5 dB. Our work is a leading demonstrator for FCCSP packaging in the 100 to 140 GHz frequency range. We show that with the current fabrication processes, organic packaging is a valuable low-loss solution for sub-THz millimeter wave applications.
{"title":"Multi-layer FCCSP organic packaging for D-band millimeter wave applications","authors":"N. P. Gaunkar, G. Dogiamis, T. Kamgaing, A. Elsherbini, J. Swan","doi":"10.1109/ectc51906.2022.00067","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00067","url":null,"abstract":"A multi-layer, organic, low-loss flip-chip chip-scale package (FCCSP) for sub-THz applications has been developed and validated with on-package passive structures operating in the frequency band of 100 GHz to 140 GHz. The designed package co-integrates an electromagnetic wave launcher, a dual band multiplexer and a wideband through package transition. The wave launcher includes two rectangular patches separated by dielectric layers and supports a radiation bandwidth of 40 GHz. It has a return loss better than 10 dB in the designed bandwidth and an insertion loss between 1 to 1.5 dB. The on-package multiplexer (diplexer) combines two bandpass hairpin resonator filters. The two filters are designed to have a minimum bandwidth of 12 GHz each. The designed diplexer also has a return loss better than 10 dB and an insertion loss between 4 to 5 dB. Our work is a leading demonstrator for FCCSP packaging in the 100 to 140 GHz frequency range. We show that with the current fabrication processes, organic packaging is a valuable low-loss solution for sub-THz millimeter wave applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129861446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00132
Cong Gan, Hai-Jun Huang, Bin Hou, Min-bo Zhou, Xin-Ping Zhang
In this work, bimodal Cu particles have been synthesized by using 2-amino-2-methyl-1-propanol (AMP)-based hybrid capping agent for the first time. A novel hybrid Cu ink is prepared by combining bimodal Cu particles with solvents and Cu-based metal-organic decomposition (MOD) ink composed of Cu(II) formate, AMP and octylamine. The printed Cu patterns (films) by using the hybrid Cu ink show resistivity as low as 60 μΩ•cm after sintering under mid processing conditions (e.g., sintering at 110°C for 20 min in nitrogen atmosphere). The results also show that sintered Cu films of the hybrid Cu ink have good adhesion property on glass, polyimide (PI) and polyethylene terephthalate (PET) substrates, and the flexible Cu circuits on flattening and bending PI or PET substrates play the function well, in terms of easily lighting LEDs (light emitting diodes) in the circuits. Finally, the wearable strain sensor fabricated by using the hybrid Cu ink can also be well used to monitor the movement of human finger. All these results show that the hybrid Cu ink has high potential for application in printed flexible electronics.
{"title":"Fabrication of wearable strain sensor by using a novel hybrid Cu ink composed of bimodal Cu particle ink and Cu-based metal-organic decomposition ink","authors":"Cong Gan, Hai-Jun Huang, Bin Hou, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ectc51906.2022.00132","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00132","url":null,"abstract":"In this work, bimodal Cu particles have been synthesized by using 2-amino-2-methyl-1-propanol (AMP)-based hybrid capping agent for the first time. A novel hybrid Cu ink is prepared by combining bimodal Cu particles with solvents and Cu-based metal-organic decomposition (MOD) ink composed of Cu(II) formate, AMP and octylamine. The printed Cu patterns (films) by using the hybrid Cu ink show resistivity as low as 60 μΩ•cm after sintering under mid processing conditions (e.g., sintering at 110°C for 20 min in nitrogen atmosphere). The results also show that sintered Cu films of the hybrid Cu ink have good adhesion property on glass, polyimide (PI) and polyethylene terephthalate (PET) substrates, and the flexible Cu circuits on flattening and bending PI or PET substrates play the function well, in terms of easily lighting LEDs (light emitting diodes) in the circuits. Finally, the wearable strain sensor fabricated by using the hybrid Cu ink can also be well used to monitor the movement of human finger. All these results show that the hybrid Cu ink has high potential for application in printed flexible electronics.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127872034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00068
Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali
Antenna-in-Package (AiP) has emerged as a mainstream technology for millimeter-wave (mmWave) front-end modules driving it to meet future requirements. This paper discusses, for the first time, the design, modeling, and characterization of a slot bow-tie antenna (SBT) integrated into an embedded die enhanced quad flat no-lead (EDeQFN) package along with a comparison of a flip-chip version of the eQFN in WR8 (90GHz-140GHz) and WR5 (140GHz-220GHz) frequency bands. Further, a brief description of the design, modeling, and simulation results of mmWave chip-to-package transitions, transmission line structures, and antenna feed elements are provided. The insertion and return losses of these structures are less than 1.07dB and greater than 17dB, respectively for FCeQFN, less than 0.87dB, and greater than 22dB, respectively for EDeQFN package. The bandwidth and gain of the integrated SBT antenna in the above packages are 40GHz and 80GHz, with a peak gain of 7dBi and 7.7dBi in the WR8 and WR5 band, respectively. A brief description of the designed test vehicles, probing and measurement methodology for antenna bandwidth, and radiation pattern characterization in the WR5 frequency band is also presented.
{"title":"Slot Bow-Tie Antenna Integration in Flip-Chip and Embedded Die Enhanced QFN Package for WR8 and WR5 Frequency Bands","authors":"Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali","doi":"10.1109/ectc51906.2022.00068","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00068","url":null,"abstract":"Antenna-in-Package (AiP) has emerged as a mainstream technology for millimeter-wave (mmWave) front-end modules driving it to meet future requirements. This paper discusses, for the first time, the design, modeling, and characterization of a slot bow-tie antenna (SBT) integrated into an embedded die enhanced quad flat no-lead (EDeQFN) package along with a comparison of a flip-chip version of the eQFN in WR8 (90GHz-140GHz) and WR5 (140GHz-220GHz) frequency bands. Further, a brief description of the design, modeling, and simulation results of mmWave chip-to-package transitions, transmission line structures, and antenna feed elements are provided. The insertion and return losses of these structures are less than 1.07dB and greater than 17dB, respectively for FCeQFN, less than 0.87dB, and greater than 22dB, respectively for EDeQFN package. The bandwidth and gain of the integrated SBT antenna in the above packages are 40GHz and 80GHz, with a peak gain of 7dBi and 7.7dBi in the WR8 and WR5 band, respectively. A brief description of the designed test vehicles, probing and measurement methodology for antenna bandwidth, and radiation pattern characterization in the WR5 frequency band is also presented.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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