Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00308
Daisuke Hironiwa, Haw Wen Chen, Y. Morikawa, Takashi Kurimoto, R. Kamimura
With the increasing demand for high-performance devices, the achievement of high-density package products become a crucial topic. However, the scale of semiconductor chips is difficult to miniature furthermore. Against this background, the technology of the semiconductor packages is focused to improve device performance. The package structure changes greatly depending on the intended use of the device. Thus, the process of miniaturizing the wiring layer is an important item to improve the performance of almost packaged products. This report describes plasma treatment for the fabrication of redistribution layer (RDL) using photosensitive polyimide (PI) by the dry ashing equipment with the method of surface wave plasma (SWP) and capacitively coupled plasma (CCP). In order to fabricate a high-performance RDL, it is necessary to control the surface situation of copper wiring, PI, and photoresist (PR) more delicately than ever before. In this paper, we report the survey results for each process to fabricate RDL.
{"title":"The investigation of dry plasma technology in each steps for the fabrication of high performance redistribution layer","authors":"Daisuke Hironiwa, Haw Wen Chen, Y. Morikawa, Takashi Kurimoto, R. Kamimura","doi":"10.1109/ectc51906.2022.00308","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00308","url":null,"abstract":"With the increasing demand for high-performance devices, the achievement of high-density package products become a crucial topic. However, the scale of semiconductor chips is difficult to miniature furthermore. Against this background, the technology of the semiconductor packages is focused to improve device performance. The package structure changes greatly depending on the intended use of the device. Thus, the process of miniaturizing the wiring layer is an important item to improve the performance of almost packaged products. This report describes plasma treatment for the fabrication of redistribution layer (RDL) using photosensitive polyimide (PI) by the dry ashing equipment with the method of surface wave plasma (SWP) and capacitively coupled plasma (CCP). In order to fabricate a high-performance RDL, it is necessary to control the surface situation of copper wiring, PI, and photoresist (PR) more delicately than ever before. In this paper, we report the survey results for each process to fabricate RDL.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00280
Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov
In this paper, a simplified methodology is presented for the evaluation of test-to-failure board-level random vibrations using a combination of experimental and finite element modeling techniques in calculating equivalent stresses for SAC305 solder joints experiencing high- and ultra-high-cycle fatigue usually found in the emerging automotive robo-taxi industry. Some partial results that were obtained during this study allow for an investigation of the effects of a printed circuit board geometry on possible failure modes of Pb-free solder joints. These results seem to confirm the findings that have been reported previously by some researchers on the migration of a failure mode from the ductile fracture in the bulk solder to the brittle fracture of the intermetallic compound (IMC) layer due to the positive correlation between the tensile strength of the solder joint and the strain rate which may have occurred from high level of vibration and shock during the test. The generated data points were then compared to the existing S-N (stress-life) fatigue curves for the SAC305 solder joints in order to assess whether these curves can provide adequate results for the test vehicles fatigue life calculations. These preliminary results show that more work is needed in both verifying the effect of a failure mode migration in the solder joints as well as developing additional data points for S-N curve generation. This research is a continuation of the study initiated by the JEDEC JESD22 working group.
{"title":"Solder Joint Fatigue Studies Subjected to Board-level Random Vibration for Automotive Applications","authors":"Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov","doi":"10.1109/ectc51906.2022.00280","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00280","url":null,"abstract":"In this paper, a simplified methodology is presented for the evaluation of test-to-failure board-level random vibrations using a combination of experimental and finite element modeling techniques in calculating equivalent stresses for SAC305 solder joints experiencing high- and ultra-high-cycle fatigue usually found in the emerging automotive robo-taxi industry. Some partial results that were obtained during this study allow for an investigation of the effects of a printed circuit board geometry on possible failure modes of Pb-free solder joints. These results seem to confirm the findings that have been reported previously by some researchers on the migration of a failure mode from the ductile fracture in the bulk solder to the brittle fracture of the intermetallic compound (IMC) layer due to the positive correlation between the tensile strength of the solder joint and the strain rate which may have occurred from high level of vibration and shock during the test. The generated data points were then compared to the existing S-N (stress-life) fatigue curves for the SAC305 solder joints in order to assess whether these curves can provide adequate results for the test vehicles fatigue life calculations. These preliminary results show that more work is needed in both verifying the effect of a failure mode migration in the solder joints as well as developing additional data points for S-N curve generation. This research is a continuation of the study initiated by the JEDEC JESD22 working group.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00074
Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya
Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.
{"title":"A Novel Packaging Platform for High-Performance Optical Engines in Hyperscale Data Center Applications","authors":"Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya","doi":"10.1109/ectc51906.2022.00074","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00074","url":null,"abstract":"Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116632129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00214
M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li
This paper proposes a chiplet-based domain specific architecture (DSA) module on active interposer for convolutions in various scenarios. By constructing an integral development frame, the I/O and inter-chiplet links behaviors together with signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues can be co-considered and co-analyzed in the early phases, facilitating efficient implementation of heterogeneous integration. Additionally, the proposed solution takes advantage of the flexibility of a novel network-on-chip (NoC) switching fabric for inter-chiplet data exchange and versatile auxiliary circuitry enabled by an active interposer, to enhance its performance and extend the scope of application. The design and analysis results are shown, as well as associated options and potentials of the development frame. Up to now, the prototype chip samples for the switching fabric has been delivered by foundry; detailed physical design and assembly of the DSA module with off-the-shell dies and cost- effective Si interposer solution are under way.
{"title":"Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer","authors":"M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li","doi":"10.1109/ectc51906.2022.00214","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00214","url":null,"abstract":"This paper proposes a chiplet-based domain specific architecture (DSA) module on active interposer for convolutions in various scenarios. By constructing an integral development frame, the I/O and inter-chiplet links behaviors together with signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues can be co-considered and co-analyzed in the early phases, facilitating efficient implementation of heterogeneous integration. Additionally, the proposed solution takes advantage of the flexibility of a novel network-on-chip (NoC) switching fabric for inter-chiplet data exchange and versatile auxiliary circuitry enabled by an active interposer, to enhance its performance and extend the scope of application. The design and analysis results are shown, as well as associated options and potentials of the development frame. Up to now, the prototype chip samples for the switching fabric has been delivered by foundry; detailed physical design and assembly of the DSA module with off-the-shell dies and cost- effective Si interposer solution are under way.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00258
Rathin Mandal, Kazunori Yamamoto, G. Tang
numerical modeling and simulation of temperature cycling test (TCT) and power cycling test (PCT) are applied to the design reliability analysis for a proposed 6-in-1 power module (PM) package. The fatigue life for both 95Sn5Sb solder interconnect and sintered Ag die attach (DA) joints under TCT and PCT conditions are calculated and compared with a reference power module package which has already passed the reliability test. The Coffin-mansion life model ductility factor is calculated from the test data for the reference power module and applied to the analysis of the fatigue life for the PM. The reliability of solder interconnect is in the same level as the reference module which passed the 1000 cycles of TCT and 50000 cycles of PCT. Sintered Ag DA joint has a very high reliability life. The structural reliability of interconnect for the proposed PM could be further enhanced by using sintered Ag as both DA and interconnect materials. Effect of package parameters such as DA and copper clip thickness are also investigated in this study. The results provided important guidelines for the PM package design.
{"title":"Mechanical simulation and modeling for reliability of 6-in-1 power module","authors":"Rathin Mandal, Kazunori Yamamoto, G. Tang","doi":"10.1109/ectc51906.2022.00258","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00258","url":null,"abstract":"numerical modeling and simulation of temperature cycling test (TCT) and power cycling test (PCT) are applied to the design reliability analysis for a proposed 6-in-1 power module (PM) package. The fatigue life for both 95Sn5Sb solder interconnect and sintered Ag die attach (DA) joints under TCT and PCT conditions are calculated and compared with a reference power module package which has already passed the reliability test. The Coffin-mansion life model ductility factor is calculated from the test data for the reference power module and applied to the analysis of the fatigue life for the PM. The reliability of solder interconnect is in the same level as the reference module which passed the 1000 cycles of TCT and 50000 cycles of PCT. Sintered Ag DA joint has a very high reliability life. The structural reliability of interconnect for the proposed PM could be further enhanced by using sintered Ag as both DA and interconnect materials. Effect of package parameters such as DA and copper clip thickness are also investigated in this study. The results provided important guidelines for the PM package design.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00194
K. Pan, C. Okoro, Yangyang Lai, Dhananjay Joshi, Seungbae Park, S. Pollard
This study investigates the thermomechanical response of the copper TGV during thermal cycling. Two different geometries of copper TGV, the fully-filled TGV and conformal TGV, are compared concerning their in-plane and out-of-plane deformation. The TGV samples were heated from room temperature (RT) 23 °C to 400 °C and then cooled to RT. The protrusion height of the copper TGV was recorded as a function of temperature, and unrecoverable copper protrusions were observed because of the creep of the copper at high temperatures. Two-dimensional digital image correlation (2D DIC) measurements were employed to obtain the in-plane deformation of the glass substrate near the copper TGV. It was found the copper protrusion height and the in-plane deformation of the glass substrate were significantly reduced in the conformal TGVs compared to the fully-filled TGVs.
{"title":"A comparative study of the thermomechanical reliability of fully-filled and conformal through-glass via","authors":"K. Pan, C. Okoro, Yangyang Lai, Dhananjay Joshi, Seungbae Park, S. Pollard","doi":"10.1109/ectc51906.2022.00194","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00194","url":null,"abstract":"This study investigates the thermomechanical response of the copper TGV during thermal cycling. Two different geometries of copper TGV, the fully-filled TGV and conformal TGV, are compared concerning their in-plane and out-of-plane deformation. The TGV samples were heated from room temperature (RT) 23 °C to 400 °C and then cooled to RT. The protrusion height of the copper TGV was recorded as a function of temperature, and unrecoverable copper protrusions were observed because of the creep of the copper at high temperatures. Two-dimensional digital image correlation (2D DIC) measurements were employed to obtain the in-plane deformation of the glass substrate near the copper TGV. It was found the copper protrusion height and the in-plane deformation of the glass substrate were significantly reduced in the conformal TGVs compared to the fully-filled TGVs.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00068
Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali
Antenna-in-Package (AiP) has emerged as a mainstream technology for millimeter-wave (mmWave) front-end modules driving it to meet future requirements. This paper discusses, for the first time, the design, modeling, and characterization of a slot bow-tie antenna (SBT) integrated into an embedded die enhanced quad flat no-lead (EDeQFN) package along with a comparison of a flip-chip version of the eQFN in WR8 (90GHz-140GHz) and WR5 (140GHz-220GHz) frequency bands. Further, a brief description of the design, modeling, and simulation results of mmWave chip-to-package transitions, transmission line structures, and antenna feed elements are provided. The insertion and return losses of these structures are less than 1.07dB and greater than 17dB, respectively for FCeQFN, less than 0.87dB, and greater than 22dB, respectively for EDeQFN package. The bandwidth and gain of the integrated SBT antenna in the above packages are 40GHz and 80GHz, with a peak gain of 7dBi and 7.7dBi in the WR8 and WR5 band, respectively. A brief description of the designed test vehicles, probing and measurement methodology for antenna bandwidth, and radiation pattern characterization in the WR5 frequency band is also presented.
{"title":"Slot Bow-Tie Antenna Integration in Flip-Chip and Embedded Die Enhanced QFN Package for WR8 and WR5 Frequency Bands","authors":"Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali","doi":"10.1109/ectc51906.2022.00068","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00068","url":null,"abstract":"Antenna-in-Package (AiP) has emerged as a mainstream technology for millimeter-wave (mmWave) front-end modules driving it to meet future requirements. This paper discusses, for the first time, the design, modeling, and characterization of a slot bow-tie antenna (SBT) integrated into an embedded die enhanced quad flat no-lead (EDeQFN) package along with a comparison of a flip-chip version of the eQFN in WR8 (90GHz-140GHz) and WR5 (140GHz-220GHz) frequency bands. Further, a brief description of the design, modeling, and simulation results of mmWave chip-to-package transitions, transmission line structures, and antenna feed elements are provided. The insertion and return losses of these structures are less than 1.07dB and greater than 17dB, respectively for FCeQFN, less than 0.87dB, and greater than 22dB, respectively for EDeQFN package. The bandwidth and gain of the integrated SBT antenna in the above packages are 40GHz and 80GHz, with a peak gain of 7dBi and 7.7dBi in the WR8 and WR5 band, respectively. A brief description of the designed test vehicles, probing and measurement methodology for antenna bandwidth, and radiation pattern characterization in the WR5 frequency band is also presented.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00032
P. Zhao, Hong Yu Li, Yu Dian Lim, W. Seit, L. Guidoni, C. S. Tan
In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices.
{"title":"The Integration of Grounding Plane into TSV Integrated Ion Trap for Efficient Thermal Management in Large Scale Quantum Computing Device","authors":"P. Zhao, Hong Yu Li, Yu Dian Lim, W. Seit, L. Guidoni, C. S. Tan","doi":"10.1109/ectc51906.2022.00032","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00032","url":null,"abstract":"In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132934478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00355
Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani
Nowadays, counterfeit integrated circuits (IC) are increasingly common due to the continuous growth of supply chain globalization. This supply chain vulnerability results in unreliable and insecure counterfeit ICs integrated into the end-user devices in many applications, including consumer, corporate, and military domains. Various methods such as aging detection sensors, Physical Unclonable Functions (PUFs), and hardware metering have been developed to detect such counterfeits before they become integrated into critical systems. However, several complicated aspects of detection and prevention limit their use as a stopgap to the counterfeit problem. Hence, there is a critical need for novel inspection and assurance techniques that require minimal or no additional changes/modifications to the device circuit or material while remaining low-cost per sample. In this paper, the possibility of using IC packaging material characterization for counterfeit detection is proved by a preliminary material survey between the counterfeit and authentic ICs. Diffuse Reflectance Infrared Fourier Transform Spectroscopy (DRIFT) is used as the material characterization in this research, and the material spectrums will be utilized for training machine learning classification models. Several machine learning classification methods will be tested, such as Linear discriminant analysis (LDA), Support Vector Machine (SVM), random forest(RF), and multi-layer perceptron (MLP). With the help of the Standard Normal Variate (SNV) data preprocessing and MPL model, over 92 percent accuracy of counterfeit versus genuine sample discrimination has been achieved. This proves the existence of packaging material differences between counterfeit and authentic IC samples.
{"title":"Machine Learning Assisted Counterfeit IC Detection through Non-destructive Infrared (IR) Spectroscopy Material Characterization","authors":"Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/ectc51906.2022.00355","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00355","url":null,"abstract":"Nowadays, counterfeit integrated circuits (IC) are increasingly common due to the continuous growth of supply chain globalization. This supply chain vulnerability results in unreliable and insecure counterfeit ICs integrated into the end-user devices in many applications, including consumer, corporate, and military domains. Various methods such as aging detection sensors, Physical Unclonable Functions (PUFs), and hardware metering have been developed to detect such counterfeits before they become integrated into critical systems. However, several complicated aspects of detection and prevention limit their use as a stopgap to the counterfeit problem. Hence, there is a critical need for novel inspection and assurance techniques that require minimal or no additional changes/modifications to the device circuit or material while remaining low-cost per sample. In this paper, the possibility of using IC packaging material characterization for counterfeit detection is proved by a preliminary material survey between the counterfeit and authentic ICs. Diffuse Reflectance Infrared Fourier Transform Spectroscopy (DRIFT) is used as the material characterization in this research, and the material spectrums will be utilized for training machine learning classification models. Several machine learning classification methods will be tested, such as Linear discriminant analysis (LDA), Support Vector Machine (SVM), random forest(RF), and multi-layer perceptron (MLP). With the help of the Standard Normal Variate (SNV) data preprocessing and MPL model, over 92 percent accuracy of counterfeit versus genuine sample discrimination has been achieved. This proves the existence of packaging material differences between counterfeit and authentic IC samples.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132322210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00293
Goeun Kim, Doohee Lim, Tamal Das, Eunjung Lee, S. You
This paper presents a system-level co-optimization approach with Chip Power Model based power integrity simulation of the power delivery network and jitter sensitivity transfer function (JTF). Due to the need to merge multiple power domains and to locate adjacent power domains close to each other for enhancing cost effectiveness and space efficiency, the coupling resonance severely affects the whole system. To meet the rigorous performance requirements, a system-level co-design is mandatory. An approach which analyzes the V-by-One IP circuit blocks and finds the critical path based on the JTF is suggested within the case studies. An on-chip level optimization to bring higher voltage controlled oscillator output frequency and to add sufficient On-die-cap was analyzed. In the off-chip design stage, various design modifications to split the power domain, reinforce the ground path, and add package decoupling capacitors were attempted to decrease total jitter by the JTF. Finally, a co-optimization design process workflow which controls the total jitter budgeting is presented. The total jitter is decreased by 68.49% compared to the worst design case.
本文提出了一种基于芯片功率模型的输电网络功率完整性仿真和抖动灵敏度传递函数(JTF)的系统级协同优化方法。由于需要合并多个功率域，并且为了提高成本效益和空间效率，需要对相邻功率域进行较近的定位，因此耦合共振严重影响了整个系统。为了满足严格的性能需求，系统级协同设计是必需的。在案例研究中，提出了一种基于JTF分析v by one IP电路块并找到关键路径的方法。分析了一种片上级优化方法，以提高压控振荡器的输出频率，并增加足够的片上电容。在片外设计阶段，为了减少JTF的总抖动，尝试了各种设计修改，以分割功率域、加强接地路径和添加封装去耦电容器。最后，提出了一种控制总抖动预算的协同优化设计流程。与最坏设计情况相比，总抖动减小了68.49%。
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