Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00329
Jisoo Hwang, James Jeong, Heejung Choi, Jun So Pak, Heeseok Lee, Minkyu Mike Kim, Ilryong Kim
In this paper, to improve PI (Power Integrity) performance of system-level PDN (Power Delivery Network), the optimal arrangement of various package decoupling capacitors and on-chip IPs (Intellectual Property) are analyzed from the co-design point of view. By applying decoupling capacitor to the package PDN, impedance peak of the system-level PDN can be lowered in the frequency domain, and so does the voltage drop in the time domain. In this paper, the PI performance improvement effect according to the location of the package decoupling capacitor is analyzed. Furthermore, it is confirmed that the inductance generated in the package PDN should be reduced to optimize the PI improvement effect of the package decoupling capacitor. A method to reduce the inductance of such package PDN, especially bump-to-decap inductance, is analyzed from the co-design point of view of on-chip PDN and package PDN. Therefore, in this paper, it is proposed what should be considered in the chip floorplanning stage for optimization of PDN from IP to DSC, especially for the case where DSC is applied.
{"title":"Analysis on Optimal Chip Floorplanning Considering Various Types of Decoupling Capacitors in Package PDN","authors":"Jisoo Hwang, James Jeong, Heejung Choi, Jun So Pak, Heeseok Lee, Minkyu Mike Kim, Ilryong Kim","doi":"10.1109/ectc51906.2022.00329","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00329","url":null,"abstract":"In this paper, to improve PI (Power Integrity) performance of system-level PDN (Power Delivery Network), the optimal arrangement of various package decoupling capacitors and on-chip IPs (Intellectual Property) are analyzed from the co-design point of view. By applying decoupling capacitor to the package PDN, impedance peak of the system-level PDN can be lowered in the frequency domain, and so does the voltage drop in the time domain. In this paper, the PI performance improvement effect according to the location of the package decoupling capacitor is analyzed. Furthermore, it is confirmed that the inductance generated in the package PDN should be reduced to optimize the PI improvement effect of the package decoupling capacitor. A method to reduce the inductance of such package PDN, especially bump-to-decap inductance, is analyzed from the co-design point of view of on-chip PDN and package PDN. Therefore, in this paper, it is proposed what should be considered in the chip floorplanning stage for optimization of PDN from IP to DSC, especially for the case where DSC is applied.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00085
Nathan Ip, N. Nejadsadeghi, C. Fonseca, Norifumi Kohama, Kimio Motoda
In semiconductor direct wafer bonding process, two silicon wafers are mechanically joined together by interfacial adhesion under room conditions. Accurate alignment between the two wafers along the bond interface is critical to achieve high device performances. This paper uses a coupled solid and fluid mechanics simulation model to study the wafer bonding dynamics. The results of this simulation model are studied in detail and compared against experimental data. This simulation model confirms the role of air viscosity in wafer bonding process. This model can help optimize key hardware features to improve process performance such as post-bond distortion.
{"title":"Multi-Physics Simulation of Wafer-to-Wafer Bonding Dynamics","authors":"Nathan Ip, N. Nejadsadeghi, C. Fonseca, Norifumi Kohama, Kimio Motoda","doi":"10.1109/ectc51906.2022.00085","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00085","url":null,"abstract":"In semiconductor direct wafer bonding process, two silicon wafers are mechanically joined together by interfacial adhesion under room conditions. Accurate alignment between the two wafers along the bond interface is critical to achieve high device performances. This paper uses a coupled solid and fluid mechanics simulation model to study the wafer bonding dynamics. The results of this simulation model are studied in detail and compared against experimental data. This simulation model confirms the role of air viscosity in wafer bonding process. This model can help optimize key hardware features to improve process performance such as post-bond distortion.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126408590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00211
Pao-Nan Lee, Yu-Chang Hsieh, Hung-Lun Lo, Chang-Ho Li, F. Huang, James Lin, Wei-Chu Hsu, Chen-Chao Wang
5G communication has been widely implemented since year 2020, especially for FR1 sub-6GHz range. Band n77, n78 and n79 are three critical bands in the 5G FR1 because of higher frequency and much wider bandwidth - This also brings new challenge on filter design. In this work, we propose a new structure which combines OSAT Fan-Out RDL inductors and foundry MIM capacitors to enhance filter performance. A 800 MHz LPF test vehicle indicates this new structure is able to sustain 38 dBm at least, which is better than 36 dBm in the conventional IPD. Band pass filters for band n77 and n79 are designed and fabricated by this new structure as well. The insertion loss is about 1.44 dB for band n77 and 2.07 dB for band n79; The maximum sustainable input power is 34 dBm for both n77 filter and n79 filter. Besides single filter, Fan-Out RDL can replace conventional coreless packaging substrate to realize a thinner RF FEM.
{"title":"Integration of Foundry MIM Capacitor and OSAT Fan-Out RDL for High Performance RF Filters","authors":"Pao-Nan Lee, Yu-Chang Hsieh, Hung-Lun Lo, Chang-Ho Li, F. Huang, James Lin, Wei-Chu Hsu, Chen-Chao Wang","doi":"10.1109/ectc51906.2022.00211","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00211","url":null,"abstract":"5G communication has been widely implemented since year 2020, especially for FR1 sub-6GHz range. Band n77, n78 and n79 are three critical bands in the 5G FR1 because of higher frequency and much wider bandwidth - This also brings new challenge on filter design. In this work, we propose a new structure which combines OSAT Fan-Out RDL inductors and foundry MIM capacitors to enhance filter performance. A 800 MHz LPF test vehicle indicates this new structure is able to sustain 38 dBm at least, which is better than 36 dBm in the conventional IPD. Band pass filters for band n77 and n79 are designed and fabricated by this new structure as well. The insertion loss is about 1.44 dB for band n77 and 2.07 dB for band n79; The maximum sustainable input power is 34 dBm for both n77 filter and n79 filter. Besides single filter, Fan-Out RDL can replace conventional coreless packaging substrate to realize a thinner RF FEM.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00272
Kuei Hsiao Kuo Frank, Shaun Xiao, Abram Hwang, Kui-Yu Chang, Jovi Chang, F. Chien
In this investigation, the effects of small polyimide open (PIO) size for bump electrical, mechanical and package reliability performances are discussed. The contact resistance (Rc) between under bump metal (UBM) and Aluminum pad (Al) is assessed with varied PIO size; 10μm, 15μm, 20μm, 30μm and 35μm. The Rc test vehicle with I/O connected by Al metal for 4- wire Kelvin measurement is designed for Rc data collection. The UBM size is fixed for different PIO size, copper post shear strength and failure modes for different ratio of PIO area to UBM area (2%~25%) are also analyzed. Two different re-passivation materials, one is high temperature cured PI (curing temperature>350C) which is the mainstream for Cu pillar bump; the other is low temperature cured stiffer (high modulus) PI (curing temperature<300 C) that is typically used for advanced fab node are selected for comparison.The effects of small PIO size in subsequent assembly and reliability are also studied. The package size of test vehicle is 196 mm2 with a daisy-chain die size of 11 x 11 mm2. The minimum bump pitch is 140μm. The UBM is fixed at 35x65μm for different PIO size; 10μm, 10x20μm, 20μm and 15x25μm to simulate typical bump design request. All the study legs of different PIO size were released to assembly and had been evaluated by employing package level thermal cycling test. The assembly and reliability performance were investigated by C-mode Scanning Acoustic Microscope (CSAM), Scanning Electron Microscope (SEM) and cross-section for each PIO leg.The study of this investigation is to know the effects of small PIO size to bump electrical, mechanical and chip package interaction to achieving robust Cu pillar interconnection in flip chip package.
本文讨论了小聚酰亚胺开口(PIO)尺寸对碰撞电性能、机械性能和封装可靠性的影响。在不同的PIO尺寸下，评估了碰撞金属(UBM)与铝衬垫(Al)之间的接触电阻(Rc);10μm、15μm、20μm、30μm、35μm。设计了四线开尔文测量用铝接I/O的Rc测试车，用于Rc数据采集。对不同PIO面积与UBM面积之比(2%~25%)下铜柱抗剪强度及破坏模式进行了分析。两种不同的再钝化材料，一种是高温固化PI(固化温度>350C)，这是铜柱凹凸的主流;另一种是低温固化刚性(高模量)PI(固化温度<300℃)，通常用于先进的晶圆厂节点进行比较。研究了小PIO尺寸对后续装配和可靠性的影响。测试车的封装尺寸为196 mm2，雏菊链模具尺寸为11 x 11 mm2。最小凹凸间距为140μm。UBM固定在35x65μm，适用于不同的PIO尺寸;10μm、10 × 20μm、20μm和15 × 25μm模拟典型凹凸设计要求。所有不同PIO尺寸的研究腿都被释放到组装中，并采用封装级热循环试验对其进行了评价。采用c型扫描声学显微镜(CSAM)、扫描电子显微镜(SEM)和每个PIO腿的截面对其装配和可靠性性能进行了研究。本研究的目的是了解小PIO尺寸对倒装封装中碰撞电气、机械和芯片封装相互作用的影响，以实现稳健的铜柱互连。
{"title":"Study of Small Polyimide Open Size in Contact Resistance and Reliability For Flip Chip Cu Pillar Package","authors":"Kuei Hsiao Kuo Frank, Shaun Xiao, Abram Hwang, Kui-Yu Chang, Jovi Chang, F. Chien","doi":"10.1109/ectc51906.2022.00272","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00272","url":null,"abstract":"In this investigation, the effects of small polyimide open (PIO) size for bump electrical, mechanical and package reliability performances are discussed. The contact resistance (Rc) between under bump metal (UBM) and Aluminum pad (Al) is assessed with varied PIO size; 10μm, 15μm, 20μm, 30μm and 35μm. The Rc test vehicle with I/O connected by Al metal for 4- wire Kelvin measurement is designed for Rc data collection. The UBM size is fixed for different PIO size, copper post shear strength and failure modes for different ratio of PIO area to UBM area (2%~25%) are also analyzed. Two different re-passivation materials, one is high temperature cured PI (curing temperature>350C) which is the mainstream for Cu pillar bump; the other is low temperature cured stiffer (high modulus) PI (curing temperature<300 C) that is typically used for advanced fab node are selected for comparison.The effects of small PIO size in subsequent assembly and reliability are also studied. The package size of test vehicle is 196 mm2 with a daisy-chain die size of 11 x 11 mm2. The minimum bump pitch is 140μm. The UBM is fixed at 35x65μm for different PIO size; 10μm, 10x20μm, 20μm and 15x25μm to simulate typical bump design request. All the study legs of different PIO size were released to assembly and had been evaluated by employing package level thermal cycling test. The assembly and reliability performance were investigated by C-mode Scanning Acoustic Microscope (CSAM), Scanning Electron Microscope (SEM) and cross-section for each PIO leg.The study of this investigation is to know the effects of small PIO size to bump electrical, mechanical and chip package interaction to achieving robust Cu pillar interconnection in flip chip package.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115644012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00136
Jacinta Aman Lim, B. Dunlap, S. Hong, H. Shin, Byung-Cheol Kim
6-sided die protection on 600mm x 600mm Fan-Out Panel Level Packaging (FOPLP) has emerged as a scale up alternative to 300mm Fan-Out Wafer Level Packaging (FOWLP). In comparison to a 300mm round panel, a 600mm x 600mm panel could fit 5 times more 200mm wafers than a 300mm round panel. The need for migrating to carrier sizes larger than 300mm for FOWLP becomes a necessity to lower down costs and handle higher volumes. Although 600mm FOPLP is in its early stages of adoption by mainstream Wafer Level Packaging (WLP), questions arise on the performance and comparison to its 300mm FOWLP counterpart.As opposed to its 300mm round panel predecessor for 6-sided die protection with mold compound, several material sets used for panel processing had to be revisited such as polymer concentration for thin film and large panel processing for metal deposition such as seed layer and redistribution layers. Affects of photolithography on large panel and subsequent downstream process such as panel backside thinning will need to be considered for overall package reliability.This paper will describe the differences and similarities between 600mm x 600mm FOPLP and 300mm round panel FOWLP utilizing a 6-sided die protection process. We will review the key metrics that affect package reliability such as Fan-Out Ratio, thin film/build up process and scaling up from 300mm round panel FOWLP to 600mm FOPLP. Finally, we will present the package reliability performance between a 300mm FOWLP versus 600mm x 600mm FOPLP.
600mm x 600mm扇出面板级封装(FOPLP)上的6面芯片保护已经成为300mm扇出晶圆级封装(FOWLP)的扩展替代方案。与300mm圆面板相比，600mm x 600mm面板可以容纳5倍于300mm圆面板的200mm晶圆。为了降低成本和处理更高的产量，FOWLP需要迁移到大于300mm的载体尺寸。虽然主流晶圆级封装(WLP)采用600mm FOPLP尚处于早期阶段，但与300mm FOPLP相比，其性能和比较方面仍存在问题。与使用模具化合物保护的300mm圆形面板相比，用于面板加工的几种材料必须重新考虑，例如用于薄膜的聚合物浓度和用于金属沉积(如种子层和再分配层)的大型面板加工。光刻对大型面板和后续下游工艺(如面板背面变薄)的影响将需要考虑整体封装可靠性。本文将描述600mm x 600mm FOPLP和300mm圆面板FOWLP之间的差异和相似之处，利用6面模具保护工艺。我们将回顾影响封装可靠性的关键指标，如扇出比、薄膜/构建工艺以及从300mm圆面板FOPLP扩展到600mm FOPLP。最后，我们将介绍300mm FOPLP与600mm × 600mm FOPLP之间的封装可靠性性能。
{"title":"Package Reliability Evaluation of 600mm FOPLP with 6-Sided Die Protection with 0.35mm Ball Pitch","authors":"Jacinta Aman Lim, B. Dunlap, S. Hong, H. Shin, Byung-Cheol Kim","doi":"10.1109/ectc51906.2022.00136","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00136","url":null,"abstract":"6-sided die protection on 600mm x 600mm Fan-Out Panel Level Packaging (FOPLP) has emerged as a scale up alternative to 300mm Fan-Out Wafer Level Packaging (FOWLP). In comparison to a 300mm round panel, a 600mm x 600mm panel could fit 5 times more 200mm wafers than a 300mm round panel. The need for migrating to carrier sizes larger than 300mm for FOWLP becomes a necessity to lower down costs and handle higher volumes. Although 600mm FOPLP is in its early stages of adoption by mainstream Wafer Level Packaging (WLP), questions arise on the performance and comparison to its 300mm FOWLP counterpart.As opposed to its 300mm round panel predecessor for 6-sided die protection with mold compound, several material sets used for panel processing had to be revisited such as polymer concentration for thin film and large panel processing for metal deposition such as seed layer and redistribution layers. Affects of photolithography on large panel and subsequent downstream process such as panel backside thinning will need to be considered for overall package reliability.This paper will describe the differences and similarities between 600mm x 600mm FOPLP and 300mm round panel FOWLP utilizing a 6-sided die protection process. We will review the key metrics that affect package reliability such as Fan-Out Ratio, thin film/build up process and scaling up from 300mm round panel FOWLP to 600mm FOPLP. Finally, we will present the package reliability performance between a 300mm FOWLP versus 600mm x 600mm FOPLP.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121356468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00035
Juno Kim, D. Min, Kangsan Lee, Mingu Lee, K. Lim, D. Rhee
A performance testing method of the Bernoulli picker which can handle an ultra-thin die without contact are formulated, and a series of experiments are conducted to evaluate and optimize the performance of the picker. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3D IC heterogeneous integration devices. To improve the quality and reliability of the devices with the hybrid bonding, it is crucial to prevent the voids and other defects in a die stacking. The Bernoulli picker that operates with the Bernoulli airflow principle is a core technology for the hybrid bonding. The competing effect of the jet force and the lifting force with respect to the die let the Bernoulli picker protect the plasma activation surface of the die due to the non-contact handling and avoid the misaligned die stacking due to the airflow driven self-alignment capability. However, as the thickness of the die becomes very thin less than 50 μm, the possibility of the die touching the surface of the Bernoulli picker increases since the warpage of the die increases due to the decrease of the die stiffness. In this paper, the authors build a method of evaluating whether the Bernoulli picker enables to handle the ultra-thin die without contact, and performs the evaluation under various process conditions to optimize the performance of the picker. To verify the performance of the Bernoulli picker, the following three items are tested: the warpage of the die, the levitation height of the die, and the restoration range of the die. The warpage and the levitation height of the die are the factors that verify the non-contact picking, and the restoration range of the die is the factor that evaluate the self-alignment capability of the die. Finally, it is confirmed that the ultra-thin die is successfully well aligned and bonded without voids using the optimized Bernoulli picker.
{"title":"A Performance Testing Method of Bernoullie Picker for Ultra-Thin Die Handling Application","authors":"Juno Kim, D. Min, Kangsan Lee, Mingu Lee, K. Lim, D. Rhee","doi":"10.1109/ectc51906.2022.00035","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00035","url":null,"abstract":"A performance testing method of the Bernoulli picker which can handle an ultra-thin die without contact are formulated, and a series of experiments are conducted to evaluate and optimize the performance of the picker. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3D IC heterogeneous integration devices. To improve the quality and reliability of the devices with the hybrid bonding, it is crucial to prevent the voids and other defects in a die stacking. The Bernoulli picker that operates with the Bernoulli airflow principle is a core technology for the hybrid bonding. The competing effect of the jet force and the lifting force with respect to the die let the Bernoulli picker protect the plasma activation surface of the die due to the non-contact handling and avoid the misaligned die stacking due to the airflow driven self-alignment capability. However, as the thickness of the die becomes very thin less than 50 μm, the possibility of the die touching the surface of the Bernoulli picker increases since the warpage of the die increases due to the decrease of the die stiffness. In this paper, the authors build a method of evaluating whether the Bernoulli picker enables to handle the ultra-thin die without contact, and performs the evaluation under various process conditions to optimize the performance of the picker. To verify the performance of the Bernoulli picker, the following three items are tested: the warpage of the die, the levitation height of the die, and the restoration range of the die. The warpage and the levitation height of the die are the factors that verify the non-contact picking, and the restoration range of the die is the factor that evaluate the self-alignment capability of the die. Finally, it is confirmed that the ultra-thin die is successfully well aligned and bonded without voids using the optimized Bernoulli picker.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121502578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00222
Klaus Ahn, Jade Park, Bruce Lee, L. Kang, Jay Kim, Kyeongrok Shin, Sung Hyuk Kim, Jea-Duck Lee, Myoung Kee Kim, Ho-Seon Lee, Byeongyong Park, Bok-Ju Park, Tong-Ook Kong
5G wireless communication, there is two frequency bands: sub-6 (3.5GHz) and mmWave (26GHz, 28GHz and 39GHz). Although sub-6 frequency is mainly used in 5G wireless communication, the demand on mmWave of consumer is growing according to increasing the amount of data. However, systems operating at mmWave frequency range have to manage with much higher signal losses then in the sub-6 frequency range. Moreover, the physical size of interconnections (chip to chip, chip to antenna) becomes comparable to the operating wavelength. Therefore, new packaging technology is required corresponding the mmWave frequency range. Antenna integrated with RF chip using FOWLP technology has been developed for mmWave 5G application. The antenna and package structure of FO-AiP have been designed and simulated to obtain optimized performance. Besides, packaging process technologies have been developed to realize the designed FO-AiP structure. The FO-AiP is fabricated with array patch antenna for target frequency of 28GHz and package technology is similar to double molded FOWLP. Instead of 2nd mold compound, transparent low Dk/ Df insulation material has been adopted. The FO-AiP has been started in RDL first FOWLP on 300mm wafer size. The simulated single-patch antenna bandwidth under S11 ⩽ -10 dB was from 26.5 to 29.5 GHz and antenna gain of 7.5 dBi in the operating band. For 2 x 2 array antenna, antenna gain increased over 10 dBi while maintaining the 3GHz antenna bandwidth. The measurement results have a good agreement with the simulation. As a result, FO-AiP should be a promising technology for 5G mmWave system application.
{"title":"Chip-last FOWLP based antenna-in-package (FO-AiP) for 5G mmWave application","authors":"Klaus Ahn, Jade Park, Bruce Lee, L. Kang, Jay Kim, Kyeongrok Shin, Sung Hyuk Kim, Jea-Duck Lee, Myoung Kee Kim, Ho-Seon Lee, Byeongyong Park, Bok-Ju Park, Tong-Ook Kong","doi":"10.1109/ectc51906.2022.00222","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00222","url":null,"abstract":"5G wireless communication, there is two frequency bands: sub-6 (3.5GHz) and mmWave (26GHz, 28GHz and 39GHz). Although sub-6 frequency is mainly used in 5G wireless communication, the demand on mmWave of consumer is growing according to increasing the amount of data. However, systems operating at mmWave frequency range have to manage with much higher signal losses then in the sub-6 frequency range. Moreover, the physical size of interconnections (chip to chip, chip to antenna) becomes comparable to the operating wavelength. Therefore, new packaging technology is required corresponding the mmWave frequency range. Antenna integrated with RF chip using FOWLP technology has been developed for mmWave 5G application. The antenna and package structure of FO-AiP have been designed and simulated to obtain optimized performance. Besides, packaging process technologies have been developed to realize the designed FO-AiP structure. The FO-AiP is fabricated with array patch antenna for target frequency of 28GHz and package technology is similar to double molded FOWLP. Instead of 2nd mold compound, transparent low Dk/ Df insulation material has been adopted. The FO-AiP has been started in RDL first FOWLP on 300mm wafer size. The simulated single-patch antenna bandwidth under S11 ⩽ -10 dB was from 26.5 to 29.5 GHz and antenna gain of 7.5 dBi in the operating band. For 2 x 2 array antenna, antenna gain increased over 10 dBi while maintaining the 3GHz antenna bandwidth. The measurement results have a good agreement with the simulation. As a result, FO-AiP should be a promising technology for 5G mmWave system application.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00342
C.H. Huang, P. S. Shih, J.H. Huang, S. J. Gräfner, Y.A. Chen, C. Kao
Direct Cu-Cu bonding is successfully bonded at 250 °C, 5MPa under 10−2 torr for 15min with the use of electroless fabricated Cu. Several effected factors on bonding interface including temperature, pressure, surface roughness, and time are studied.Direct Cu-Cu bonding in Cu pillar bump is currently used to replace traditional solder bump due to the capability of scaling down pitch, better electrical and mechanical properties. Among all methods to fabricate Cu, electroless plating possesses the advantages of simple fabrication process, high uniformity and low cost. Moreover, the autocatalytic behavior of electroless deposition shows a high level of competence on massive production of uniform Cu layer without the use of external electrical energy under atmospheric environment, which is beneficial to the industries. Therefore, it is worthy of developing Cu-Cu bonding process using electroless fabricated Cu for future three-dimensional (3D) integration applications.In this study, Cu films are first deposited on silicon substrates. Chemical Mechanical Polishing (CMP) process is used to reduce the surface roughness of electroless Cu for comparing the bonding interface of different roughness. The effects of temperature, external pressure, surface roughness, and bonding time are studied to optimize the bonding parameters. Through prolonged annealing under 10−2 torr, the void ratio of the bonded joints can be further reduced. Several factors which contribute to the reduction of interfacial voids are studied and their mechanisms are delivered. To sum, a newly Cu- Cu bonding using electroless fabricated Cu is developed and optimized.
{"title":"Thermal Compression Cu-Cu bonding using electroless Cu and the evolution of voids within bonding interface","authors":"C.H. Huang, P. S. Shih, J.H. Huang, S. J. Gräfner, Y.A. Chen, C. Kao","doi":"10.1109/ectc51906.2022.00342","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00342","url":null,"abstract":"Direct Cu-Cu bonding is successfully bonded at 250 °C, 5MPa under 10−2 torr for 15min with the use of electroless fabricated Cu. Several effected factors on bonding interface including temperature, pressure, surface roughness, and time are studied.Direct Cu-Cu bonding in Cu pillar bump is currently used to replace traditional solder bump due to the capability of scaling down pitch, better electrical and mechanical properties. Among all methods to fabricate Cu, electroless plating possesses the advantages of simple fabrication process, high uniformity and low cost. Moreover, the autocatalytic behavior of electroless deposition shows a high level of competence on massive production of uniform Cu layer without the use of external electrical energy under atmospheric environment, which is beneficial to the industries. Therefore, it is worthy of developing Cu-Cu bonding process using electroless fabricated Cu for future three-dimensional (3D) integration applications.In this study, Cu films are first deposited on silicon substrates. Chemical Mechanical Polishing (CMP) process is used to reduce the surface roughness of electroless Cu for comparing the bonding interface of different roughness. The effects of temperature, external pressure, surface roughness, and bonding time are studied to optimize the bonding parameters. Through prolonged annealing under 10−2 torr, the void ratio of the bonded joints can be further reduced. Several factors which contribute to the reduction of interfacial voids are studied and their mechanisms are delivered. To sum, a newly Cu- Cu bonding using electroless fabricated Cu is developed and optimized.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122788283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00061
Shan-Bo Wang, An-Hsuan Hsu, C. Kao, D. Tarng, Chien-Lung Liang, Kwang-Lung Lin
Thermal compression bonding (TCB) of Cu pillars at high temperature often induces undesirable warpage occurrence due to the mismatch in coefficient of thermal expansion (CTE) among heterogeneous components. Reducing the bonding temperature to avoid warpage is desirable for the development of Cu-to-Cu bonding in three-dimensional integrated circuit (3D IC) packaging.One of the approaches for lowering bonding temperature is to implement low melting temperature materials between Cu pillars. We presented in this article a novel low-temperature bonding technology for fine-pitch, less than 20 μm, Cu-to-Cu interconnects with Cu substrates. The TCB was conducted at 150°C. The low-temperature bonding was assisted by an electroplated intermediate Ga/X-alloy bilayer. The surface of the Ga layer was pre-treated with dilute sulfuric acid for better wetting behavior. The intermediate Ga layer melted and gave rise to liquid/solid interdiffusion with the X-alloy layer during the bonding according to the binary Ga-X-alloy phase diagram. The Ga component further diffused through the X-alloy layer and preferentially reacted with the Cu substrate to form thermodynamically stable CuGa2 intermetallic compound (IMC) at the Cu/X-alloy interface. The crosssectional scanning electron microscope (SEM) and focus ion beam (FIB) analyses indicated that the uniform IMC layer has around 2 μm in thickness. The energy dispersive X-ray spectroscopy (EDS) analysis showed that the electroplated Ga layer was completed consumed and mostly converted to interfacial IMC and partially dissolved in the X-alloy layer after the bonding. The microstructure characterization of the joint revealed an indistinct bonding interface with few impurities or defects, showing pronounced effect of interdiffusion during the bonding. The produced joint structure exhibited a bonding strength greater than 5 MPa as measured by a chip-scale universal testing machine. The low-temperature liquid/solid interdiffusion bonding process could be operated without the need of chemical mechanical polish (CMP). It is believed, basing on the bonding performance, that the Ga assisted low-temperature Cu-to-Cu bonding approach could be more feasible for new applications in fine-pitch 3D IC packaging.
{"title":"Novel Ga Assisted Low-temperature Bonding Technology for Fine-pitch Interconnects","authors":"Shan-Bo Wang, An-Hsuan Hsu, C. Kao, D. Tarng, Chien-Lung Liang, Kwang-Lung Lin","doi":"10.1109/ectc51906.2022.00061","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00061","url":null,"abstract":"Thermal compression bonding (TCB) of Cu pillars at high temperature often induces undesirable warpage occurrence due to the mismatch in coefficient of thermal expansion (CTE) among heterogeneous components. Reducing the bonding temperature to avoid warpage is desirable for the development of Cu-to-Cu bonding in three-dimensional integrated circuit (3D IC) packaging.One of the approaches for lowering bonding temperature is to implement low melting temperature materials between Cu pillars. We presented in this article a novel low-temperature bonding technology for fine-pitch, less than 20 μm, Cu-to-Cu interconnects with Cu substrates. The TCB was conducted at 150°C. The low-temperature bonding was assisted by an electroplated intermediate Ga/X-alloy bilayer. The surface of the Ga layer was pre-treated with dilute sulfuric acid for better wetting behavior. The intermediate Ga layer melted and gave rise to liquid/solid interdiffusion with the X-alloy layer during the bonding according to the binary Ga-X-alloy phase diagram. The Ga component further diffused through the X-alloy layer and preferentially reacted with the Cu substrate to form thermodynamically stable CuGa2 intermetallic compound (IMC) at the Cu/X-alloy interface. The crosssectional scanning electron microscope (SEM) and focus ion beam (FIB) analyses indicated that the uniform IMC layer has around 2 μm in thickness. The energy dispersive X-ray spectroscopy (EDS) analysis showed that the electroplated Ga layer was completed consumed and mostly converted to interfacial IMC and partially dissolved in the X-alloy layer after the bonding. The microstructure characterization of the joint revealed an indistinct bonding interface with few impurities or defects, showing pronounced effect of interdiffusion during the bonding. The produced joint structure exhibited a bonding strength greater than 5 MPa as measured by a chip-scale universal testing machine. The low-temperature liquid/solid interdiffusion bonding process could be operated without the need of chemical mechanical polish (CMP). It is believed, basing on the bonding performance, that the Ga assisted low-temperature Cu-to-Cu bonding approach could be more feasible for new applications in fine-pitch 3D IC packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131496984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00107
S. Lim, S. Chong, D. Wee, T. Chai
Antenna-in-package (AiP) technology is a packaging solution where antennas are incorporated into an integrated circuit (IC) package with a RF chip [1], [2]. One of the promising technology is the Fan-out wafer level technology especially for its excellent RF performance in mobile and automotive applications [3], [4].This paper demonstrates a double FOWLP based AiP package for 77 GHz automotive radar applications with package attachment to PCB board. The ultra large package size is 32 x 16 mm2 with 0.6mm mold thickness after singulation. The lower mold layer consists of a Monolithic microwave integrated circuit (MMIC) chip and lithography process is done to reroute chip I/O pads to the mold compound top layer. The through mold vias (TMV) are interconnect vias formed through the mold compound to connect to the M3 RDL layer. The antenna excitation elements are then fabricated onto the surface of the 2nd mold EMC 2. The package is then attached to an interposer PCB and functional application board with double-side surface mount components for electrical testing and characterization. Detailed assembly process parameters on wafer reconfiguration, die placement shift compensation, compression wafer molding and debonding process to establish die placement accuracy and die protrusion of ±10um will be discussed in this work. Details of the thermocompression bonding process (TCB) for the package attachment to the PCB will also be summarized in this paper.
{"title":"Assembly challenges and demonstrations of ultra-large Antenna in Package for Automotive Radar applications","authors":"S. Lim, S. Chong, D. Wee, T. Chai","doi":"10.1109/ectc51906.2022.00107","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00107","url":null,"abstract":"Antenna-in-package (AiP) technology is a packaging solution where antennas are incorporated into an integrated circuit (IC) package with a RF chip [1], [2]. One of the promising technology is the Fan-out wafer level technology especially for its excellent RF performance in mobile and automotive applications [3], [4].This paper demonstrates a double FOWLP based AiP package for 77 GHz automotive radar applications with package attachment to PCB board. The ultra large package size is 32 x 16 mm2 with 0.6mm mold thickness after singulation. The lower mold layer consists of a Monolithic microwave integrated circuit (MMIC) chip and lithography process is done to reroute chip I/O pads to the mold compound top layer. The through mold vias (TMV) are interconnect vias formed through the mold compound to connect to the M3 RDL layer. The antenna excitation elements are then fabricated onto the surface of the 2nd mold EMC 2. The package is then attached to an interposer PCB and functional application board with double-side surface mount components for electrical testing and characterization. Detailed assembly process parameters on wafer reconfiguration, die placement shift compensation, compression wafer molding and debonding process to establish die placement accuracy and die protrusion of ±10um will be discussed in this work. Details of the thermocompression bonding process (TCB) for the package attachment to the PCB will also be summarized in this paper.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128009860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：