Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00325
B. Hou, Hai-Jun Huang, Chunling Wang, Min-bo Zhou, Xin-Ping Zhang
Pressureless low temperature Cu–Cu bonding by sintering Cu nanoparticle (NP) paste is a promising method to realize die attachment in power electronics and third-generation semiconductor devices. However, the low reliability of sintered Cu paste joints due to poor sintering microstructure and processing defects is a challenging and urgent issue to be solved. The present work develops a novel Cu paste consisting of bimodal-size Cu NPs with special wrapping structure by means of a one-step method and use of reducing hybrid solvents. The sintered Cu paste matrix shows relatively dense sintered microstructure, despite using mild process condition of pressureless low temperature sintering, and sintered Cu– Cu joints in large-area dummy die attachment exhibit high shear strength up to 29.5 MPa after pressureless sintering at 280 °C for 10 min in N2 atmosphere. High strength of joints is ascribed to the strengthening effect of bulky Cu phase formed in sintered microstructures. After thermal aging tests, the strength of joints is increased to over 40 MPa, indicating exceptional long-term reliability. The bimodal size Cu NP paste is capable of sintering by adopting relatively mild process yet endows sintered Cu–Cu joints with robust reliability, thus exhibits a broad application prospect in the packaging field of high power electronics.
{"title":"Superb sinterability of the Cu paste consisting of bimodal size distribution Cu nanoparticles for low-temperature and pressureless sintering of large-area die attachment and the sintering mechanism","authors":"B. Hou, Hai-Jun Huang, Chunling Wang, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ectc51906.2022.00325","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00325","url":null,"abstract":"Pressureless low temperature Cu–Cu bonding by sintering Cu nanoparticle (NP) paste is a promising method to realize die attachment in power electronics and third-generation semiconductor devices. However, the low reliability of sintered Cu paste joints due to poor sintering microstructure and processing defects is a challenging and urgent issue to be solved. The present work develops a novel Cu paste consisting of bimodal-size Cu NPs with special wrapping structure by means of a one-step method and use of reducing hybrid solvents. The sintered Cu paste matrix shows relatively dense sintered microstructure, despite using mild process condition of pressureless low temperature sintering, and sintered Cu– Cu joints in large-area dummy die attachment exhibit high shear strength up to 29.5 MPa after pressureless sintering at 280 °C for 10 min in N2 atmosphere. High strength of joints is ascribed to the strengthening effect of bulky Cu phase formed in sintered microstructures. After thermal aging tests, the strength of joints is increased to over 40 MPa, indicating exceptional long-term reliability. The bimodal size Cu NP paste is capable of sintering by adopting relatively mild process yet endows sintered Cu–Cu joints with robust reliability, thus exhibits a broad application prospect in the packaging field of high power electronics.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00288
R. Imani, Shailesh Chouhan, J. Delsing, Sarthak Acharya
Metasurfaces, as a two-dimensional (2D) form of metamaterial, offer the possibility of designing miniaturized antennas for radio frequency (RF) energy harvesting systems with high efficiency, but fabrication of these antennas is still a major challenge. Printed circuit board (PCB) lithography, utilizing subtractive etch-and-print techniques to create metal interconnects on PCBs, was the first technique used to create metasurfaces antennas and remains the dominant technique to this day. The development of large-area fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation metasurfaces antenna. The present study reports a new fully additive manufacturing method for the fabrication of copper split-ring resonator (SRR) arrays on a PCB as a planar compact metasurfaces antenna. This new method was developed by combining sequential build up (SBU), laser direct writing (LDW), and covalent bonded metallization (CBM) methods and called (SBU-CBM). In this method, standard FR-4 covered with a layer of polyurethane was used as a basic PCB. The polymer surface was coated with a grafting molecule, followed by LDW to pattern the SRR array on the PCB. Finally, in electroless plating, only the laser-scanned area was selectively plated, and copper covalent bond metallization was selectively plated on the SRR pattern. Copper SRR arrays with different sizes were successfully fabricated on PCB using the SBU-CBM method. Copper strip lines within the SRR repeating building block were miniaturized up to 5 μm. To the best of our knowledge, this is the smallest size of a PCB antenna that has been reported to date.
{"title":"A Fully Additive Approach for the Fabrication of Split-Ring Resonator Metasurfaces","authors":"R. Imani, Shailesh Chouhan, J. Delsing, Sarthak Acharya","doi":"10.1109/ectc51906.2022.00288","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00288","url":null,"abstract":"Metasurfaces, as a two-dimensional (2D) form of metamaterial, offer the possibility of designing miniaturized antennas for radio frequency (RF) energy harvesting systems with high efficiency, but fabrication of these antennas is still a major challenge. Printed circuit board (PCB) lithography, utilizing subtractive etch-and-print techniques to create metal interconnects on PCBs, was the first technique used to create metasurfaces antennas and remains the dominant technique to this day. The development of large-area fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation metasurfaces antenna. The present study reports a new fully additive manufacturing method for the fabrication of copper split-ring resonator (SRR) arrays on a PCB as a planar compact metasurfaces antenna. This new method was developed by combining sequential build up (SBU), laser direct writing (LDW), and covalent bonded metallization (CBM) methods and called (SBU-CBM). In this method, standard FR-4 covered with a layer of polyurethane was used as a basic PCB. The polymer surface was coated with a grafting molecule, followed by LDW to pattern the SRR array on the PCB. Finally, in electroless plating, only the laser-scanned area was selectively plated, and copper covalent bond metallization was selectively plated on the SRR pattern. Copper SRR arrays with different sizes were successfully fabricated on PCB using the SBU-CBM method. Copper strip lines within the SRR repeating building block were miniaturized up to 5 μm. To the best of our knowledge, this is the smallest size of a PCB antenna that has been reported to date.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128524846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00192
Kendra Young, R. Aspandiar, Nilesh Badwe, S. Walwadkar, Young-woo Lee, Tae-Kyu Lee
With the increase of interest in low melting temperature solder alloys, in recent studies on Sn-Bi based system solder show relatively good thermal cycling performances comparable to conventional Sn-Ag-Cu based solder interconnects at a given thermal cycling profile. Sn-Bi eutectic system microstructures are similar to Sn-Pb eutectic microstructure but have different damage accumulation mechanism due to Bi crystal lattice with Rhombohedral A7 unit cell structure, which is less ductile compared to Sn-Pb, where Pb has face centered cubic crystal lattice. The nature of less ductility in Sn-Bi alloy system reveals a different damage accumulation process during thermal cycling compared to Sn-Ag-Cu solder material, although the thermal cycling performance is comparable with micro-elementalloying. To identify the degradation mechanism in Sn-Bi solder interconnects, the study presented here is a series of microstructure analysis on segmented thermal cycling completed components, which reveal gradual and localized microstructure evolution. 12x12 mm2 chip array BGA (CABGA) components were thermal cycled with a -40 to 100°C cycle profile and a 10min dwell time. The microstructure developments per component were analyzed with 200-250 cycles interval cross-sections until both Sn- Ag-Cu and Sn-Bi solder joints reached to full failure. The correlation between crack initiation, crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron- backscattered diffraction (EBSD) based strain and residual stress analysis. The analysis revealed the potential damage accumulation process in Sn-Bi solder joint under thermal cycling, which is discussed in this paper.
{"title":"Thermal cycling induced interconnect stability degradation mechanism in low melting temperature solder joints","authors":"Kendra Young, R. Aspandiar, Nilesh Badwe, S. Walwadkar, Young-woo Lee, Tae-Kyu Lee","doi":"10.1109/ectc51906.2022.00192","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00192","url":null,"abstract":"With the increase of interest in low melting temperature solder alloys, in recent studies on Sn-Bi based system solder show relatively good thermal cycling performances comparable to conventional Sn-Ag-Cu based solder interconnects at a given thermal cycling profile. Sn-Bi eutectic system microstructures are similar to Sn-Pb eutectic microstructure but have different damage accumulation mechanism due to Bi crystal lattice with Rhombohedral A7 unit cell structure, which is less ductile compared to Sn-Pb, where Pb has face centered cubic crystal lattice. The nature of less ductility in Sn-Bi alloy system reveals a different damage accumulation process during thermal cycling compared to Sn-Ag-Cu solder material, although the thermal cycling performance is comparable with micro-elementalloying. To identify the degradation mechanism in Sn-Bi solder interconnects, the study presented here is a series of microstructure analysis on segmented thermal cycling completed components, which reveal gradual and localized microstructure evolution. 12x12 mm2 chip array BGA (CABGA) components were thermal cycled with a -40 to 100°C cycle profile and a 10min dwell time. The microstructure developments per component were analyzed with 200-250 cycles interval cross-sections until both Sn- Ag-Cu and Sn-Bi solder joints reached to full failure. The correlation between crack initiation, crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron- backscattered diffraction (EBSD) based strain and residual stress analysis. The analysis revealed the potential damage accumulation process in Sn-Bi solder joint under thermal cycling, which is discussed in this paper.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128583415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00127
Hojoong Kim, Hyojung J. Choo, W. Yeo
Volumetric muscle loss (VML) indicates the traumatic or surgical loss of skeletal muscle tissues, which leads to chronic muscle weakness and impaired muscle function. VML is a demanding issue since it requires surgical autologous muscle transplantation, which causes substantial morbidity to the donor site. Several researchers have studied VML on craniofacial muscles of large animals, such as zygomaticus muscles of sheep, emphasizing the pathophysiological differences between limb and craniofacial VML. However, a craniofacial VML mouse model using actual craniofacial muscles has not been reported due to the small size of the craniofacial muscle of a mouse. Another difficulty in developing the craniofacial VML mouse model is the lack of functional assay tools that can monitor the regeneration or recovery of injured muscles in the active mouse in a non-invasive manner. Current electromyogram (EMG) systems have limitations due to the form factor, rigidity, and bulky platforms, which require invasive needle-type sensors, wires, and multiple electronic modules. Here, we introduce thin-film, wireless nanomembrane electronics to measure noninvasive, real-time muscle EMG on the skin of mouse masseter muscles with or without biopsy punch-induced VML. The integration of soft materials, flexible structures, membrane electronics, and soft packaging technologies develop the all-in-one wearable sensor system that can be mounted on the skin. To measure the function of VML-injured masseter muscles of active mice, we use a soft, wireless, and wearable electronic system to provide real-time EMG monitoring. Overall, the presented study, integrating sensors, electronics, and packaging technologies, shows a wearable assay tool for the mechanism study and the therapeutic development of craniofacial VML.
{"title":"Wireless Nanomembrane Electronics and Soft Packaging Technologies for Noninvasive, Real-time Monitoring of Muscle Activities","authors":"Hojoong Kim, Hyojung J. Choo, W. Yeo","doi":"10.1109/ectc51906.2022.00127","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00127","url":null,"abstract":"Volumetric muscle loss (VML) indicates the traumatic or surgical loss of skeletal muscle tissues, which leads to chronic muscle weakness and impaired muscle function. VML is a demanding issue since it requires surgical autologous muscle transplantation, which causes substantial morbidity to the donor site. Several researchers have studied VML on craniofacial muscles of large animals, such as zygomaticus muscles of sheep, emphasizing the pathophysiological differences between limb and craniofacial VML. However, a craniofacial VML mouse model using actual craniofacial muscles has not been reported due to the small size of the craniofacial muscle of a mouse. Another difficulty in developing the craniofacial VML mouse model is the lack of functional assay tools that can monitor the regeneration or recovery of injured muscles in the active mouse in a non-invasive manner. Current electromyogram (EMG) systems have limitations due to the form factor, rigidity, and bulky platforms, which require invasive needle-type sensors, wires, and multiple electronic modules. Here, we introduce thin-film, wireless nanomembrane electronics to measure noninvasive, real-time muscle EMG on the skin of mouse masseter muscles with or without biopsy punch-induced VML. The integration of soft materials, flexible structures, membrane electronics, and soft packaging technologies develop the all-in-one wearable sensor system that can be mounted on the skin. To measure the function of VML-injured masseter muscles of active mice, we use a soft, wireless, and wearable electronic system to provide real-time EMG monitoring. Overall, the presented study, integrating sensors, electronics, and packaging technologies, shows a wearable assay tool for the mechanism study and the therapeutic development of craniofacial VML.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128623152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00134
Da-Hee Kim, Jae-Ean Lee, Gyujin Choi, Sunguk Lee, Giho Jeong, Hongwon Kim, S. Lee, Dong Wook Kim
The fan out technology has been recently introduced as an effective method to reduce a packaging cost and to minimize a package size by using a redistribution layer(RDL). Moreover, as the number of high-capacity ultra-small devices increases, transition to fan-out package technology (FOPKG) is an important for realizing fast signal speed and high capacity. To this end, one of the key parameters for FOPKG’s interconnection density and fine pitch is adopting the stacked fine via technology.In this paper, we propose the physical crack mode of the stacked via in the fan-out panel level package(FOPLP), and try to optimize structural integrity based on the crack generation mechanism. Physical crack in stacked vias occurs in two different modes: via-via interface crack, via-dielectric point crack. To investigate via-via interface crack, various via shapes were tested. As a result, vias with lower dimple showed better structural stability under temperature changing condition. For via-dielectric point crack, structural DOE for tapered via angle was performed, and an optimal angle with released stress between cu and dielectric could be found. Furthermore, it was found that physical crack occurs depending on via size. Thus, in order to secure reliability margin, a study was conducted to change in shape and reinforce the weak point.In summary, as a result of the above study, it could be possible to optimize the via structure. The package reliability tests (Pre-condition + TC / u-HAST, HTS) were successfully evaluated with a vehicle that is adopted by optimal triple stacked via structure. By using the stacked via optimized through this study, the characteristics of FOPKG can be further improved by high electrical performance and the reduction of package size.
{"title":"Study of reliable via structure for Fan Out Panel Level Package (FoPLP)","authors":"Da-Hee Kim, Jae-Ean Lee, Gyujin Choi, Sunguk Lee, Giho Jeong, Hongwon Kim, S. Lee, Dong Wook Kim","doi":"10.1109/ectc51906.2022.00134","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00134","url":null,"abstract":"The fan out technology has been recently introduced as an effective method to reduce a packaging cost and to minimize a package size by using a redistribution layer(RDL). Moreover, as the number of high-capacity ultra-small devices increases, transition to fan-out package technology (FOPKG) is an important for realizing fast signal speed and high capacity. To this end, one of the key parameters for FOPKG’s interconnection density and fine pitch is adopting the stacked fine via technology.In this paper, we propose the physical crack mode of the stacked via in the fan-out panel level package(FOPLP), and try to optimize structural integrity based on the crack generation mechanism. Physical crack in stacked vias occurs in two different modes: via-via interface crack, via-dielectric point crack. To investigate via-via interface crack, various via shapes were tested. As a result, vias with lower dimple showed better structural stability under temperature changing condition. For via-dielectric point crack, structural DOE for tapered via angle was performed, and an optimal angle with released stress between cu and dielectric could be found. Furthermore, it was found that physical crack occurs depending on via size. Thus, in order to secure reliability margin, a study was conducted to change in shape and reinforce the weak point.In summary, as a result of the above study, it could be possible to optimize the via structure. The package reliability tests (Pre-condition + TC / u-HAST, HTS) were successfully evaluated with a vehicle that is adopted by optimal triple stacked via structure. By using the stacked via optimized through this study, the characteristics of FOPKG can be further improved by high electrical performance and the reduction of package size.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00164
Se-Chul Park, Jong-ho Park, S. Bae, Junyoung Park, Tae-Jin Jung, H. Yun, Kwangok Jeong, Seok-Bong Park, Ju-il Choi, U. Kang, D. Kang
Fan-out wafer level packaging (FOWLP) enables high density heterogeneous integration of distinguished functions into single chip by 3D stacking logic and memory chips. High density 3D FOWLP requires Cu pillars to deliver power and signal between stacked chips. However, realization of reliable Cu pillars is a challenge due to its distinguished features including extreme height with high aspect ratio (A/R) and its exceptionally long process time for electroplating. Herein, this study reports realization of high A/R and fine pitch Cu pillars incorporating high speed electroplating with novel strip process. Process conditions including electroplating current, ion concentration, process temperature, and mechanical agitation were studied and experimentally evaluated to accelerate electroplating rate. Gradual modulation of applied current in electroplating process helps to resolve non-uniform ion distribution. Elevation of process temperature enhances diffusion and flow of Cu ions. Surface modification for photoresist leads the superior tolerance in high temperature electroplating bath through preventing leaching and deformation of the photoresist. High A/R structure of Cu pillar requires novel strip process, and identification and modeling of the process relating nozzle and spray position leads drastic improvement of its performance than conventional process. The derived knobs demonstrates mass-productive and reliable Cu pillar for 3D heterogeneous packaging.
{"title":"Realization of high A/R and fine pitch Cu pillars incorporating high speed electroplating with novel strip process","authors":"Se-Chul Park, Jong-ho Park, S. Bae, Junyoung Park, Tae-Jin Jung, H. Yun, Kwangok Jeong, Seok-Bong Park, Ju-il Choi, U. Kang, D. Kang","doi":"10.1109/ectc51906.2022.00164","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00164","url":null,"abstract":"Fan-out wafer level packaging (FOWLP) enables high density heterogeneous integration of distinguished functions into single chip by 3D stacking logic and memory chips. High density 3D FOWLP requires Cu pillars to deliver power and signal between stacked chips. However, realization of reliable Cu pillars is a challenge due to its distinguished features including extreme height with high aspect ratio (A/R) and its exceptionally long process time for electroplating. Herein, this study reports realization of high A/R and fine pitch Cu pillars incorporating high speed electroplating with novel strip process. Process conditions including electroplating current, ion concentration, process temperature, and mechanical agitation were studied and experimentally evaluated to accelerate electroplating rate. Gradual modulation of applied current in electroplating process helps to resolve non-uniform ion distribution. Elevation of process temperature enhances diffusion and flow of Cu ions. Surface modification for photoresist leads the superior tolerance in high temperature electroplating bath through preventing leaching and deformation of the photoresist. High A/R structure of Cu pillar requires novel strip process, and identification and modeling of the process relating nozzle and spray position leads drastic improvement of its performance than conventional process. The derived knobs demonstrates mass-productive and reliable Cu pillar for 3D heterogeneous packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129132896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00271
Tao Peng, Xiaohui Peng, Wenjie Wu, L. Peng, Gang Li, Jinbao Yang, Yuanyuan Yang, Jing Chen, Caiping Zhu, Pengli Zhu, Rong Sun
To improve the reliability of microelectronic packages, underfills are widely used in flip-chip packages to protect solder bumps from hazard environment. Nevertheless, the residual stress caused by the curing shrinkage of underfill has always an important issue for the reliability. Currently, there is a lack of comprehensive understanding of the curing residual stress in the constrained state of packaging structure. In this work, a novel in-situ characterization was conducted on the flip-chip test vehicle (FCTV) to analyze the curing behavior of underfill in the 3-dimensionally constrained state. Interestingly, the curing shrinkage exhibited anisotropy under 3-dimensionally constrained state, and the actual shrinkage in Z-axis direction was much larger than that in X/Y-axis direction. The shrinkage in Z-axis direction can produce residual compressive stress (or prestress) in the solder bumps, while the shrinkage in X/Y-axis direction was mainly residual shrinkage, which contributed obviously to warpage. Therefore, except for CTE mismatch, curing residual stress also played an important role in the package warpage and deformation during thermal processes. In addition, an abnormal negative expansion behavior (NEB) in the laminar underfill after release from the constrained state also seemed to be related to the curing residual stress and needs to be further studied. This work provided a new perspective on the influence of underfill curing residual stress on the reliability of packaging structures.
{"title":"Anisotropy of curing residual stress of underfill in the encapsulation under three-dimensionally constrained condition based on in-situ characterization","authors":"Tao Peng, Xiaohui Peng, Wenjie Wu, L. Peng, Gang Li, Jinbao Yang, Yuanyuan Yang, Jing Chen, Caiping Zhu, Pengli Zhu, Rong Sun","doi":"10.1109/ectc51906.2022.00271","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00271","url":null,"abstract":"To improve the reliability of microelectronic packages, underfills are widely used in flip-chip packages to protect solder bumps from hazard environment. Nevertheless, the residual stress caused by the curing shrinkage of underfill has always an important issue for the reliability. Currently, there is a lack of comprehensive understanding of the curing residual stress in the constrained state of packaging structure. In this work, a novel in-situ characterization was conducted on the flip-chip test vehicle (FCTV) to analyze the curing behavior of underfill in the 3-dimensionally constrained state. Interestingly, the curing shrinkage exhibited anisotropy under 3-dimensionally constrained state, and the actual shrinkage in Z-axis direction was much larger than that in X/Y-axis direction. The shrinkage in Z-axis direction can produce residual compressive stress (or prestress) in the solder bumps, while the shrinkage in X/Y-axis direction was mainly residual shrinkage, which contributed obviously to warpage. Therefore, except for CTE mismatch, curing residual stress also played an important role in the package warpage and deformation during thermal processes. In addition, an abnormal negative expansion behavior (NEB) in the laminar underfill after release from the constrained state also seemed to be related to the curing residual stress and needs to be further studied. This work provided a new perspective on the influence of underfill curing residual stress on the reliability of packaging structures.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116332245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00052
Archit Shah, Sherman E. Peek, Bhargav Yelamanchili, Vaibhav Gupta, D. Tuckerman, C. Cantaloube, John A. Sellers, M. Hamilton
We describe a superconducting multi-chip module (S-MCM) technology using Mo as a robust substrate on which to construct multi-layer superconducting redistribution layers for chip-to-chip signal transmission for densely-integrated cryogenic and quantum electronics. The mechanical robustness and ductile nature of Mo can allow for the integration of chips on a larger scale S-MCM substrate compared to currently available technologies. We demonstrate this integration technology by flip-chip bonding Si chips to Mo substrates using In bumps and epoxy underfill. Superconducting daisy-chain test structures were formed by Mo substrates with polyimide dielectric and superconducting Nb traces connected to Si chips with varying numbers of transitions and bump array densities. Resistance and superconducting transition temperatures of the various daisy-chain configurations were measured from room temperature to 4.2 K. To explore CTE-related challenges, assemblies using Si chips with dimensions up to 27 mm x 22 mm (In bump array size of 20 mm x 20 mm) were found to survive the multiple thermal cycles from room temperature to cryogenic temperatures.
我们描述了一种超导多芯片模块(S-MCM)技术，使用Mo作为坚固的衬底，在其上构建多层超导重分布层，用于芯片间信号传输，用于密集集成的低温和量子电子学。与目前可用的技术相比，Mo的机械坚固性和延展性可以允许在更大规模的S-MCM基板上集成芯片。我们通过使用In凸起和环氧底料将Si芯片倒装到Mo衬底来演示这种集成技术。超导菊链测试结构由Mo衬底与聚酰亚胺介质和超导Nb走线连接到具有不同跃迁数量和碰撞阵列密度的Si芯片形成。在室温至4.2 K范围内测量了不同雏菊链构型的电阻和超导转变温度。为了探索与cte相关的挑战，使用尺寸高达27 mm x 22 mm(凹凸阵列尺寸为20 mm x 20 mm)的Si芯片的组件被发现可以在从室温到低温的多个热循环中存活下来。
{"title":"Superconducting Molybdenum Multi-Chip Module Approach for Cryogenic and Quantum Applications","authors":"Archit Shah, Sherman E. Peek, Bhargav Yelamanchili, Vaibhav Gupta, D. Tuckerman, C. Cantaloube, John A. Sellers, M. Hamilton","doi":"10.1109/ectc51906.2022.00052","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00052","url":null,"abstract":"We describe a superconducting multi-chip module (S-MCM) technology using Mo as a robust substrate on which to construct multi-layer superconducting redistribution layers for chip-to-chip signal transmission for densely-integrated cryogenic and quantum electronics. The mechanical robustness and ductile nature of Mo can allow for the integration of chips on a larger scale S-MCM substrate compared to currently available technologies. We demonstrate this integration technology by flip-chip bonding Si chips to Mo substrates using In bumps and epoxy underfill. Superconducting daisy-chain test structures were formed by Mo substrates with polyimide dielectric and superconducting Nb traces connected to Si chips with varying numbers of transitions and bump array densities. Resistance and superconducting transition temperatures of the various daisy-chain configurations were measured from room temperature to 4.2 K. To explore CTE-related challenges, assemblies using Si chips with dimensions up to 27 mm x 22 mm (In bump array size of 20 mm x 20 mm) were found to survive the multiple thermal cycles from room temperature to cryogenic temperatures.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127878022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00315
Eun-Sung Ha, Haksan Jeong, Kyung Deuk Min, Kyung-Yeol Kim, Seung-Boo Jung
In recent years’ fan-out package is playing a most important role in heterogeneous integrated system in package (SiP) technology because of improved degree of freedom of design by using fan-out area of package. The fan-out package is now used as central processing unit (CPU), graphics processing unit (GPU), high bandwidth memory (HBM), mobile application processor (AP), audio codec, antenna in package (AiP) and so on. We fabricated the EMC with Electromagnetic interference (EMI) shielding properties using EMI shielding filler to fabricate the antenna directly on the surface of EMC to reduce the thickness and interconnection of AiP. AlN and carbonyl-Fe was applied to ceramic filler and EMI shielding filler of granular-type EMC, respectively. With increasing contents of carbonyl-Fe, the coefficient of thermal expansion (CTE) of EMC increased and modulus of EMC decreased. Relative permittivity of EMC increased with increasing contents of carbonyl-Fe following the percolation theory. The near-field shielding effectiveness of EMC consisted of 25% carbonyl-Fe was more than 10dB at the frequency range of 0.8 kHz to 18 GHz. The shielding effectiveness of EMC with Fe was mainly contributed by shielding by absorption. The dielectric loss of transmission that evaluated using CPW increased with increasing Fe contents of EMC because of relative permittivity.
{"title":"RF Characterization in Range of 18GHz in Fan-out Package Structure Molded by Epoxy Molding Compound with EMI Shielding Property","authors":"Eun-Sung Ha, Haksan Jeong, Kyung Deuk Min, Kyung-Yeol Kim, Seung-Boo Jung","doi":"10.1109/ectc51906.2022.00315","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00315","url":null,"abstract":"In recent years’ fan-out package is playing a most important role in heterogeneous integrated system in package (SiP) technology because of improved degree of freedom of design by using fan-out area of package. The fan-out package is now used as central processing unit (CPU), graphics processing unit (GPU), high bandwidth memory (HBM), mobile application processor (AP), audio codec, antenna in package (AiP) and so on. We fabricated the EMC with Electromagnetic interference (EMI) shielding properties using EMI shielding filler to fabricate the antenna directly on the surface of EMC to reduce the thickness and interconnection of AiP. AlN and carbonyl-Fe was applied to ceramic filler and EMI shielding filler of granular-type EMC, respectively. With increasing contents of carbonyl-Fe, the coefficient of thermal expansion (CTE) of EMC increased and modulus of EMC decreased. Relative permittivity of EMC increased with increasing contents of carbonyl-Fe following the percolation theory. The near-field shielding effectiveness of EMC consisted of 25% carbonyl-Fe was more than 10dB at the frequency range of 0.8 kHz to 18 GHz. The shielding effectiveness of EMC with Fe was mainly contributed by shielding by absorption. The dielectric loss of transmission that evaluated using CPW increased with increasing Fe contents of EMC because of relative permittivity.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00205
Chunlin He, Ruud DeWit, Jay Chao, Tim Champagne, R. Guino, T. Winster, R. Trichur, Mario Saliba, F. Song, F. Roick, Simon Heitmann, Bernd Roesener, Johan Stelling
New technology trends in smart electronics are driving advanced semiconductor packaging innovations. Mobile RF and automotive IC designs, as examples, continue to evolve towards architectures requiring greater functionality, better shielding at higher frequencies, miniaturization, higher robustness/ ruggedness, and with lower power consumption. In turn, the architecture enhancements put new demands on semiconductor encapsulant material development and criteria. To meet these challenges, new types of SVHC-free, low warpage, liquid compression molding (LCM) encapsulants were developed with Cu Plating capability by laser direct structuring (LDS). Electroless Cu plating of 25/25 μm L/S lasered tracks and lasered through mold vias (TMVs) down to 50 μm have already been demonstrated during 2021.This presentation will cover further material development on a new LDS encapsulant applied via stencil printing aiming for <50 μm thin dielectric layers with 15/15 μm L/S Cu tracks and <50 μm Cu plated TMVs/ blind vias. These metrics provide opportunity for more functionality with even smaller package footprints vs todays' granular and transfer molding encapsulation methods. Moreover, this liquid LDS technology can improve final device building efficiency by introducing only three backend approved processing steps (encapsulation, lasering and plating) versus a typical less efficient mask and lithography based semi-additive process. In contrast to subtractive and semi-additive technologies, LDS is a truly additive, highly selective, and direct technology which provides additional metal planes directly on the encapsulant. And supporting a more sustainable and natural resources saving backend manufacturing of semiconductor packages.
{"title":"Laser Direct Structuring of Semiconductor Liquid Encapsulants for Active Mold Packaging","authors":"Chunlin He, Ruud DeWit, Jay Chao, Tim Champagne, R. Guino, T. Winster, R. Trichur, Mario Saliba, F. Song, F. Roick, Simon Heitmann, Bernd Roesener, Johan Stelling","doi":"10.1109/ectc51906.2022.00205","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00205","url":null,"abstract":"New technology trends in smart electronics are driving advanced semiconductor packaging innovations. Mobile RF and automotive IC designs, as examples, continue to evolve towards architectures requiring greater functionality, better shielding at higher frequencies, miniaturization, higher robustness/ ruggedness, and with lower power consumption. In turn, the architecture enhancements put new demands on semiconductor encapsulant material development and criteria. To meet these challenges, new types of SVHC-free, low warpage, liquid compression molding (LCM) encapsulants were developed with Cu Plating capability by laser direct structuring (LDS). Electroless Cu plating of 25/25 μm L/S lasered tracks and lasered through mold vias (TMVs) down to 50 μm have already been demonstrated during 2021.This presentation will cover further material development on a new LDS encapsulant applied via stencil printing aiming for <50 μm thin dielectric layers with 15/15 μm L/S Cu tracks and <50 μm Cu plated TMVs/ blind vias. These metrics provide opportunity for more functionality with even smaller package footprints vs todays' granular and transfer molding encapsulation methods. Moreover, this liquid LDS technology can improve final device building efficiency by introducing only three backend approved processing steps (encapsulation, lasering and plating) versus a typical less efficient mask and lithography based semi-additive process. In contrast to subtractive and semi-additive technologies, LDS is a truly additive, highly selective, and direct technology which provides additional metal planes directly on the encapsulant. And supporting a more sustainable and natural resources saving backend manufacturing of semiconductor packages.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125652377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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