Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357879
Chih-Chang Lee, Tzu-Yi Yang
We propose a common-mode variable voltage (CMW) method to improve the bandwidth of low pass filter for ultra-wideband (UWB) transmitter. It is based on leap-frog structure to design a 250 MHz 8th -order GM-C Chebyshev low pass filter. In the analytic results, tuning the common-mode reference voltage (VCM) of common-mode feedback circuits of transconductor, the cutoff frequency of filter can be calibrated to overcome the process variation and temperature dependencies. This approach can effectively reduce the chip size and do not need excess circuits. The filter combines a resistor network and 4times13 decoder to program the gain of filter and is implemented in a CMOS 0.18 mum process and power dissipation is 18 mW under 1.8 V power supply. Measurement results show that the filter can be reformed 50% bandwidth and the gain can be programmed from -14 dB to -38 dB with 2 dB step. The attenuation at 285 MHz and 330 MHz is 16 dB and 32 dB, respectively, and the total harmonic distortion (THD) of programmable gain filter is -37 dBc for 1Vpp differential input signal at 150 MHz.
{"title":"A Tuning Technique for Bandwidth of Programmable Gain Filter","authors":"Chih-Chang Lee, Tzu-Yi Yang","doi":"10.1109/ASSCC.2006.357879","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357879","url":null,"abstract":"We propose a common-mode variable voltage (CMW) method to improve the bandwidth of low pass filter for ultra-wideband (UWB) transmitter. It is based on leap-frog structure to design a 250 MHz 8th -order GM-C Chebyshev low pass filter. In the analytic results, tuning the common-mode reference voltage (VCM) of common-mode feedback circuits of transconductor, the cutoff frequency of filter can be calibrated to overcome the process variation and temperature dependencies. This approach can effectively reduce the chip size and do not need excess circuits. The filter combines a resistor network and 4times13 decoder to program the gain of filter and is implemented in a CMOS 0.18 mum process and power dissipation is 18 mW under 1.8 V power supply. Measurement results show that the filter can be reformed 50% bandwidth and the gain can be programmed from -14 dB to -38 dB with 2 dB step. The attenuation at 285 MHz and 330 MHz is 16 dB and 32 dB, respectively, and the total harmonic distortion (THD) of programmable gain filter is -37 dBc for 1Vpp differential input signal at 150 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357884
I. Lai, Y. Kambayashi, M. Fujishima
A cascade CMOS mixer is fabricated to exploit the unlicensed band around 60 GHz. This topology avoids the need for area-consuming power combining and uses simple matching with slow-wave transmission lines (SWTL). SWTL has a higher quality factor and allows area reduction. The circuit is fabricated in standard digital 90-nm CMOS and has a radio frequency (RF) return-loss more than 10 dB between 46 GHz and 64 GHz. At RF of 60 GHz, intermediate frequency (IF) of 4 GHz and local oscillator (LO) power of 1.5 dBm, the conversion loss is 1.2 dB and an input-referred 1-dB compression point of 0.5 dBm was measured. The length reduction of the transmission lines achieved is 47% and the resulting chip occupies an area of 0.61 mm x 0.80 mm with comparable performance to other works.
制作了级联CMOS混频器来利用60 GHz左右的未授权频段。这种拓扑结构避免了占用面积的功率组合，并与慢波传输线(SWTL)进行简单匹配。SWTL具有更高的质量因子，并允许缩小面积。该电路采用标准的数字90纳米CMOS制造，在46 GHz和64 GHz之间的射频(RF)回波损耗大于10 dB。在RF为60 GHz，中频为4 GHz，本振功率为1.5 dBm时，转换损耗为1.2 dB，测量到输入参考1 dB压缩点为0.5 dBm。传输线长度减少了47%，芯片面积为0.61 mm x 0.80 mm，性能与其他产品相当。
{"title":"60-GHz CMOS Down-Conversion Mixer with Slow-Wave Matching Transmission Lines","authors":"I. Lai, Y. Kambayashi, M. Fujishima","doi":"10.1109/ASSCC.2006.357884","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357884","url":null,"abstract":"A cascade CMOS mixer is fabricated to exploit the unlicensed band around 60 GHz. This topology avoids the need for area-consuming power combining and uses simple matching with slow-wave transmission lines (SWTL). SWTL has a higher quality factor and allows area reduction. The circuit is fabricated in standard digital 90-nm CMOS and has a radio frequency (RF) return-loss more than 10 dB between 46 GHz and 64 GHz. At RF of 60 GHz, intermediate frequency (IF) of 4 GHz and local oscillator (LO) power of 1.5 dBm, the conversion loss is 1.2 dB and an input-referred 1-dB compression point of 0.5 dBm was measured. The length reduction of the transmission lines achieved is 47% and the resulting chip occupies an area of 0.61 mm x 0.80 mm with comparable performance to other works.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"77 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357883
S. Reynolds, J. Powell
Double-conversion superheterodyne downconverter blocks operating around 77 GHz and 94 GHz have been realized in 0.13-mum SiGe BiCMOS technology. Both use a single-balanced RF mixer to downconvert the signal to an 8.8 GHz IF, which is amplified and downconverted a second time to baseband. The 77-GHz circuit achieves an upper SSB NF of 12.8 dB at 77 GHz and <12 dB at 76 GHz, with 20 dB of conversion gain and an input-referred 1-dB compression point of -14.7 dBm. The 94-GHz circuit achieves an upper SSB NF of 17.2 dB at 94 GHz, with 15 dB of conversion gain and an input-referred 1-dB compression point of -10.7 dBm. Both circuits use a bias current of 3.2 mA in the RF mixer core, with total testsite power consumption of 120 mA from a 3-V supply.
{"title":"77 and 94-GHz Downconversion Mixers in SiGe BiCMOS","authors":"S. Reynolds, J. Powell","doi":"10.1109/ASSCC.2006.357883","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357883","url":null,"abstract":"Double-conversion superheterodyne downconverter blocks operating around 77 GHz and 94 GHz have been realized in 0.13-mum SiGe BiCMOS technology. Both use a single-balanced RF mixer to downconvert the signal to an 8.8 GHz IF, which is amplified and downconverted a second time to baseband. The 77-GHz circuit achieves an upper SSB NF of 12.8 dB at 77 GHz and <12 dB at 76 GHz, with 20 dB of conversion gain and an input-referred 1-dB compression point of -14.7 dBm. The 94-GHz circuit achieves an upper SSB NF of 17.2 dB at 94 GHz, with 15 dB of conversion gain and an input-referred 1-dB compression point of -10.7 dBm. Both circuits use a bias current of 3.2 mA in the RF mixer core, with total testsite power consumption of 120 mA from a 3-V supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357896
Yonggang Chen, R. Jaeger, J. Suhling
A CMOS stress sensor is merged with a delta-sigma modulator to produce a sensor with a low frequency RF output. A PMOS current mirror with two orthogonal transistors is used as the stress sensor. The delta-sigma modulator generates an output signal that can be processed digitally or monitored by a communications receiver. The frequency shift of the DSBSC output of the modulator is directly proportional to the stress induced mismatch in the sensor cell. A test chip demonstrating the sensor has been fabricated using the 1.5 mum MOSIS CMOS process.
将CMOS应力传感器与δ - σ调制器合并，产生具有低频RF输出的传感器。采用两个正交晶体管的PMOS电流反射镜作为应力传感器。δ - σ调制器产生一个输出信号，该信号可以被数字处理或由通信接收器监控。调制器DSBSC输出的频移与传感器单元中应力引起的失配成正比。采用1.5 μ m MOSIS CMOS工艺制作了演示传感器的测试芯片。
{"title":"Delta-Sigma Based CMOS Stress Sensor with RF Output","authors":"Yonggang Chen, R. Jaeger, J. Suhling","doi":"10.1109/ASSCC.2006.357896","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357896","url":null,"abstract":"A CMOS stress sensor is merged with a delta-sigma modulator to produce a sensor with a low frequency RF output. A PMOS current mirror with two orthogonal transistors is used as the stress sensor. The delta-sigma modulator generates an output signal that can be processed digitally or monitored by a communications receiver. The frequency shift of the DSBSC output of the modulator is directly proportional to the stress induced mismatch in the sensor cell. A test chip demonstrating the sensor has been fabricated using the 1.5 mum MOSIS CMOS process.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357881
M. Motoyoshi, Minoru Fujishima
A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18 μm CMOS, a divide-by-three HILD is realized with a power consumption of 43 μW, a maximum operating frequency of 6 GHz, and a locking range of 80% at a supply voltage of 0.7 V. The core size is 10.8 μm x 10.5 μm.
{"title":"43μW 6GHz CMOS Divide-by-3 Frequency Divider Based on Three-Phase Harmonic Injection Locking","authors":"M. Motoyoshi, Minoru Fujishima","doi":"10.1109/ASSCC.2006.357881","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357881","url":null,"abstract":"A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18 μm CMOS, a divide-by-three HILD is realized with a power consumption of 43 μW, a maximum operating frequency of 6 GHz, and a locking range of 80% at a supply voltage of 0.7 V. The core size is 10.8 μm x 10.5 μm.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129248910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357844
T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura
A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.
{"title":"A 10-bit 200MS/s Pipeline A/D Converter for High-Speed Video Signal Digitizer","authors":"T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura","doi":"10.1109/ASSCC.2006.357844","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357844","url":null,"abstract":"A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357869
T. Ishii, H. Ito, M. Kimura, K. Okada, K. Masu
This paper proposes an on-chip differential- transmission-line (DTL) interconnect to reduce delay and power consumption in long global interconnects. The DTL interconnect can transmit signals at near light-of-speed with small power dissipation of Tx. The proposed DTL interconnect consists of Tx, DTL and Rx, and an asymmetric Tx is employed to reduce offset delay in Tx. In the measurement result, 5 Gbps signal transmission can be achieved through 3 mm-length interconnect, and delay and total power consumption are 140 ps and 6.5 mW, respectively. A 180 nm standard CMOS process was utilized. Figure of merit (FoM) for on-chip interconnects is proposed to evaluate delay and power consumption. The proposed DTL interconnect is compared with the conventional RC, DTL and optical interconnects, and it achieves the highest FoM at more than 5 mm length.
{"title":"A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology","authors":"T. Ishii, H. Ito, M. Kimura, K. Okada, K. Masu","doi":"10.1109/ASSCC.2006.357869","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357869","url":null,"abstract":"This paper proposes an on-chip differential- transmission-line (DTL) interconnect to reduce delay and power consumption in long global interconnects. The DTL interconnect can transmit signals at near light-of-speed with small power dissipation of Tx. The proposed DTL interconnect consists of Tx, DTL and Rx, and an asymmetric Tx is employed to reduce offset delay in Tx. In the measurement result, 5 Gbps signal transmission can be achieved through 3 mm-length interconnect, and delay and total power consumption are 140 ps and 6.5 mW, respectively. A 180 nm standard CMOS process was utilized. Figure of merit (FoM) for on-chip interconnects is proposed to evaluate delay and power consumption. The proposed DTL interconnect is compared with the conventional RC, DTL and optical interconnects, and it achieves the highest FoM at more than 5 mm length.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129002967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357931
Youngdon Choi, D. Jeong, Wonchan Kim, Jung-Bae Lee, Changhyun Kim
This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.
{"title":"An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm","authors":"Youngdon Choi, D. Jeong, Wonchan Kim, Jung-Bae Lee, Changhyun Kim","doi":"10.1109/ASSCC.2006.357931","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357931","url":null,"abstract":"This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114555188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357878
M. Shen, Li-Han Hung, Po-Chiun Huang
This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.
本文介绍了一种低压CMOS全差分运算放大器。它包括三个增益级和两种补偿方案，缓冲反向嵌套米勒补偿(B-RNMC)和前馈跨导补偿(FFTC)。在B-RNMC中，在反馈路径中插入一个跨导级，以消除可能降低相位裕度的右半平面(RHP)零点。在FFTC中，前馈跨导有助于增强输出大信号响应。采用标准的0.35 μ m CMOS技术，测量结果表明，在环路输出负载下，直流增益大于90 dB，增益带宽积为8.9 MHz，相位裕度为86度。1.2 Vpp步骤的稳定时间为2.4 mus。在单个1.2V电源下，所有电路的功耗为342 muW。
{"title":"A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensations","authors":"M. Shen, Li-Han Hung, Po-Chiun Huang","doi":"10.1109/ASSCC.2006.357878","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357878","url":null,"abstract":"This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"243 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120971421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357841
D. Chih-Wei Chang, I-Tao Liao, S. Tseng, Chein-Wen Jen
PAC DSP is a 32-bit programmable DSP solution which is ideal for next-generation media-rich and multifunction portable devices, such as portable media player (PMP), personal digital assistant (PDA), and smart phones. It provides high computation power from its parallel processing of multiple signal processing instructions and achieves efficient energy consumption form its unique architecture/micro-architecture design. Also, it maintains high application flexibility with general programmability.
{"title":"PAC DSP Core and Its Applications","authors":"D. Chih-Wei Chang, I-Tao Liao, S. Tseng, Chein-Wen Jen","doi":"10.1109/ASSCC.2006.357841","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357841","url":null,"abstract":"PAC DSP is a 32-bit programmable DSP solution which is ideal for next-generation media-rich and multifunction portable devices, such as portable media player (PMP), personal digital assistant (PDA), and smart phones. It provides high computation power from its parallel processing of multiple signal processing instructions and achieves efficient energy consumption form its unique architecture/micro-architecture design. Also, it maintains high application flexibility with general programmability.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129612714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：