Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357867
M. Hariyama, N. Yokoyama, M. Kameyama
This paper presents a 1000-frame/sec stereo-matching VLSI for adaptive window-size control. To reduce the computational amount, the algorithm uses images divided into non-overlapping regions. The matching result is iteratively refined by reducing a window size. Window-parallel and pixel-parallel architecture is proposed to achieve to exploit the potential parallelism.
{"title":"1000 frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control","authors":"M. Hariyama, N. Yokoyama, M. Kameyama","doi":"10.1109/ASSCC.2006.357867","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357867","url":null,"abstract":"This paper presents a 1000-frame/sec stereo-matching VLSI for adaptive window-size control. To reduce the computational amount, the algorithm uses images divided into non-overlapping regions. The matching result is iteratively refined by reducing a window size. Window-parallel and pixel-parallel architecture is proposed to achieve to exploit the potential parallelism.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125310798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357844
T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura
A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.
{"title":"A 10-bit 200MS/s Pipeline A/D Converter for High-Speed Video Signal Digitizer","authors":"T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura","doi":"10.1109/ASSCC.2006.357844","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357844","url":null,"abstract":"A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357896
Yonggang Chen, R. Jaeger, J. Suhling
A CMOS stress sensor is merged with a delta-sigma modulator to produce a sensor with a low frequency RF output. A PMOS current mirror with two orthogonal transistors is used as the stress sensor. The delta-sigma modulator generates an output signal that can be processed digitally or monitored by a communications receiver. The frequency shift of the DSBSC output of the modulator is directly proportional to the stress induced mismatch in the sensor cell. A test chip demonstrating the sensor has been fabricated using the 1.5 mum MOSIS CMOS process.
将CMOS应力传感器与δ - σ调制器合并，产生具有低频RF输出的传感器。采用两个正交晶体管的PMOS电流反射镜作为应力传感器。δ - σ调制器产生一个输出信号，该信号可以被数字处理或由通信接收器监控。调制器DSBSC输出的频移与传感器单元中应力引起的失配成正比。采用1.5 μ m MOSIS CMOS工艺制作了演示传感器的测试芯片。
{"title":"Delta-Sigma Based CMOS Stress Sensor with RF Output","authors":"Yonggang Chen, R. Jaeger, J. Suhling","doi":"10.1109/ASSCC.2006.357896","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357896","url":null,"abstract":"A CMOS stress sensor is merged with a delta-sigma modulator to produce a sensor with a low frequency RF output. A PMOS current mirror with two orthogonal transistors is used as the stress sensor. The delta-sigma modulator generates an output signal that can be processed digitally or monitored by a communications receiver. The frequency shift of the DSBSC output of the modulator is directly proportional to the stress induced mismatch in the sensor cell. A test chip demonstrating the sensor has been fabricated using the 1.5 mum MOSIS CMOS process.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357941
D. Fang, R. Roberts, B. Nikolić
A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.
一种并联、12 μ m间距、低功耗6-b分段数模转换器(DAC)阵列在2.5/1 V 90nm CMOS工艺中驱动3 μ m x 3 μ m模拟DRAM单元阵列，应用于无掩模光刻。创新的自校准补偿电路将电荷泄漏和电容过程失配的影响限制在100 ms数据保持时间内小于0.5 LSB。一个2mm × 2mm的测试芯片实现了一个混合信号接口，32个dac驱动4个32 × 256模拟DRAM阵列。
{"title":"A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS","authors":"D. Fang, R. Roberts, B. Nikolić","doi":"10.1109/ASSCC.2006.357941","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357941","url":null,"abstract":"A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129506913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357883
S. Reynolds, J. Powell
Double-conversion superheterodyne downconverter blocks operating around 77 GHz and 94 GHz have been realized in 0.13-mum SiGe BiCMOS technology. Both use a single-balanced RF mixer to downconvert the signal to an 8.8 GHz IF, which is amplified and downconverted a second time to baseband. The 77-GHz circuit achieves an upper SSB NF of 12.8 dB at 77 GHz and <12 dB at 76 GHz, with 20 dB of conversion gain and an input-referred 1-dB compression point of -14.7 dBm. The 94-GHz circuit achieves an upper SSB NF of 17.2 dB at 94 GHz, with 15 dB of conversion gain and an input-referred 1-dB compression point of -10.7 dBm. Both circuits use a bias current of 3.2 mA in the RF mixer core, with total testsite power consumption of 120 mA from a 3-V supply.
{"title":"77 and 94-GHz Downconversion Mixers in SiGe BiCMOS","authors":"S. Reynolds, J. Powell","doi":"10.1109/ASSCC.2006.357883","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357883","url":null,"abstract":"Double-conversion superheterodyne downconverter blocks operating around 77 GHz and 94 GHz have been realized in 0.13-mum SiGe BiCMOS technology. Both use a single-balanced RF mixer to downconvert the signal to an 8.8 GHz IF, which is amplified and downconverted a second time to baseband. The 77-GHz circuit achieves an upper SSB NF of 12.8 dB at 77 GHz and <12 dB at 76 GHz, with 20 dB of conversion gain and an input-referred 1-dB compression point of -14.7 dBm. The 94-GHz circuit achieves an upper SSB NF of 17.2 dB at 94 GHz, with 15 dB of conversion gain and an input-referred 1-dB compression point of -10.7 dBm. Both circuits use a bias current of 3.2 mA in the RF mixer core, with total testsite power consumption of 120 mA from a 3-V supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357877
Tien-Yu Lo, C. Hung
A novel configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60dB third-order inter- modulation (IM3) distortion for up to 0.9 VPP at 40 MHz. Ths OTA was fabricated by the TSMC 180-nm Deep N-WELL CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.
{"title":"1.5-V Linear CMOS OTA with -60dB IM3 for High Frequency Applications","authors":"Tien-Yu Lo, C. Hung","doi":"10.1109/ASSCC.2006.357877","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357877","url":null,"abstract":"A novel configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60dB third-order inter- modulation (IM3) distortion for up to 0.9 VPP at 40 MHz. Ths OTA was fabricated by the TSMC 180-nm Deep N-WELL CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357931
Youngdon Choi, D. Jeong, Wonchan Kim, Jung-Bae Lee, Changhyun Kim
This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.
{"title":"An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm","authors":"Youngdon Choi, D. Jeong, Wonchan Kim, Jung-Bae Lee, Changhyun Kim","doi":"10.1109/ASSCC.2006.357931","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357931","url":null,"abstract":"This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114555188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357878
M. Shen, Li-Han Hung, Po-Chiun Huang
This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.
本文介绍了一种低压CMOS全差分运算放大器。它包括三个增益级和两种补偿方案，缓冲反向嵌套米勒补偿(B-RNMC)和前馈跨导补偿(FFTC)。在B-RNMC中，在反馈路径中插入一个跨导级，以消除可能降低相位裕度的右半平面(RHP)零点。在FFTC中，前馈跨导有助于增强输出大信号响应。采用标准的0.35 μ m CMOS技术，测量结果表明，在环路输出负载下，直流增益大于90 dB，增益带宽积为8.9 MHz，相位裕度为86度。1.2 Vpp步骤的稳定时间为2.4 mus。在单个1.2V电源下，所有电路的功耗为342 muW。
{"title":"A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensations","authors":"M. Shen, Li-Han Hung, Po-Chiun Huang","doi":"10.1109/ASSCC.2006.357878","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357878","url":null,"abstract":"This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"243 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120971421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357841
D. Chih-Wei Chang, I-Tao Liao, S. Tseng, Chein-Wen Jen
PAC DSP is a 32-bit programmable DSP solution which is ideal for next-generation media-rich and multifunction portable devices, such as portable media player (PMP), personal digital assistant (PDA), and smart phones. It provides high computation power from its parallel processing of multiple signal processing instructions and achieves efficient energy consumption form its unique architecture/micro-architecture design. Also, it maintains high application flexibility with general programmability.
{"title":"PAC DSP Core and Its Applications","authors":"D. Chih-Wei Chang, I-Tao Liao, S. Tseng, Chein-Wen Jen","doi":"10.1109/ASSCC.2006.357841","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357841","url":null,"abstract":"PAC DSP is a 32-bit programmable DSP solution which is ideal for next-generation media-rich and multifunction portable devices, such as portable media player (PMP), personal digital assistant (PDA), and smart phones. It provides high computation power from its parallel processing of multiple signal processing instructions and achieves efficient energy consumption form its unique architecture/micro-architecture design. Also, it maintains high application flexibility with general programmability.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129612714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357880
J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim
We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.
{"title":"A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology","authors":"J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim","doi":"10.1109/ASSCC.2006.357880","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357880","url":null,"abstract":"We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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