Microelectronic Engineering最新文献_第9页

Theoretical insights into the impact of border and interface traps on hysteresis in monolayer MoS2 FETs 边界和界面陷阱对单层MoS2场效应管迟滞影响的理论见解

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-03-08 DOI: 10.1016/j.mee.2025.112333

Rittik Ghosh, Alexandros Provias, Alexander Karl, Christoph Wilhelmer, Theresia Knobloch, Mohammad Rasool Davoudi, Seyed Mehdi Sattari-Esfahlan, Dominic Waldhör, Tibor Grasser

Threshold voltage hysteresis

(Δ V_{h})

in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based self-consistent modeling framework to investigate the impact of border and interface traps on

Δ V_{h}

and apply it to monolayer (1-L) MoS₂ field-effect transistors (FETs). The transient trapping and detrapping of charges during gate voltage sweeps across a wide range of frequencies and temperatures is analyzed using a two-state non-radiative multi-phonon (NMP) model. Our results reveal distinct dynamic responses for slow border and fast interface traps, with border traps exhibiting slower time constants due to larger relaxation energies and interface traps showing fast nuclear tunneling-dominated dynamics resulting from the smaller relaxation energies. These simulations highlights the critical role of the spatial and energetic distributions of the traps in determining

Δ V_{h}

, providing insights into the stability of 2D FETs and paving the way for improved device engineering.

二维晶体管传输特性中的阈值电压迟滞ΔVh是实现稳定二维CMOS集成电路的瓶颈。滞后主要归因于沟道/氧化物界面和氧化物中的陷阱。在这项研究中，我们提出了一个基于物理的自一致建模框架来研究边界和界面陷阱对ΔVh的影响，并将其应用于单层（1-L） MoS2场效应晶体管（fet）。利用双态非辐射多声子（NMP）模型分析了栅极电压在宽频率和温度范围内扫描时电荷的瞬态捕获和去捕获。我们的研究结果揭示了慢边界和快界面陷阱的不同动态响应，边界陷阱由于较大的弛豫能而表现出较慢的时间常数，而界面陷阱由于较小的弛豫能而表现出快速的核隧道主导动力学。这些模拟突出了陷阱的空间和能量分布在确定ΔVh中的关键作用，提供了对二维场效应管稳定性的见解，并为改进器件工程铺平了道路。

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引用次数: 0

On the feature accuracy of deep learning mask topography effect models 深度学习掩膜地形效应模型的特征精度研究

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-27 DOI: 10.1016/j.mee.2025.112332

Linus Engelmann , IrenaeusWlokas

A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.

利用生成式神经网络（GAN）方法开发了基于深度学习的光刻模型，并评估了其预测不同抗蚀高度航拍图像的能力。通过分析模型生成的航空图像与黄金图像之间的偏差以及关键维数（CD）值的差异，评估了GAN方法的性能。并根据各掩模的特征分布进行误差分析。对选定的模式及其航空图像进行定性比较，以评估局部误差，并通过均方根误差（RMS）定量评估全球精度。误差分析揭示了深度学习模型产生的导致与严格模型结果偏差最大的特征，并将误差分解为预测不足和预测过高特征的误差贡献。对深度学习模型产生的选定抗阻高度的航拍图像阵列进行了评估，揭示了随着抗阻高度的增加，误差也在增加。通过比较具有和不具有光学接近校正（OPC）特征的目标图案，说明了在计算光刻中应用深度学习技术的局限性。

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引用次数: 0

Impact of constant bias stress on reliability of IGZO thin-film transistors on softening polymer 恒定偏置应力对软化聚合物上IGZO薄膜晶体管可靠性的影响

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-25 DOI: 10.1016/j.mee.2025.112331

Gerardo Gutierrez-Heredia , Ovidio Rodriguez-Lopez , Pedro Emanuel Rocha-Flores , Walter E. Voit

This study analyzed the electrical behavior of indium‑gallium‑zinc-oxide (IGZO) thin-film transistors (TFTs) under different applied voltages. The IGZO TFTs were fabricated on a polymer substrate using full photolithographic processes. The electrical performance was monitored under constant bias stress for 10,000 s and the analysis revealed relatively high field-effect mobility (>10 cm²/Vs) when higher voltages (>5 V) were applied to the IGZO TFTs. Furthermore, the experimental results demonstrated shifts in the threshold voltage (V_TH), mobility, and saturation drain current, exhibiting a strong dependence on the applied voltage. After 10,000 s of bias stress, the threshold voltage shift varied by 0.5 V for the lowest applied voltage and exceeded 5 V for the higher values. Moreover, the electrical analysis indicated a significant reduction in the lifetime of IGZO TFTs when the applied voltage exceeded 15 V. These findings enable a comparative analysis of the impact of bias stress on mobility, V_TH, and driving current, offering a pathway to optimize the electrical performance of TFTs-based flexible applications. Furthermore, by exploring the mechanism behind the changes induced by the constant electric field at the gate contact, this work provides insights for predicting the reliability and lifetime of novel devices tailored for wearable, flexible, and biomedical technologies.

本研究分析了铟镓锌氧化物（IGZO）薄膜晶体管（TFT）在不同外加电压下的电气行为。IGZO TFT 是采用全光刻工艺在聚合物基底上制造的。在 10,000 秒的恒定偏压应力下对其电气性能进行了监测，分析结果表明，当对 IGZO TFT 施加较高电压（5 V）时，其场效应迁移率相对较高（10 cm2/Vs）。此外，实验结果表明，阈值电压 (VTH)、迁移率和饱和漏极电流都发生了变化，表现出对施加电压的强烈依赖性。经过 10,000 秒的偏压应力后，最低应用电压的阈值电压偏移为 0.5 V，而较高电压值的阈值电压偏移则超过了 5 V。此外，电学分析表明，当施加电压超过 15 V 时，IGZO TFT 的寿命会显著缩短。这些发现有助于比较分析偏压对迁移率、VTH 和驱动电流的影响，为优化基于 TFT 的柔性应用的电学性能提供了一条途径。此外，通过探索栅极接触处恒定电场诱导变化背后的机理，这项研究为预测为可穿戴、柔性和生物医学技术量身定制的新型器件的可靠性和使用寿命提供了见解。

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引用次数: 0

Thermal management of through-silicon vias and back-end-of-line layers in 3D ICs: A comprehensive review 3D集成电路中硅通孔和后端线层的热管理：综合综述

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-20 DOI: 10.1016/j.mee.2025.112325

Hongbang Zhang , Miao Tian , Xiaokun Gu

Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.

三维集成电路（3D ic）由于具有提高性能和降低功耗的潜力而成为半导体研究的前沿。随着半导体技术的进步，3D集成电路的不断小型化和集成密度的增加使得尺寸和界面效应更加明显，从而导致更高的热流密度和更复杂的热管理挑战。通过硅通孔（TSV）和后端线（BEOL）结构作为3D集成电路的核心部件，负责水平和垂直互连，并直接影响芯片内的热传输性能。在这篇综述中，我们概述了热管理在tsv和BEOL结构中的现状，讨论了散热性能，热参数提取，结构优化和布局算法的发展。针对跨尺度模拟的挑战以及表征复杂微纳结构的热性质和温度分布的困难，介绍了微纳尺度理论计算和热测试技术的现状，这些技术已经发展成为三维集成电路热管理的有力工具。本文总结了该领域的主要进展和挑战，强调了解决这些问题对优化tsv和BEOL设计，提高3D集成电路的热管理性能的重要性，为未来的研究提供了有价值的参考和指导。

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引用次数: 0

Optimization of read operation for low power consumption in 3D NAND flash memory 3D NAND快闪记忆体低功耗读取操作之优化

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-20 DOI: 10.1016/j.mee.2025.112324

Jesun Park , Seongwoo Kim , Taeyoung Cho , Myounggon Kang

This study proposes a low power read operation to minimize the hot carrier injection (HCI) phenomenon that occurs during read operations in 3D NAND Flash Memory. Owing to the characteristics of the 3D NAND Flash Memory structure, the channels of unselected strings can easily remain in a floating state. This leads to HCI during read operations, resulting in read disturbances. To improve the read disturb characteristics, triangular pulse voltages (V_TP) with adjusted slopes and delayed application times were applied to the string selected line (SSL) and the ground selected line (GSL) during read operations. Using the proposed read scheme, it was confirmed that HCI was decreased compared to the conventional method, and it was possible to operate at low power.

本研究提出了一种低功耗读取操作，以最大限度地减少3D NAND闪存读取操作过程中发生的热载流子注入（HCI）现象。由于3D NAND闪存结构的特性，未选择串的通道很容易保持在浮动状态。这将导致读操作期间的HCI，从而导致读干扰。为了改善读干扰特性，在读操作过程中，对串选线（SSL）和地选线（GSL）施加可调整斜率和延迟施加时间的三角形脉冲电压（VTP）。采用所提出的读取方案，与传统方法相比，HCI降低了，并且可以在低功耗下工作。

引用次数: 0

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography 边珠去除（EBR）工艺的优化，以提高光刻中缺陷的减少

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-17 DOI: 10.1016/j.mee.2025.112330

Bishnu P. Khanal, Marlene Dugger

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination.

In this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

减少缺陷仍然是集成电路制造过程中的一个关键目标，特别是在高度可重复使用的光刻模块中，最大限度地减少缺陷是至关重要的。晶圆边缘的缺陷会污染光刻模块和下游加工设备，导致重新分布到晶圆表面，并对整体器件良率产生不利影响。在抗蚀剂涂层过程中，一个持续的挑战是由过量光刻胶（PR）对自身和底层基材的强烈范德华吸引力驱动的抗蚀剂边缘珠的形成。边缘珠去除（EBR）过程是一个标准的清洁步骤，旨在消除这些边缘珠和防止潜在的污染。在这项研究中，我们确定了在EBR清洗过程中，EBR引起的缺陷和额外的EBR过程对边缘图案的侵蚀的来源。本研究对优化EBR清洗工艺进行了全面的研究，以有效消除EBR引起的缺陷，从而提高整体器件良率。具体来说，我们确定了由EBR清洁过程引起的三种主要缺陷：彩虹型、手指型和泪滴型缺陷。我们的实验研究表明，除了EBR冲洗时间外，PR浇铸时间是导致这些缺陷形成的关键参数。通过适当优化PR浇铸时间和EBR冲洗时间，我们能够消除几乎100%的密集缺陷簇，即使在整个晶圆边缘的低倍率光学显微镜下也很容易看到。我们观察到，较短的PR浇铸时间显示了由于EBR工艺效率低下导致的边缘缺陷，因为PR没有足够的时间完全沉淀，导致多余的PR在EBR清除步骤中继续流向晶圆边缘，导致晶圆边缘部分PR去除，形成彩虹缺陷。适当优化PR浇铸时间和EBR化学剂分配时间对于解决这些缺陷至关重要，从而确保高效的EBR清洗过程和提高整体设备良率。

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引用次数: 0

Neural network for in-sensor time series recognition based on optoelectronic memristor 基于光电忆阻器的传感器内时间序列识别神经网络

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-17 DOI: 10.1016/j.mee.2025.112329

Zhang Zhang , Qifan Wang , Gang Shi , Gang Liu

In recent years, inspired by multifunctional image sensors, in-sensor computing technology that combines sensing and computing functions has become a new research hotspot in the field of machine vision, which is an extremely promising way to break through the Von Neumann architecture by equipping the sensing unit with the computing ability and avoiding the data moving in the computation process. Whereas most existing in-sensor computing systems can only realize the processing of spatial frames in-sensor and cannot fuse the time series information. In order to solve this limitation and realize the processing of time information and spatial frames in the sensor at the same time, it is necessary to decouple and process the information in the processing unit in the sensor. In this paper, a time series recognition neural network based on optoelectronic memristor arrays is proposed. By using the optical plasticity and relaxation effects of the optoelectronic memristor arrays and based on the in-sensor computing technology, the information timing decoupling, processing and recognition in the sensor are realized. The results show that the network achieves a time series recognition accuracy of 98.4 % with two frames of image input, and the recognition rate still reaches 90 % after weight quantization and the addition of 40 % noise.

近年来，受多功能图像传感器的启发，结合传感和计算功能的传感器内计算技术成为机器视觉领域的一个新的研究热点，通过赋予传感单元计算能力，避免计算过程中数据的移动，是一种极具前景的突破冯·诺依曼架构的方法。而现有的传感器内计算系统大多只能实现传感器内空间帧的处理，无法融合时间序列信息。为了解决这一限制，实现传感器中时间信息和空间帧的同时处理，需要对传感器中处理单元中的信息进行解耦和处理。本文提出了一种基于光电忆阻器阵列的时间序列识别神经网络。利用光电忆阻器阵列的光塑性和弛豫效应，基于传感器内计算技术，实现了传感器内信息的时序解耦、处理和识别。结果表明，在输入两帧图像的情况下，该网络的时间序列识别准确率达到98.4%，在权值量化和加入40%噪声后，识别率仍达到90%。

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引用次数: 0

Optimization of pattern quality in DMD scanning maskless lithography: A parametric study of the OS3L exposure algorithm DMD扫描无掩模光刻中图案质量的优化：OS3L曝光算法的参数化研究

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-14 DOI: 10.1016/j.mee.2025.112328

Ting-Hsuan Miau , Yung-Chun Lee

In digital micromirror device (DMD) scanning maskless lithography systems, the pattern accuracy has a critical effect on the final component quality. However, the patterning performance is highly sensitive to the parameters used in the scanning process. Accordingly, this study examines the effects of three key parameters (the rotation angle of the DMD array, the step size, and the optical distortion of the image projection lens) on the patterning quality of a DMD-based scanning maskless lithography system utilizing an oblique scanning and step-strobe lighting (OS³L) exposure algorithm. The MATLAB simulation results show that the optical distortion of the image projection lens causes an uneven distribution of the exposure points along the x-axis direction, with sparser focal spots on the sides of the exposure field and denser spots in the center. In addition, the results suggest that the DMD rotation angle should be close to (but not less than) the critical angle, i.e., the angle at which the maximum horizontal resolution is obtained. Finally, the light spot distribution is extremely sensitive to the step size, but the relationship between them is unpredictable and nonlinear. Consequently, the effects of the step size on the light spot distribution should be checked on a case-by-case basis. Overall, the results presented in this study provide useful guidelines for the selection of the parameter settings that optimize the patterning quality in DMD-based scanning maskless lithography systems using the OS³L exposure algorithm.

在数字微镜器件（DMD）扫描无掩模光刻系统中，图案精度对最终元件质量有至关重要的影响。然而，图形性能对扫描过程中使用的参数高度敏感。因此，本研究考察了三个关键参数（DMD阵列的旋转角度，步长和图像投影透镜的光学畸变）对基于DMD的扫描无掩模光刻系统的图案质量的影响，该系统采用倾斜扫描和步进频闪照明（OS3L）曝光算法。MATLAB仿真结果表明，像投影透镜的光学畸变导致曝光点沿x轴方向分布不均匀，曝光场两侧的焦斑较稀疏，中心的焦斑较密集。此外，结果表明，DMD旋转角度应接近（但不小于）临界角，即获得最大水平分辨率的角度。最后，光斑分布对步长非常敏感，但它们之间的关系是不可预测的和非线性的。因此，步长对光斑分布的影响应逐案检查。总的来说，本研究的结果为选择参数设置提供了有用的指导，这些参数设置可以优化基于dmd的扫描无掩模光刻系统中使用OS3L曝光算法的图案质量。

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引用次数: 0

Amorphous indium gallium zinc oxide thin film transistors (a-IGZO-TFTs): Exciting prospects and fabrication challenges 非晶铟镓氧化锌薄膜晶体管（a-IGZO-TFTs）：令人兴奋的前景和制造挑战

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-08 DOI: 10.1016/j.mee.2025.112327

J. Ajayan , S. Sreejith , N. Aruna Kumari , M. Manikandan , Sachidananda Sen , Maneesh Kumar

In today's consumer electronics market, major manufacturing companies may be profitable and scalable thanks to technologies like thin-film transistors (TFTs). TFTs are found in TVs, smartphones, laptops, brain-like synaptic transistors, back-planes in CMOS image sensors, integrated circuits (ICs), flexible & wearable electronics, power switching circuits, back-end-of-line (BEOL) transistor elements in 3D-logic and cell transistors in dynamic random-access memory (DRAM). They have also been proposed as a potential solution for flexible CPUs. A high mobility of 74.4 cm²/Vs and I_ON/I_OFF of 3.39 × 10⁹ and a V_ON of less than ±0.1 V and a SS of less than 0.1 V/dec were achieved in a-IGZO based TFTs. Numerous efforts have been made to enhance the a-IGZO TFTs' electrical characteristics by optimizing the fabrication process. Numerous studies have also addressed the instability problems, such as the a-IGZO devices' hot-carrier effects, self-heating, and charge-trapping. TFTs with a-IGZO are being extensively studied adopting the a vertical-channel approach in order to be used in 3-D electronic devices. This article reviews the recent developments in materials and architectures, performance overview of IGZO-TFTs, advances and challenges in fabrication technologies and reliability issues & degradation mechanisms of IGZO-TFTs.

在今天的消费电子市场上，由于薄膜晶体管（tft）等技术，大型制造公司可能会盈利并可扩展。tft广泛应用于电视、智能手机、笔记本电脑、类脑突触晶体管、CMOS图像传感器背板、集成电路（ic）、柔性电子放大器等领域。可穿戴电子产品，电源开关电路，3d逻辑中的后端（BEOL）晶体管元件和动态随机存取存储器（DRAM）中的单元晶体管。它们也被提议作为灵活cpu的潜在解决方案。在基于A - igzo的TFTs中获得了74.4 cm2/Vs的高迁移率和3.39 × 109的离子/离合比，VON小于±0.1 V和SS小于0.1 V/dec。通过优化制造工艺来提高a-IGZO tft的电学特性已经做了大量的努力。许多研究也解决了不稳定性问题，如a-IGZO器件的热载子效应、自加热和电荷捕获。为了在三维电子器件中应用，采用垂直通道方法对具有a- igzo的tft进行了广泛的研究。本文综述了材料和结构的最新发展，igzo - tft的性能概述，制造技术的进步和挑战以及可靠性问题。igzo - tft的降解机制。

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引用次数: 0

Spin coating in semiconductor lithography: Advances in modeling and future prospects 半导体光刻中的自旋镀膜：建模进展及未来展望

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-02-07 DOI: 10.1016/j.mee.2025.112326

Pan Liu , Liejie Huang , Chaoyi Zheng , Yanan Bao , Dawei Gao , Guodong Zhou

With the development of advanced integrated circuit technologies, semiconductor manufacturing processes have become increasingly important. Photolithography is one of the most critical and costly steps in chip manufacturing, and the quality of the photoresist film formed during the subprocess of spin-coating significantly impacts photolithography performance. The thickness of photoresist films ranges from several hundred nanometers to tens of micrometers, with uniformity requirements typically within ±1 %. These stringent specifications pose significant challenges to the stability and precision of the spin coating process. This review outlines the research progress on spin-coating and discusses various model-building methods, including theoretical analysis, experimentation, simulation, and machine learning. The paper highlights new experimental approaches and recent advancements aimed at optimizing the spin-coating process under different conditions.

随着先进集成电路技术的发展，半导体制造工艺变得越来越重要。光刻是芯片制造中最关键、最昂贵的步骤之一，而在旋转镀膜子过程中形成的光刻胶膜的质量对光刻性能有重要影响。光刻胶薄膜的厚度范围从几百纳米到几十微米，均匀性要求通常在±1%以内。这些严格的规范对旋转涂层工艺的稳定性和精度提出了重大挑战。本文综述了旋涂技术的研究进展，并讨论了旋涂技术的各种建模方法，包括理论分析、实验、仿真和机器学习。本文重点介绍了在不同条件下优化旋涂工艺的新实验方法和最新进展。

引用次数: 0