Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733455
Zong-Yu Xie, I-You Yu, Jenn-Ming Song, D. Tarng, C. Hung
This study aims to investigate microstructural effect on direct Cu bonding. Electro-deposited Cu samples with different grain sizes, preferred orientations as well as hardnesses were prepared. The influence of individual factors will be studied especially grain size. Experimental results show that through grain refinement the strength of directly-bonded electroplated copper joints can be effectively increased by 30%.
{"title":"Influence of Grain Refinement on Direct Bonding for Electrodeposited Copper","authors":"Zong-Yu Xie, I-You Yu, Jenn-Ming Song, D. Tarng, C. Hung","doi":"10.23919/ICEP.2019.8733455","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733455","url":null,"abstract":"This study aims to investigate microstructural effect on direct Cu bonding. Electro-deposited Cu samples with different grain sizes, preferred orientations as well as hardnesses were prepared. The influence of individual factors will be studied especially grain size. Experimental results show that through grain refinement the strength of directly-bonded electroplated copper joints can be effectively increased by 30%.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130804674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733413
Jen-Hsiang Liu, Yan-Jie Li, Jenn-Ming Song
Taking the advantage of low sintering temperature and high processing flexibility, Ag nanoparticles have been widely used to fabricate interconnections and joints. This report studies the preferred orientation of the sintered nanoparticles and electrical resistivity subjected to thermal or/and chemical reductions using grazing incidence XRD and EBSD. Submicron-sized Ag powders prepared by thermal spray pyrolysis are also investigated for comparison. Compared to chemical reduction which develops (111) out-of-plane texture, thermal sintering of nanoparticles tends to form (100)-oriented grains and more twin boundaries. A decrease in sintered film thickness further intensifies (111) texture in the case of chemical sintering. A proportional relationship between electrical conductance and twin boundary ratio was also proposed.
{"title":"Microstructural and Electrical Characteristics of Sintered Ag Interconnections through Different Reduction Methods","authors":"Jen-Hsiang Liu, Yan-Jie Li, Jenn-Ming Song","doi":"10.23919/ICEP.2019.8733413","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733413","url":null,"abstract":"Taking the advantage of low sintering temperature and high processing flexibility, Ag nanoparticles have been widely used to fabricate interconnections and joints. This report studies the preferred orientation of the sintered nanoparticles and electrical resistivity subjected to thermal or/and chemical reductions using grazing incidence XRD and EBSD. Submicron-sized Ag powders prepared by thermal spray pyrolysis are also investigated for comparison. Compared to chemical reduction which develops (111) out-of-plane texture, thermal sintering of nanoparticles tends to form (100)-oriented grains and more twin boundaries. A decrease in sintered film thickness further intensifies (111) texture in the case of chemical sintering. A proportional relationship between electrical conductance and twin boundary ratio was also proposed.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122305967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733474
T. Koshi, E. Iwase
We developed a self-healing metal interconnect and applied it to a flexible electronic device. The self-healing metal interconnect regains its conductivity again even if the interconnect is broken by stretching deformation. For the selfhealing, dielectrophoresis of metal nanoparticles is used. In this paper, design, fabrication, and evaluation of a flexible electronic device using self-healing metal interconnects are described. The device was composed of self-healing metal interconnects and surface-mounted light emitting diode (LED) chips. We confirmed a decrease of impedance of the device and re-emitting of LED chips by self-healing of the broken interconnect.
{"title":"Self-Healing Metal Interconnect for Flexible Electronic Device","authors":"T. Koshi, E. Iwase","doi":"10.23919/ICEP.2019.8733474","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733474","url":null,"abstract":"We developed a self-healing metal interconnect and applied it to a flexible electronic device. The self-healing metal interconnect regains its conductivity again even if the interconnect is broken by stretching deformation. For the selfhealing, dielectrophoresis of metal nanoparticles is used. In this paper, design, fabrication, and evaluation of a flexible electronic device using self-healing metal interconnects are described. The device was composed of self-healing metal interconnects and surface-mounted light emitting diode (LED) chips. We confirmed a decrease of impedance of the device and re-emitting of LED chips by self-healing of the broken interconnect.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127910931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733523
T. Murayama, T. Sakuishi, Y. Morikawa
In recent years, discussion on power consumption and latency of GPU used for AI application has started. In order to realize further high-speed processing and low power consumption of the GPU processing a huge amount of data, it is necessary to consider the packaging structure of the GPU [1]. The current GPU package structure is based on the package substrate using flip chip PoP (Package on Package) technology and Si interposer. In this structure applied, the wiring distance is increased due to the structural restriction of signal transmission through the Si interposer on the package substrate, which is the cause of the increase in power consumption and latency. Therefore, the packaging structure around the Si interposer has been focused, and expected structures that does not use the Si interposer have been proposed [2]. A method of directly forming fine wiring layers which plays a role of RDL (Redistributed Layer) by using a photosensitive insulation material on a build-up substrate without using a Si interposer has been reported [3]. Furthermore, in view of the high frequency trend of the signal frequency, the development of glass-epoxy materials having low Df (dielectric loss constant) and low Dk (dielectric constant) material properties as a build-up film is proceeding [4]. It is expected that it will be a more effective method to effectively utilize the characteristics of low Df and low Dk and to form fine wiring on the build-up layer using semiconductor fine wiring technology. For future high density packaging, plasma dry etching technology aiming fabrication of multilayer wiring on build-up film has been developed [5].In this paper, the results of microfabrication of build-up thickness of 5 μm are reported for the purpose of fabricating fine wiring on build-up film using dry process. This technology has been developed as one of new SiP (System in Package) technologies for realizing future heterogeneous integration. The process results of dry etching and Cu electroplating are described. In order to adapt to chip mounting, the size of the wiring formed in the build-up layer is targeted at line / space = 2 μm / 2 μm. The reason for using Si substrate instead of mold panel is because it is suitable for use of expensive NGD (known good die). In Si semiconductor packaging, very stable technology corresponding to Si substrate of 300 mm size has been established up to today. And, for Cu fine wiring formation on a build-up film using a dry process, it is also necessary to ensure sufficient adhesion between the Cu seed layer and the build-up film. In order to manufacture highly reliable fine Cu wiring, it is necessary to evaluate the controllability of good adhesion of the seed Cu layer / glass epoxy film interface. Fluorine compound gas is used for dry etching of build-up film. There are residues containing fluorine on the surface to be etched. These residual fluorine compounds reduce the adhesion between the build-up film and the seed layer for Cu
近年来，关于人工智能应用中GPU的功耗和延迟的讨论已经开始。为了进一步实现GPU在处理海量数据时的高速处理和低功耗，需要考虑GPU[1]的封装结构。目前的GPU封装结构是基于使用倒装芯片PoP (package on package)技术和Si中间层的封装基板。在这种应用的结构中，由于信号通过封装基板上的Si中间层传输的结构限制，导致布线距离增加，这是导致功耗和延迟增加的原因。因此，围绕硅中间层的封装结构已经得到了关注，并且已经提出了不使用硅中间层的预期结构。已经报道了一种直接形成精细布线层的方法，该方法通过在堆积衬底上使用光敏绝缘材料而不使用Si中间体来发挥RDL(再分布层)的作用。此外，鉴于信号频率的高频化趋势，具有低Df(介电损耗常数)和低Dk(介电常数)材料性能的玻璃环氧树脂材料作为沉积膜的开发正在进行中。利用低Df和低Dk的特性，利用半导体精细布线技术在构筑层上形成精细布线，有望成为一种更为有效的方法。针对未来高密度封装的发展，针对积层膜上多层布线的等离子体干蚀刻技术得到了发展。本文报道了用干法在堆积膜上制备细线的5 μm堆积厚度微加工的结果。该技术已发展成为实现未来异构集成的新型SiP (System in Package)技术之一。介绍了干法蚀刻和镀铜的工艺结果。为了适应芯片安装，在堆积层中形成的布线尺寸目标为线/空间= 2 μm / 2 μm。使用Si衬底代替模具面板的原因是它适合使用昂贵的NGD(已知的好模具)。在硅半导体封装中，迄今为止已经建立了非常稳定的300mm尺寸硅衬底对应的技术。此外，对于使用干法在堆积膜上形成铜细线，还需要确保Cu种子层与堆积膜之间有足够的附着力。为了制造高可靠性的细铜布线，有必要评估种子铜层/玻璃环氧膜界面良好附着力的可控性。氟化合物气用于干式蚀刻堆积膜。待蚀刻表面有含氟残留物。这些残留的氟化合物降低了镀铜的堆积膜和种子层之间的附着力。因此，有必要构建一种干燥工艺方法，通过消除残留氟化合物的影响来提高对种子层的附着力。将溅射过程前表面自由能的变化与Cu种子层剥离试验结果进行了比较。报道了构筑膜表面状况和种子膜附着力的基本研究结果。
{"title":"Surface-modification technology by using Radical Shower Treatment (RST) process in submicron interposer for Fan-out packaging applications.","authors":"T. Murayama, T. Sakuishi, Y. Morikawa","doi":"10.23919/ICEP.2019.8733523","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733523","url":null,"abstract":"In recent years, discussion on power consumption and latency of GPU used for AI application has started. In order to realize further high-speed processing and low power consumption of the GPU processing a huge amount of data, it is necessary to consider the packaging structure of the GPU [1]. The current GPU package structure is based on the package substrate using flip chip PoP (Package on Package) technology and Si interposer. In this structure applied, the wiring distance is increased due to the structural restriction of signal transmission through the Si interposer on the package substrate, which is the cause of the increase in power consumption and latency. Therefore, the packaging structure around the Si interposer has been focused, and expected structures that does not use the Si interposer have been proposed [2]. A method of directly forming fine wiring layers which plays a role of RDL (Redistributed Layer) by using a photosensitive insulation material on a build-up substrate without using a Si interposer has been reported [3]. Furthermore, in view of the high frequency trend of the signal frequency, the development of glass-epoxy materials having low Df (dielectric loss constant) and low Dk (dielectric constant) material properties as a build-up film is proceeding [4]. It is expected that it will be a more effective method to effectively utilize the characteristics of low Df and low Dk and to form fine wiring on the build-up layer using semiconductor fine wiring technology. For future high density packaging, plasma dry etching technology aiming fabrication of multilayer wiring on build-up film has been developed [5].In this paper, the results of microfabrication of build-up thickness of 5 μm are reported for the purpose of fabricating fine wiring on build-up film using dry process. This technology has been developed as one of new SiP (System in Package) technologies for realizing future heterogeneous integration. The process results of dry etching and Cu electroplating are described. In order to adapt to chip mounting, the size of the wiring formed in the build-up layer is targeted at line / space = 2 μm / 2 μm. The reason for using Si substrate instead of mold panel is because it is suitable for use of expensive NGD (known good die). In Si semiconductor packaging, very stable technology corresponding to Si substrate of 300 mm size has been established up to today. And, for Cu fine wiring formation on a build-up film using a dry process, it is also necessary to ensure sufficient adhesion between the Cu seed layer and the build-up film. In order to manufacture highly reliable fine Cu wiring, it is necessary to evaluate the controllability of good adhesion of the seed Cu layer / glass epoxy film interface. Fluorine compound gas is used for dry etching of build-up film. There are residues containing fluorine on the surface to be etched. These residual fluorine compounds reduce the adhesion between the build-up film and the seed layer for Cu","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129451243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733581
S. Saegusa, I. Sakurai, I. Okada, T. Fukuoka, S. Suzuki, Y. Utsumi, A. Yamaguchi
To achieve the three dimensional additive manufacturing process, we investigated X-ray radiolysis-induced chemical reaction of Cu(CH3COO)2 solution. Here, we demonstrated synthesis and immobilization of cupric oxide particles onto a silicon or aluminium substrate using X-ray radiolysis directly from a liquid solution. The X-ray radiolysis of Cu(CH3COO)2 solutions was observed to produce curious shaped microstructures consisting of cupric oxide (CuO, Cu2O, Cu4O3) particles and Cu particles. The sizes of the particles depended on the additive type of alcohol. The results indicate that there are several routes and reaction processes for these particles and aggregation to be synthesized. In addition, we demonstrated the synthesis of these particles using X-ray radiolysis cell combined with a solution flow system. The developed technique of X-ray radiolysis enables us to achieve the rapid and easy synthesis of higher-order structures consisting of cupric oxide and copper particles onto the desired area.
{"title":"X-ray radiolysis-based three dimensional additive manufacturing process","authors":"S. Saegusa, I. Sakurai, I. Okada, T. Fukuoka, S. Suzuki, Y. Utsumi, A. Yamaguchi","doi":"10.23919/ICEP.2019.8733581","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733581","url":null,"abstract":"To achieve the three dimensional additive manufacturing process, we investigated X-ray radiolysis-induced chemical reaction of Cu(CH3COO)2 solution. Here, we demonstrated synthesis and immobilization of cupric oxide particles onto a silicon or aluminium substrate using X-ray radiolysis directly from a liquid solution. The X-ray radiolysis of Cu(CH3COO)2 solutions was observed to produce curious shaped microstructures consisting of cupric oxide (CuO, Cu2O, Cu4O3) particles and Cu particles. The sizes of the particles depended on the additive type of alcohol. The results indicate that there are several routes and reaction processes for these particles and aggregation to be synthesized. In addition, we demonstrated the synthesis of these particles using X-ray radiolysis cell combined with a solution flow system. The developed technique of X-ray radiolysis enables us to achieve the rapid and easy synthesis of higher-order structures consisting of cupric oxide and copper particles onto the desired area.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131679842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733527
S. Nemoto, Takehiko Maeda, Masahiro Miyajima, Yasuhiko Akaike, K. Kitagawa, Hideki Ishii, H. Shimamoto, K. Kikuchi
Palladium (Pd) has played a big role to improve the corrosion resistance of copper (Cu) wire. To examine the corrosion resistance of Cu wire, the Cu/Al interface obtained by sputtering [1] was evaluated. In particular, the effect of Pd on Cu wire joints was investigated by preparing pseudo Palladium Coated Copper (PCC) samples and varying the Pd concentration. In this paper, pseudo PCC wire joint samples were evaluated for corrosion resistance and the results compared with those from actual Cu and PCC wire joint samples.
{"title":"Investigation of mechanism of corrosion resistance of Pd coated Cu wire joint by pseudo process","authors":"S. Nemoto, Takehiko Maeda, Masahiro Miyajima, Yasuhiko Akaike, K. Kitagawa, Hideki Ishii, H. Shimamoto, K. Kikuchi","doi":"10.23919/ICEP.2019.8733527","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733527","url":null,"abstract":"Palladium (Pd) has played a big role to improve the corrosion resistance of copper (Cu) wire. To examine the corrosion resistance of Cu wire, the Cu/Al interface obtained by sputtering [1] was evaluated. In particular, the effect of Pd on Cu wire joints was investigated by preparing pseudo Palladium Coated Copper (PCC) samples and varying the Pd concentration. In this paper, pseudo PCC wire joint samples were evaluated for corrosion resistance and the results compared with those from actual Cu and PCC wire joint samples.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134053600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733454
Po-Hsiang Chiu, Jenn-Ming Song
Hybrid pastes containing copper oxide particles with nano-(NPO) and submicron sizes (SMPO) were successfully developed for conductor fabrication through photonic sintering. Subjected to 3 or 4 flash pulses, copper particle pastes can be transformed into conductive sintered structure. A optimal SMPO:NPO ratio of 3:1 to obtain low electrical resistivity was suggested. The additions of copper formate can further reduce the resistivity down to 64.6±5.7μΩ•cm. FTIR spectra indicate that copper formate is easier to dissociate by flash irradiation compared to cupric sulfate and cupric chloride. One of the salt dissociation products, metallic copper, contributes to better electrical conductance
{"title":"Interconnect Fabrication using Copper Oxide Particles by Photonic-sintering","authors":"Po-Hsiang Chiu, Jenn-Ming Song","doi":"10.23919/ICEP.2019.8733454","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733454","url":null,"abstract":"Hybrid pastes containing copper oxide particles with nano-(NPO) and submicron sizes (SMPO) were successfully developed for conductor fabrication through photonic sintering. Subjected to 3 or 4 flash pulses, copper particle pastes can be transformed into conductive sintered structure. A optimal SMPO:NPO ratio of 3:1 to obtain low electrical resistivity was suggested. The additions of copper formate can further reduce the resistivity down to 64.6±5.7μΩ•cm. FTIR spectra indicate that copper formate is easier to dissociate by flash irradiation compared to cupric sulfate and cupric chloride. One of the salt dissociation products, metallic copper, contributes to better electrical conductance","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127796742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733497
T. Matsumae, Michitaka Yamamoto, Y. Kurashima, E. Higurashi, H. Takagi
A Cu-based heat spreader with smooth Au bonding film was fabricated by electroforming for room temperature bonding with electronic device in atmospheric air. The Cu substrates were electroformed using Au/Cu (bottom to top) and Au/Ta/Cu seed layers deposited onto smooth thermally-oxidized Si wafers; next, they were exfoliated at the Au/SiO2 interface. The exfoliated Au surface was bonded with the surface of Au-metallized Si chip at room temperature in atmospheric air by the surface activated bonding method. The Cu substrate electroformed using Au/Cu layer was poorly bonded because Cu atoms diffused through the Au film formed CuO on the surface. In the case of the Au/Ta/Cu seed layer, however, the Cu substrate was strongly bonded because the diffusion of Cu was blocked by the Ta barrier layer. It is expected that this technique will contribute to direct bonding between semiconductor device and heat spreader at room temperature without the use of vacuum bonding equipment.
{"title":"Room temperature bonding of smooth Au surface of electroformed Cu substrate in atmospheric air","authors":"T. Matsumae, Michitaka Yamamoto, Y. Kurashima, E. Higurashi, H. Takagi","doi":"10.23919/ICEP.2019.8733497","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733497","url":null,"abstract":"A Cu-based heat spreader with smooth Au bonding film was fabricated by electroforming for room temperature bonding with electronic device in atmospheric air. The Cu substrates were electroformed using Au/Cu (bottom to top) and Au/Ta/Cu seed layers deposited onto smooth thermally-oxidized Si wafers; next, they were exfoliated at the Au/SiO2 interface. The exfoliated Au surface was bonded with the surface of Au-metallized Si chip at room temperature in atmospheric air by the surface activated bonding method. The Cu substrate electroformed using Au/Cu layer was poorly bonded because Cu atoms diffused through the Au film formed CuO on the surface. In the case of the Au/Ta/Cu seed layer, however, the Cu substrate was strongly bonded because the diffusion of Cu was blocked by the Ta barrier layer. It is expected that this technique will contribute to direct bonding between semiconductor device and heat spreader at room temperature without the use of vacuum bonding equipment.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733417
Shiqi Zhou, Chih-han Yang, Yu-An Shen, S. Lin, H. Nishikawa
A new Sn-45Bi-2.6Zn (wt. %) alloy was developed to replacing eutectic Sn-58Bi alloy as a low-melting temperature solder alloy. A tensile elongation improvement was obtained by increasing the Sn to Bi volume ratio because the content of intrinsic brittle Bi was reduced. A solidus temperature of 133 Υ was achieved in a calculated Sn-Bi-Zn ternary system. The calculation of phase diagram (CALPHAD) method was used to help understand the melting behavior of Sn-45Bi-2.6Zn alloy. After aging, the elongation was still superior than that of eutectic Sn-58bi owing to the larger volume fraction of Sn phase.
{"title":"The study of Sn-45Bi-2.6Zn alloy before and after thermal aging","authors":"Shiqi Zhou, Chih-han Yang, Yu-An Shen, S. Lin, H. Nishikawa","doi":"10.23919/ICEP.2019.8733417","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733417","url":null,"abstract":"A new Sn-45Bi-2.6Zn (wt. %) alloy was developed to replacing eutectic Sn-58Bi alloy as a low-melting temperature solder alloy. A tensile elongation improvement was obtained by increasing the Sn to Bi volume ratio because the content of intrinsic brittle Bi was reduced. A solidus temperature of 133 Υ was achieved in a calculated Sn-Bi-Zn ternary system. The calculation of phase diagram (CALPHAD) method was used to help understand the melting behavior of Sn-45Bi-2.6Zn alloy. After aging, the elongation was still superior than that of eutectic Sn-58bi owing to the larger volume fraction of Sn phase.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129570134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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