Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282697
A. Bessemoulin, M. G. McCulloch, A. Alexander, D. Mccann, S. Mahon, J. Harvey
The performance of a compact K-band power amplifier MMIC fabricated in standard 6-inch 0.15-mum GaAs power PHEMT technology is reported. The circuit features on-chip ESD protection including input short-circuit stub, dual capacitors at RF ports and high-current diode arrays on each gate pad. Occupying less than 3 mm2, this 3-stage power amplifier achieves a linear gain of more than 20-dB over the 17 to 24 GHz frequency range with 6-dB noise figure. It also delivers a CW output power of more than 29-and 30-dBm, in the 17-20 GHz band, at 5- and 6-V respectively. Preliminary ESD characterization shows the circuit withstands 180-V in human body model test (tester limit), and 100-V machine model (equivalent to at least 500-V HBM), without DC or RF performance degradation. Finally, performance in standard 24-lead plastic QFN package (4times4 mm2) is presented: the device exhibits more than 17.5-dB linear gain over 17-24 GHz, with P-.1dB greater than 28-dBm in the 17.7-19.7 GHz radio range
报道了采用标准6英寸0.15 μ m GaAs功率PHEMT技术制作的紧凑型k波段功率放大器MMIC的性能。该电路具有片内ESD保护功能，包括输入短路存根、射频端口的双电容和每个门垫上的大电流二极管阵列。这款3级功率放大器占地面积小于3平方毫米，在17至24 GHz频率范围内实现了超过20 db的线性增益，噪声系数为6 db。它还在17-20 GHz频段分别以5- v和6-V提供超过29和30 dbm的连续波输出功率。初步的ESD特性表明，该电路在人体模型测试(测试仪极限)和100 v机器模型测试(至少相当于500 v HBM)中承受180 v，没有DC或RF性能下降。最后，介绍了标准24引脚塑料QFN封装(4times4 mm2)的性能:该器件在17-24 GHz范围内具有17.5 db以上的线性增益，P-。在17.7-19.7 GHz无线电范围内，比28dbm大1dB
{"title":"Compact K-band Watt-level GaAs PHEMT Power Amplifier MMIC with integrated ESD protection","authors":"A. Bessemoulin, M. G. McCulloch, A. Alexander, D. Mccann, S. Mahon, J. Harvey","doi":"10.1109/EMICC.2006.282697","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282697","url":null,"abstract":"The performance of a compact K-band power amplifier MMIC fabricated in standard 6-inch 0.15-mum GaAs power PHEMT technology is reported. The circuit features on-chip ESD protection including input short-circuit stub, dual capacitors at RF ports and high-current diode arrays on each gate pad. Occupying less than 3 mm2, this 3-stage power amplifier achieves a linear gain of more than 20-dB over the 17 to 24 GHz frequency range with 6-dB noise figure. It also delivers a CW output power of more than 29-and 30-dBm, in the 17-20 GHz band, at 5- and 6-V respectively. Preliminary ESD characterization shows the circuit withstands 180-V in human body model test (tester limit), and 100-V machine model (equivalent to at least 500-V HBM), without DC or RF performance degradation. Finally, performance in standard 24-lead plastic QFN package (4times4 mm2) is presented: the device exhibits more than 17.5-dB linear gain over 17-24 GHz, with P-.1dB greater than 28-dBm in the 17.7-19.7 GHz radio range","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117319597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282772
J. V. Siles, J. Grajal, V. Krozer
This work represents a further step to establish a physical numerical CAD tool for the design of Schottky-diode based MMIC circuits for millimetre-wave and terahertz applications. This software has shown very good capabilities for the design and optimization of Schottky multipliers and fundamental mixers with good agreement with measurements. The tool allows the concurrent optimization of the semiconductor device and the external circuit. The additional functionality presented in this paper consists of the design of subharmonically-pumped (SHP) GaAs Schottky diode mixers. Thus, a realistic prediction regarding LO power requirements, influence of parasitics, optimum input and output matching networks and mixer performance can be obtained prior to fabrication avoiding costly redesigns. A 400 GHz antiparallel-diode pair SHP mixer have been designed and optimized. State-of-the-art conversion losses are predicted for this SHP mixer
{"title":"Design of Subharmonically Pumped Schottky Mixers for Submillimetre-wave Applications","authors":"J. V. Siles, J. Grajal, V. Krozer","doi":"10.1109/EMICC.2006.282772","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282772","url":null,"abstract":"This work represents a further step to establish a physical numerical CAD tool for the design of Schottky-diode based MMIC circuits for millimetre-wave and terahertz applications. This software has shown very good capabilities for the design and optimization of Schottky multipliers and fundamental mixers with good agreement with measurements. The tool allows the concurrent optimization of the semiconductor device and the external circuit. The additional functionality presented in this paper consists of the design of subharmonically-pumped (SHP) GaAs Schottky diode mixers. Thus, a realistic prediction regarding LO power requirements, influence of parasitics, optimum input and output matching networks and mixer performance can be obtained prior to fabrication avoiding costly redesigns. A 400 GHz antiparallel-diode pair SHP mixer have been designed and optimized. State-of-the-art conversion losses are predicted for this SHP mixer","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132432101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282778
P. Upadhyaya, D. Heo, Y. Chen
A 2 GHz quadrature CMOS LC voltage controlled oscillator (VCO) has been designed in a standard 0.18-mum SiGe-BiCMOS process for direct conversion transceiver. Consuming total 8.5 mA of current from a 1.3 V power supply, the quadrature VCO achieves a measured single-sideband phase noise of -120 dBc/Hz at 1.0 MHz offset frequency. The VCO achieves -3 dBm of carrier power to a 50-ohm load and tuning range of 300 MHz to meet requirements for the WCDMA standard. Series-coupled technique for achieving quadrature phase lock with low phase error (< 0.6deg) and low phase noise is presented
{"title":"A 1.3V Low Phase Noise 2-GHz CMOS Quadrature LC VCO","authors":"P. Upadhyaya, D. Heo, Y. Chen","doi":"10.1109/EMICC.2006.282778","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282778","url":null,"abstract":"A 2 GHz quadrature CMOS LC voltage controlled oscillator (VCO) has been designed in a standard 0.18-mum SiGe-BiCMOS process for direct conversion transceiver. Consuming total 8.5 mA of current from a 1.3 V power supply, the quadrature VCO achieves a measured single-sideband phase noise of -120 dBc/Hz at 1.0 MHz offset frequency. The VCO achieves -3 dBm of carrier power to a 50-ohm load and tuning range of 300 MHz to meet requirements for the WCDMA standard. Series-coupled technique for achieving quadrature phase lock with low phase error (< 0.6deg) and low phase noise is presented","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133458986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282812
C. Wei, A. Metzger, Y. Zhu, C. Cismaru, A. Klimashov, P. Zampardi, R. Ramanrata, Y. Tkachenko
InGaP-GaAs based BIFET is a novel technology that integrates HBT and FET onto a single wafer. The technique expands functionality of circuits and reduces the cost. A novel four-terminal large-signal model was developed for accurate DC and RF applications. The device has a p-layer as backgate that has significant impact on the DC/RF characteristics and therefore, the drain current, gate current, leakage current and all charges/capacitances are 3-dimensional functions, which increases the complexity of the model. The model predicts very well IV/leakage curves for all configurations, including the cases when backgate is connected to source or to gate in that the device reduces to three-terminal. For the three terminal cases, the model also predicts RF performances. Statistic model is also presented to predict the variation of Idss/Vp as well as the corner models that define the extremes of characteristics in terms of epi-layer structure
{"title":"DC/RF and Statistic Modeling of Four Terminal InGap/GaAs Bifet for wireless application","authors":"C. Wei, A. Metzger, Y. Zhu, C. Cismaru, A. Klimashov, P. Zampardi, R. Ramanrata, Y. Tkachenko","doi":"10.1109/EMICC.2006.282812","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282812","url":null,"abstract":"InGaP-GaAs based BIFET is a novel technology that integrates HBT and FET onto a single wafer. The technique expands functionality of circuits and reduces the cost. A novel four-terminal large-signal model was developed for accurate DC and RF applications. The device has a p-layer as backgate that has significant impact on the DC/RF characteristics and therefore, the drain current, gate current, leakage current and all charges/capacitances are 3-dimensional functions, which increases the complexity of the model. The model predicts very well IV/leakage curves for all configurations, including the cases when backgate is connected to source or to gate in that the device reduces to three-terminal. For the three terminal cases, the model also predicts RF performances. Statistic model is also presented to predict the variation of Idss/Vp as well as the corner models that define the extremes of characteristics in terms of epi-layer structure","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282677
T. Martín-Guerrero, J. D. Baños-Polglase, C. Camacho-Peñalosa, M. Fernández-Barciela, D. G. Morgan, P. Tasker
A novel approach to extract the state functions of microwave FET-type quasi-static models from large-signal waveform measurements is described. The approach employs a one-port quasi-static nonlinear state functions frequency domain-based extraction method together with a procedure to transform, by proper loading at the control terminals, the two-port extraction problem into multiple one-port extraction problems. The main advantage of this approach is that it provides directly the charge-voltage state functions, without the need to perform the integration of the incremental capacitance-voltage characteristics as required by time domain-based approaches. The performance of the resulting approach is assessed by extracting the nonlinear state functions of a HEMT quasi-static model from large-signal microwave measurements
{"title":"Frequency domain-based approach for nonlinear quasi-static FET model extraction from large-signal waveform measurements","authors":"T. Martín-Guerrero, J. D. Baños-Polglase, C. Camacho-Peñalosa, M. Fernández-Barciela, D. G. Morgan, P. Tasker","doi":"10.1109/EMICC.2006.282677","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282677","url":null,"abstract":"A novel approach to extract the state functions of microwave FET-type quasi-static models from large-signal waveform measurements is described. The approach employs a one-port quasi-static nonlinear state functions frequency domain-based extraction method together with a procedure to transform, by proper loading at the control terminals, the two-port extraction problem into multiple one-port extraction problems. The main advantage of this approach is that it provides directly the charge-voltage state functions, without the need to perform the integration of the incremental capacitance-voltage characteristics as required by time domain-based approaches. The performance of the resulting approach is assessed by extracting the nonlinear state functions of a HEMT quasi-static model from large-signal microwave measurements","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282655
H. Tseng
Mixed-mode modeling is originally demonstrated for parameter extraction of advanced InGaAs HBTs in RFIC systems. This efficient approach combines the genetic algorithm (GA) with succinct analytical formulae to determine physically meaningful circuit elements used in the SPICE-like simulator. Evaluation of simulated and analytically-derived values validates the accuracy of this methodology
{"title":"Mixed-Mode Modeling and Parameter Extraction of Advanced InGaAs HBTs in RFIC Systems","authors":"H. Tseng","doi":"10.1109/EMICC.2006.282655","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282655","url":null,"abstract":"Mixed-mode modeling is originally demonstrated for parameter extraction of advanced InGaAs HBTs in RFIC systems. This efficient approach combines the genetic algorithm (GA) with succinct analytical formulae to determine physically meaningful circuit elements used in the SPICE-like simulator. Evaluation of simulated and analytically-derived values validates the accuracy of this methodology","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115214927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282680
Kwok-hung. Pao, C. Hsu, H. Chuang, C.‐L. Lu, C. Chen
A 3-10 GHz broadband CMOS T/R switch for ultra-wideband (UWB) transceiver is presented. The broadband CMOS T/R switch is fabricated based on the 0.18 mu 1P6M standard CMOS process. On-chip measurement of the CMOS T/R switch is performed. The insertion loss of the proposed CMOS T/R Switch is about 3.1plusmn1.3dB. The return losses at both input and output terminals are higher than 14 dB. It is also characterized with 25-34dB isolation and 18-20 dBm input P1dB. The broadband CMOS T/R switch shows highly linear phase and group delay of 20plusmn10 ps from 10MHz to 15GHz. It can be easily integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications
{"title":"A 3-10GHz Broadband CMOS T/R Switch for UWB Applications","authors":"Kwok-hung. Pao, C. Hsu, H. Chuang, C.‐L. Lu, C. Chen","doi":"10.1109/EMICC.2006.282680","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282680","url":null,"abstract":"A 3-10 GHz broadband CMOS T/R switch for ultra-wideband (UWB) transceiver is presented. The broadband CMOS T/R switch is fabricated based on the 0.18 mu 1P6M standard CMOS process. On-chip measurement of the CMOS T/R switch is performed. The insertion loss of the proposed CMOS T/R Switch is about 3.1plusmn1.3dB. The return losses at both input and output terminals are higher than 14 dB. It is also characterized with 25-34dB isolation and 18-20 dBm input P1dB. The broadband CMOS T/R switch shows highly linear phase and group delay of 20plusmn10 ps from 10MHz to 15GHz. It can be easily integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114676965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282661
F. Alimenti, M. Borgarino, R. Codeluppi, V. Palazzari, M. Pifferi, L. Roselli, A. Scorzoni, F. Fantini
This paper deals with the design of a 5GHz WLAN heterodyne transmitter for domotic applications. The transmitter has been realized in commercial 0.35μm Si/SiGe BiCMOS technology with the purpose to reduce cost while achieve an high integration level. Measurements on a prototype, wire-bonded on a low-cost FR4 printed circuit board, have been carried-out showing an overall linear gain of 14dB an input referred compression point of -6.5dBm and a third-order input intercept point of +2.7dBm
{"title":"A Single-Chip 5GHz WLAN Transmitter in 0.35μm Si/SiGe BiCMOS Technology","authors":"F. Alimenti, M. Borgarino, R. Codeluppi, V. Palazzari, M. Pifferi, L. Roselli, A. Scorzoni, F. Fantini","doi":"10.1109/EMICC.2006.282661","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282661","url":null,"abstract":"This paper deals with the design of a 5GHz WLAN heterodyne transmitter for domotic applications. The transmitter has been realized in commercial 0.35μm Si/SiGe BiCMOS technology with the purpose to reduce cost while achieve an high integration level. Measurements on a prototype, wire-bonded on a low-cost FR4 printed circuit board, have been carried-out showing an overall linear gain of 14dB an input referred compression point of -6.5dBm and a third-order input intercept point of +2.7dBm","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126073793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282816
W. Batty
Original recursive construction and series acceleration techniques are presented for an analytically exact solution of temperature response at any point in an arbitrary N-level, finite, rectangular multi-layer. This enhanced solution is fast and robust and provides accurate calculation of thermal resistance for packaged and mounted power FETs and MMICs. The model is validated against liquid crystal measurements. It forms the basis for quasi-analytical construction of the global thermal impedance matrix for complicated microwave systems by spectral, domain decomposition. Construction costs can be O(I), where I is the number of subvolume heating and interface elements. An original recursive convolution technique is presented producing transient simulation after pre-computation at O(N) cost, where N is the number of time steps. The method is illustrated by simulation of a mounted, packaged and metallised FET. This represents the most detailed quasi-analytical thermal simulation ever presented. This generalised network parameter description provides immediately boundary condition independent (BCI) compact dynamic thermal models for electrothermal CAD
{"title":"Analytical Solution in Complicated Volumes for Detailed Compact Thermal Model Construction","authors":"W. Batty","doi":"10.1109/EMICC.2006.282816","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282816","url":null,"abstract":"Original recursive construction and series acceleration techniques are presented for an analytically exact solution of temperature response at any point in an arbitrary N-level, finite, rectangular multi-layer. This enhanced solution is fast and robust and provides accurate calculation of thermal resistance for packaged and mounted power FETs and MMICs. The model is validated against liquid crystal measurements. It forms the basis for quasi-analytical construction of the global thermal impedance matrix for complicated microwave systems by spectral, domain decomposition. Construction costs can be O(I), where I is the number of subvolume heating and interface elements. An original recursive convolution technique is presented producing transient simulation after pre-computation at O(N) cost, where N is the number of time steps. The method is illustrated by simulation of a mounted, packaged and metallised FET. This represents the most detailed quasi-analytical thermal simulation ever presented. This generalised network parameter description provides immediately boundary condition independent (BCI) compact dynamic thermal models for electrothermal CAD","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116524046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/EMICC.2006.282813
B. G. Vasallo, N. Wichmann, S. Bollaert, A. Cappy, Tomas Gonzalez, D. Pardo, J. Mateos
The intrinsic static and dynamic performance of InAlAs/InGaAs double-gate high electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2D Monte Carlo simulator. Our model allows going deeply into the physical behavior of this novel device in comparison with similar standard HEMTs. Different gate lengths are analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. The intrinsic cut-off frequency fc of the DG-HEMTs is found to be similar to that of HEMTs, but the higher values of the figures of merit gm/gd and Cgs/C gd lead to an improvement of fmax
{"title":"Monte Carlo Comparison Between InP-Based Double-Gate and Standard HEMTs","authors":"B. G. Vasallo, N. Wichmann, S. Bollaert, A. Cappy, Tomas Gonzalez, D. Pardo, J. Mateos","doi":"10.1109/EMICC.2006.282813","DOIUrl":"https://doi.org/10.1109/EMICC.2006.282813","url":null,"abstract":"The intrinsic static and dynamic performance of InAlAs/InGaAs double-gate high electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2D Monte Carlo simulator. Our model allows going deeply into the physical behavior of this novel device in comparison with similar standard HEMTs. Different gate lengths are analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. The intrinsic cut-off frequency fc of the DG-HEMTs is found to be similar to that of HEMTs, but the higher values of the figures of merit gm/gd and Cgs/C gd lead to an improvement of fmax","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129547660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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