Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008313
Haiying Li, K. Jacob, C. Wong
Effective heat dissipation is crucial to enhance the performance and reliability of the electronic devices. In this paper, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with a mixed combination of fillers for optimizing key properties were also investigated. The thermal conductance and electrical conductance were investigated, and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The carbon fiber and silica filled composites showed an increase of thermal conductivity three to four times that of silica filled encapsulants of the same filler loading, while maintaining or enhancing major mechanical and thermal properties, respectively.
{"title":"Improvement of thermal conductivity of underfill materials for electronic packaging","authors":"Haiying Li, K. Jacob, C. Wong","doi":"10.1109/ECTC.2002.1008313","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008313","url":null,"abstract":"Effective heat dissipation is crucial to enhance the performance and reliability of the electronic devices. In this paper, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with a mixed combination of fillers for optimizing key properties were also investigated. The thermal conductance and electrical conductance were investigated, and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The carbon fiber and silica filled composites showed an increase of thermal conductivity three to four times that of silica filled encapsulants of the same filler loading, while maintaining or enhancing major mechanical and thermal properties, respectively.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116930385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008268
H. Balkan, D. Patterson, G. Burgess, C. Carlson, P. Elenius, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, J. Wood
The reliability of a ternary Sn/Ag/Cu alloy for flip chip solder joints will be reported in this paper. Dominant failure mechanisms for given thermal stress regimes are well defined for 63Sn/Pb eutectic solder. Characterizing Sn/Ag/Cu solder reliability in comparison to 63Sn/Pb solder provides a true baseline for these thermal stress regimes and still allows for a broad search of mechanisms due to the change in alloy properties inherent in this new metallurgic system. Reliability characterization must examine both solder bump and under bump metallization (UBM) robustness, because the interaction between the two contributes to the overall efficacy of the structure. Reported in this work are thermal cycle, high temperature storage, and die shear test results demonstrating the solder bump reliability. Electromigration, multiple reflow, and bare die high temperature test results verifying the UBM robustness are also presented. In addition, the assembly-related details are reported in an effort to provide a foundation for improved yield.
{"title":"Flip chip reliability: comparative characterization of lead free (Sn/Ag/Cu) and 63Sn/Pb eutectic solder","authors":"H. Balkan, D. Patterson, G. Burgess, C. Carlson, P. Elenius, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, J. Wood","doi":"10.1109/ECTC.2002.1008268","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008268","url":null,"abstract":"The reliability of a ternary Sn/Ag/Cu alloy for flip chip solder joints will be reported in this paper. Dominant failure mechanisms for given thermal stress regimes are well defined for 63Sn/Pb eutectic solder. Characterizing Sn/Ag/Cu solder reliability in comparison to 63Sn/Pb solder provides a true baseline for these thermal stress regimes and still allows for a broad search of mechanisms due to the change in alloy properties inherent in this new metallurgic system. Reliability characterization must examine both solder bump and under bump metallization (UBM) robustness, because the interaction between the two contributes to the overall efficacy of the structure. Reported in this work are thermal cycle, high temperature storage, and die shear test results demonstrating the solder bump reliability. Electromigration, multiple reflow, and bare die high temperature test results verifying the UBM robustness are also presented. In addition, the assembly-related details are reported in an effort to provide a foundation for improved yield.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117103282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008348
V. Varadarajan, B.C. Kim, Dae-Hyun Han
In this paper we present the effects of heat spreader on a ball grid array (BGA) package. We have simulated a fast switching CMOS inverter inside a BGA package with power, signal and ground planes. We performed simulations to study the effects of the electrical radiation and signal integrity with different configurations of heat spreader.
{"title":"Effects of floating heat spreader in high density BGA packages","authors":"V. Varadarajan, B.C. Kim, Dae-Hyun Han","doi":"10.1109/ECTC.2002.1008348","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008348","url":null,"abstract":"In this paper we present the effects of heat spreader on a ball grid array (BGA) package. We have simulated a fast switching CMOS inverter inside a BGA package with power, signal and ground planes. We performed simulations to study the effects of the electrical radiation and signal integrity with different configurations of heat spreader.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008277
J. Pitarresi, S. Chaparala, B. Sammakia, L. Nguyen, V. Patwardhan, L. Zhang, N. Kelkar
The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.
{"title":"A parametric solder joint reliability model for wafer level-chip scale package","authors":"J. Pitarresi, S. Chaparala, B. Sammakia, L. Nguyen, V. Patwardhan, L. Zhang, N. Kelkar","doi":"10.1109/ECTC.2002.1008277","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008277","url":null,"abstract":"The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008342
K. M. Ho, A. Rebelo, M. Caggiano, J. Gilbert
The Micro Lead Chip Carrier is a fine pitch package with low electrical parasitics due to its small size and consequently short conductive paths. This makes the package ideal for such RF applications as personal wireless communications. Several lead count packages were modeled using a rapid solution computer program developed at Rutgers University as well as a commercially available 3D solver program. Finally the same packages were measured using a Vector Network Analyzer. The results of the two sets of simulations and the measurements are compared and will be presented.
{"title":"Electrical modeling and measuring inductance in the Micro Lead Chip Carrier","authors":"K. M. Ho, A. Rebelo, M. Caggiano, J. Gilbert","doi":"10.1109/ECTC.2002.1008342","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008342","url":null,"abstract":"The Micro Lead Chip Carrier is a fine pitch package with low electrical parasitics due to its small size and consequently short conductive paths. This makes the package ideal for such RF applications as personal wireless communications. Several lead count packages were modeled using a rapid solution computer program developed at Rutgers University as well as a commercially available 3D solver program. Finally the same packages were measured using a Vector Network Analyzer. The results of the two sets of simulations and the measurements are compared and will be presented.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116188796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008088
S.K. Kang, W. K. Choi, D. Shih, P. Lauro, D. W. Henderson, T. Gosselin, D. Leonard
Sn-based alloys have been developed as Pb-free solder candidates to replace the Pb-containing solders used in microelectronic applications. However, their high Sn content and high melting point often cause excessive interfacial reactions, namely, dissolution of surface finish layers and concomitant formation of intermetallic compounds at the soldering interface. These interfacial reactions can therefore influence the microstructure and mechanical properties of the solder joints and eventually their reliability. The choice of a proper surface finish layer in printed circuit boards is an important issue in successfully introducing the Sn-based, Pb-free solders. The effects of surface finish layers and multiple reflows on the BGA solder joints have been investigated. A Pb-free solder alloy, Sn-Ag-Cu has been employed as the solder ball material. Five types of surface finish on opposite sides of the BGA balls, have been investigated. Intermetallic compound formation was measured as a function of reflow cycle. The effects of the interfacial reactions on the microstructure and mechanical properties of the solder joints were also investigated as a function of surface finish and reflow cycle.
{"title":"Interfacial reactions, microstructure and mechanical properties of Pb-free solder joints in PBGA laminates","authors":"S.K. Kang, W. K. Choi, D. Shih, P. Lauro, D. W. Henderson, T. Gosselin, D. Leonard","doi":"10.1109/ECTC.2002.1008088","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008088","url":null,"abstract":"Sn-based alloys have been developed as Pb-free solder candidates to replace the Pb-containing solders used in microelectronic applications. However, their high Sn content and high melting point often cause excessive interfacial reactions, namely, dissolution of surface finish layers and concomitant formation of intermetallic compounds at the soldering interface. These interfacial reactions can therefore influence the microstructure and mechanical properties of the solder joints and eventually their reliability. The choice of a proper surface finish layer in printed circuit boards is an important issue in successfully introducing the Sn-based, Pb-free solders. The effects of surface finish layers and multiple reflows on the BGA solder joints have been investigated. A Pb-free solder alloy, Sn-Ag-Cu has been employed as the solder ball material. Five types of surface finish on opposite sides of the BGA balls, have been investigated. Intermetallic compound formation was measured as a function of reflow cycle. The effects of the interfacial reactions on the microstructure and mechanical properties of the solder joints were also investigated as a function of surface finish and reflow cycle.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124394129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008214
Hurang Hua, S.K. Sitaramanb
A next-generation packaging concept, "System-On-Package (SOP)", is being developed at Georgia Tech. At the heart of the SOP is a fully integrated substrate with ultra high-density wiring, buried capacitor, inductor, resistor and optoelectronic layers on top of a base substrate. During fabrication as well as under working conditions, severe warpage and stresses could arise in the SOP substrate due to the temperature gradients and the CTE mismatch among its different constituent materials. For the SOP integrated substrate, five materials are being considered as the candidate material for the base substrate on which thin film layers will be sequentially processed. These candidate base substrate materials are glass-epoxy composites FR-4, Ceramic cloth/FR-4 resin (Ceramic/FR-4), Carbon cloth+Carbon filler/FR-4 resin (Carbon/FR-4), Carbon cloth/Cyanate easter resin (Carbon/Cyanate), and metal matrix composites AlSiC. In this study, the thermo-mechanical reliability of the SOP substrate with these five candidate base substrate materials is evaluated. The focus of the research is on the SOP substrate warpage and fatigue interlayer delamination propagation under thermal shock. It is found that the warpage is directly proportional to the thermal load. A comparison study of the substrate with and without a silicon flip-chip assembly is also conducted. The study shows that there will be no delamination propagation for the SOP substrate both with and without a flip-chip assembly, however, a potential fatigue crack growth exists for all the substrates under the thermal shock. A comparison study of the SOP substrate under the two thermal shocks of -550C to 1250C and of -450C to 1200C is also made. The analysis results in this work may be used in optimal design of the SOP substrate.
{"title":"Optimal design of an integrated substrate based on the analysis of warpage and delamination propagation","authors":"Hurang Hua, S.K. Sitaramanb","doi":"10.1109/ECTC.2002.1008214","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008214","url":null,"abstract":"A next-generation packaging concept, \"System-On-Package (SOP)\", is being developed at Georgia Tech. At the heart of the SOP is a fully integrated substrate with ultra high-density wiring, buried capacitor, inductor, resistor and optoelectronic layers on top of a base substrate. During fabrication as well as under working conditions, severe warpage and stresses could arise in the SOP substrate due to the temperature gradients and the CTE mismatch among its different constituent materials. For the SOP integrated substrate, five materials are being considered as the candidate material for the base substrate on which thin film layers will be sequentially processed. These candidate base substrate materials are glass-epoxy composites FR-4, Ceramic cloth/FR-4 resin (Ceramic/FR-4), Carbon cloth+Carbon filler/FR-4 resin (Carbon/FR-4), Carbon cloth/Cyanate easter resin (Carbon/Cyanate), and metal matrix composites AlSiC. In this study, the thermo-mechanical reliability of the SOP substrate with these five candidate base substrate materials is evaluated. The focus of the research is on the SOP substrate warpage and fatigue interlayer delamination propagation under thermal shock. It is found that the warpage is directly proportional to the thermal load. A comparison study of the substrate with and without a silicon flip-chip assembly is also conducted. The study shows that there will be no delamination propagation for the SOP substrate both with and without a flip-chip assembly, however, a potential fatigue crack growth exists for all the substrates under the thermal shock. A comparison study of the SOP substrate under the two thermal shocks of -550C to 1250C and of -450C to 1200C is also made. The analysis results in this work may be used in optimal design of the SOP substrate.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123738567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008299
R. Biedorf, R. Heinze, A. Wollanke, K. Wolter, T. Zerna, A. Plotzke
The usual assembly of CSP on printed circuit boards requires a relatively high volume of solder paste in a very small pitch. That's why a multiple step process is used with bumping of the interposer using pre-formed solder balls, with screen printing of solder paste on the substrate and with an reflow soldering step. In this paper three variants of bumping of CSP are discussed and some results of optimising the bumping and the assembly process of CSP are presented.
{"title":"Alternative bumping processes for DRAM-CSP","authors":"R. Biedorf, R. Heinze, A. Wollanke, K. Wolter, T. Zerna, A. Plotzke","doi":"10.1109/ECTC.2002.1008299","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008299","url":null,"abstract":"The usual assembly of CSP on printed circuit boards requires a relatively high volume of solder paste in a very small pitch. That's why a multiple step process is used with bumping of the interposer using pre-formed solder balls, with screen printing of solder paste on the substrate and with an reflow soldering step. In this paper three variants of bumping of CSP are discussed and some results of optimising the bumping and the assembly process of CSP are presented.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008139
Z. Illyefalvi-Vitéz, P. Németh, P. Bojta
In the course of the last few years, new component package types and high density interconnect (HDI) substrate technologies have emerged and presented new challenges to manufacturers. New package types include a great variety from flip chips (FCs), through quad flat packs (QFPs), to micro ball grid arrays (micro-BGAs) and chip scale packages (CSPs), while for substrates, laminated or build-up HDI technologies are preferred. In particular, laser via generation and patterning technology provided new possibilities in the field of the fabrication of laminate substrates for multichip modules (MCM-Ls). Since the application of a new technology always brings new degradation and failure mechanisms, reliability testing and failure analysis are necessary to maintain the quality of products and parts.
{"title":"Failure and acceleration models for MCM-Ls tested by HAST","authors":"Z. Illyefalvi-Vitéz, P. Németh, P. Bojta","doi":"10.1109/ECTC.2002.1008139","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008139","url":null,"abstract":"In the course of the last few years, new component package types and high density interconnect (HDI) substrate technologies have emerged and presented new challenges to manufacturers. New package types include a great variety from flip chips (FCs), through quad flat packs (QFPs), to micro ball grid arrays (micro-BGAs) and chip scale packages (CSPs), while for substrates, laminated or build-up HDI technologies are preferred. In particular, laser via generation and patterning technology provided new possibilities in the field of the fabrication of laminate substrates for multichip modules (MCM-Ls). Since the application of a new technology always brings new degradation and failure mechanisms, reliability testing and failure analysis are necessary to maintain the quality of products and parts.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121532770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008317
Yicai Sun, Guofeng Pan, Linlin Li, Pange Lui
A low temperature glass solder of the ternary system with a stoichiometric composition of PbO:ZnO:B/sub 2/O/sub 3/=58:18:24(wt%) has been developed for bonding silicon chip onto a glass substrate. When bonding at 510/spl deg/C, the quenched state from its molten (900/spl deg/C) was used. After bonding, it turned into a crystalline state, whose thermal behaviour was obviously different from the quenched state. In order to illuminate the relationship between properties and behaviours, DSC infrared absorption spectroscopy and X-ray diffraction were carried out for two powders of the quenched and recondensed states. It can be confirmed that for the quenched one, the softening point (450/spl deg/C) was lower and it was melted thoroughly at 500/spl sim/510/spl deg/C for chip-bonding, and there was no X-ray diffraction peak, which is a typical spectrum for the glass phase. However, for the recondensed glass, the melting point was raised to 631/spl sim/644/spl deg/C. There were the same X-ray diffraction peaks as the standard spectrum of Pb/sub 2/ZnB/sub 2/O/sub 6/. These results indicate that the recondensed glass solder possess a crystalline structure to benefit the usage for devices at higher temperature.
{"title":"Property revealing for silicon chip-bonding glass","authors":"Yicai Sun, Guofeng Pan, Linlin Li, Pange Lui","doi":"10.1109/ECTC.2002.1008317","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008317","url":null,"abstract":"A low temperature glass solder of the ternary system with a stoichiometric composition of PbO:ZnO:B/sub 2/O/sub 3/=58:18:24(wt%) has been developed for bonding silicon chip onto a glass substrate. When bonding at 510/spl deg/C, the quenched state from its molten (900/spl deg/C) was used. After bonding, it turned into a crystalline state, whose thermal behaviour was obviously different from the quenched state. In order to illuminate the relationship between properties and behaviours, DSC infrared absorption spectroscopy and X-ray diffraction were carried out for two powders of the quenched and recondensed states. It can be confirmed that for the quenched one, the softening point (450/spl deg/C) was lower and it was melted thoroughly at 500/spl sim/510/spl deg/C for chip-bonding, and there was no X-ray diffraction peak, which is a typical spectrum for the glass phase. However, for the recondensed glass, the melting point was raised to 631/spl sim/644/spl deg/C. There were the same X-ray diffraction peaks as the standard spectrum of Pb/sub 2/ZnB/sub 2/O/sub 6/. These results indicate that the recondensed glass solder possess a crystalline structure to benefit the usage for devices at higher temperature.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131546168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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