Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307419
E. Minami, K. Quader, P. Ko, C. Hu
We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<>
{"title":"Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation","authors":"E. Minami, K. Quader, P. Ko, C. Hu","doi":"10.1109/IEDM.1992.307419","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307419","url":null,"abstract":"We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307499
K. Okabe, T. Ikezawa, I. Sakai, M. Fukuma
A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effective for suppressing drain induced barrier lowering (DIBL) of buried channel pMOSFETs, without any degradation in Vt controllability. Simulation results suggest the potential profile engineering is useful for designing 0.25 mu m buried channel pMOSFETs with high driving capability and good Vt controllability.<>
{"title":"Potential profile engineering for quarter micron buried channel pMOSFETs with n regions in the channel","authors":"K. Okabe, T. Ikezawa, I. Sakai, M. Fukuma","doi":"10.1109/IEDM.1992.307499","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307499","url":null,"abstract":"A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effective for suppressing drain induced barrier lowering (DIBL) of buried channel pMOSFETs, without any degradation in Vt controllability. Simulation results suggest the potential profile engineering is useful for designing 0.25 mu m buried channel pMOSFETs with high driving capability and good Vt controllability.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121770818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307386
F. Sato, T. Hashimoto, T. Tatsumi, H. Kitahata, T. Tashiro
This paper describes a high fmax self-aligned SiGe heterojunction bipolar transistor (HBT) technology which is based on the self-aligned selective epitaxial growth technology including Ge graded profile and link-base engineering using a BSG sidewall structure. The HBT has a Super Self-aligned Selectively grown SiGe Base (SSSB) structure. Base profile design and a 2-step annealing technique have realized a f/sub T/ of 51 GHz and low sheet resistance at the link-base region, and furthermore have accomplished fmax of as high as 50 GHz. ECL circuits of 19 psec gate delay have been achieved by using this SiGe HBT technology.<>
{"title":"Sub-20 psec ECL circuits with 50 GHz fmax self-aligned SiGe HBTs","authors":"F. Sato, T. Hashimoto, T. Tatsumi, H. Kitahata, T. Tashiro","doi":"10.1109/IEDM.1992.307386","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307386","url":null,"abstract":"This paper describes a high fmax self-aligned SiGe heterojunction bipolar transistor (HBT) technology which is based on the self-aligned selective epitaxial growth technology including Ge graded profile and link-base engineering using a BSG sidewall structure. The HBT has a Super Self-aligned Selectively grown SiGe Base (SSSB) structure. Base profile design and a 2-step annealing technique have realized a f/sub T/ of 51 GHz and low sheet resistance at the link-base region, and furthermore have accomplished fmax of as high as 50 GHz. ECL circuits of 19 psec gate delay have been achieved by using this SiGe HBT technology.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132230086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307329
H. Wann, P. Ko, C. Hu
Theoretical and experimental studies are presented to model the gate-induced drain leakage(GIDL) current due to band-to-band tunneling, which is one of the major leakage components in off-state MOSFETs. The model shows a good agreement with the experimental data for more than 7 decades of current magnitudes. Therefore the impact of this tunneling leakage current can be correctly evaluated. Based on this model, the impact of GIDL on low off-state leakage drain engineering and on oxide scaling is investigated.<>
{"title":"Gate-induced band-to-band tunneling leakage current in LDD MOSFETs","authors":"H. Wann, P. Ko, C. Hu","doi":"10.1109/IEDM.1992.307329","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307329","url":null,"abstract":"Theoretical and experimental studies are presented to model the gate-induced drain leakage(GIDL) current due to band-to-band tunneling, which is one of the major leakage components in off-state MOSFETs. The model shows a good agreement with the experimental data for more than 7 decades of current magnitudes. Therefore the impact of this tunneling leakage current can be correctly evaluated. Based on this model, the impact of GIDL on low off-state leakage drain engineering and on oxide scaling is investigated.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132293613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307495
I. Kidoguchi, S. Kamiyama, M. Mannoh, J. Hoshina, H. Ohta, A. Ishibashi, Y. Ban, K. Ohnaka
AlGaInP visible laser diode with lateral leaky waveguide structure has been demonstrated for the first time. The laser has differential quantum efficiency as high as 43% from one facet in addition to fundamental-transverse-mode stability without facet coating. The high differential quantum efficiency is due to the low propagation loss of this laser.<>
{"title":"AlGaInP visible laser diode with extremely high quantum efficiency having lateral leaky waveguide structure","authors":"I. Kidoguchi, S. Kamiyama, M. Mannoh, J. Hoshina, H. Ohta, A. Ishibashi, Y. Ban, K. Ohnaka","doi":"10.1109/IEDM.1992.307495","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307495","url":null,"abstract":"AlGaInP visible laser diode with lateral leaky waveguide structure has been demonstrated for the first time. The laser has differential quantum efficiency as high as 43% from one facet in addition to fundamental-transverse-mode stability without facet coating. The high differential quantum efficiency is due to the low propagation loss of this laser.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134443118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307491
C. Mazure, J. Fitch, C. Gunderson
A novel facet-engineered elevated source/drain formation design is presented. It is found that the ex situ clean prior to selective Si epitaxial growth (SEG) determines the resulting facets on the SEG-source/drain. We show that low angle facets are very advantageous for minimizing parasitic Miller capacitances, while simultaneously grading the source/drain junction near the gate edge and retrieving the source/drain junction from the substrate elsewhere, thus reducing the junction capacitance. Further, we show that both a strong current drive (I/sub DS/) increase and a reduction in parasitic junction capacitance can be realized with facet-engineered phosphorus doped SEG-source/drain with no detrimental effects to short channel device behavior.<>
{"title":"Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETS","authors":"C. Mazure, J. Fitch, C. Gunderson","doi":"10.1109/IEDM.1992.307491","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307491","url":null,"abstract":"A novel facet-engineered elevated source/drain formation design is presented. It is found that the ex situ clean prior to selective Si epitaxial growth (SEG) determines the resulting facets on the SEG-source/drain. We show that low angle facets are very advantageous for minimizing parasitic Miller capacitances, while simultaneously grading the source/drain junction near the gate edge and retrieving the source/drain junction from the substrate elsewhere, thus reducing the junction capacitance. Further, we show that both a strong current drive (I/sub DS/) increase and a reduction in parasitic junction capacitance can be realized with facet-engineered phosphorus doped SEG-source/drain with no detrimental effects to short channel device behavior.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130307334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307304
T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Odaka, M. Usami, T. Ikeda
A double polysilicon bipolar technology with high-speed, high-packing density, low power consumption, and high alpha -particle immunity has been newly developed. Bonded SOI substrates are used to improve the alpha -particle immunity, and scaled CMOS memory cells are introduced to reduce the power consumption and to increase the packing density. The cut-off frequency of the bipolar transistors is as high as 27 GHz and the area of the CMOS memory cell is 58 mu m/sup 2/. This technology is promising for application to ultra high-speed, high-density LSIs with ECL-CMOS scheme.<>
{"title":"A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications","authors":"T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Odaka, M. Usami, T. Ikeda","doi":"10.1109/IEDM.1992.307304","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307304","url":null,"abstract":"A double polysilicon bipolar technology with high-speed, high-packing density, low power consumption, and high alpha -particle immunity has been newly developed. Bonded SOI substrates are used to improve the alpha -particle immunity, and scaled CMOS memory cells are introduced to reduce the power consumption and to increase the packing density. The cut-off frequency of the bipolar transistors is as high as 27 GHz and the area of the CMOS memory cell is 58 mu m/sup 2/. This technology is promising for application to ultra high-speed, high-density LSIs with ECL-CMOS scheme.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131558028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307533
H. Kurino, H. Hashimoto, Y. Hiruma, T. Fujimori, M. Koyanagi
The photon emission from extremely small size MOSFETs with L/sub G/=70 nm is observed for the first time. It is found that the electron temperature of the hot electrons monotonously increases while the substrate current to drain current ratio which is related to the avalanche multiplication factor initially increases and then decreases due to the latch effect caused by the parasitic bipolar transistor action as the gate length is reduced from 500 nm to 70 nm. The number of photons emitted with a higher energy has more intimate relation with the charge pumping current change caused by the hot-carrier generated interface states. It is shown that the photon emission is more effective for evaluating the hot carrier phenomenon than the substrate current when the gate length is smaller and the drain voltage is higher.<>
{"title":"Photon emission from 70 nm gate length MOSFETs","authors":"H. Kurino, H. Hashimoto, Y. Hiruma, T. Fujimori, M. Koyanagi","doi":"10.1109/IEDM.1992.307533","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307533","url":null,"abstract":"The photon emission from extremely small size MOSFETs with L/sub G/=70 nm is observed for the first time. It is found that the electron temperature of the hot electrons monotonously increases while the substrate current to drain current ratio which is related to the avalanche multiplication factor initially increases and then decreases due to the latch effect caused by the parasitic bipolar transistor action as the gate length is reduced from 500 nm to 70 nm. The number of photons emitted with a higher energy has more intimate relation with the charge pumping current change caused by the hot-carrier generated interface states. It is shown that the photon emission is more effective for evaluating the hot carrier phenomenon than the substrate current when the gate length is smaller and the drain voltage is higher.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132573909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307319
K. Orihara, K. Minami, T. Nakano, K. Hatano, M. Furumiya, N. Mutoh, M. Ohbo, Y. Hokari
New shunt wiring technologies for HDTV FIT-CCD image sensors have been developed. They include tungsten direct shunt wiring structure. As well as a new layout for tungsten shunt lines and aluminum bus lines. A 1-inch format 2M pixel FIT-CCD image sensor was fabricated using these technologies. A low smear level, less than -110 dB, was achieved at 1 MHz frame shift frequency. Furthermore, a 1.2*10/sup 5/ electron charge handling capability was obtained up to 1.4 MHz frame shift frequency.<>
{"title":"New shunt wiring technologies for high performance HDTV CCD image sensors","authors":"K. Orihara, K. Minami, T. Nakano, K. Hatano, M. Furumiya, N. Mutoh, M. Ohbo, Y. Hokari","doi":"10.1109/IEDM.1992.307319","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307319","url":null,"abstract":"New shunt wiring technologies for HDTV FIT-CCD image sensors have been developed. They include tungsten direct shunt wiring structure. As well as a new layout for tungsten shunt lines and aluminum bus lines. A 1-inch format 2M pixel FIT-CCD image sensor was fabricated using these technologies. A low smear level, less than -110 dB, was achieved at 1 MHz frame shift frequency. Furthermore, a 1.2*10/sup 5/ electron charge handling capability was obtained up to 1.4 MHz frame shift frequency.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307347
J. Weyers, H. Vogt
A new process has been developed which provides dielectrically isolated power and low voltage devices by means of rather standard VLSI CMOS technology. Isolation is obtained by SIMOX and trenches. For Smart Power applications this process allows the manufacturing of 50 V vertical DMOS transistors (VDMOS) together with 50 V dielectrically isolated quasivertical DMOS transistors (QVDMOS). For control circuit design CMOS, high voltage PMOS transistors (HVPMOS), NPN transistors, JFETs, Zener and Schottky diodes are available on the same chip. Thus, the designer has at hand a wide range of devices which allows an optimum solution for many circuit applications.<>
{"title":"A 50 V smart power process with dielectric isolation by SIMOX","authors":"J. Weyers, H. Vogt","doi":"10.1109/IEDM.1992.307347","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307347","url":null,"abstract":"A new process has been developed which provides dielectrically isolated power and low voltage devices by means of rather standard VLSI CMOS technology. Isolation is obtained by SIMOX and trenches. For Smart Power applications this process allows the manufacturing of 50 V vertical DMOS transistors (VDMOS) together with 50 V dielectrically isolated quasivertical DMOS transistors (QVDMOS). For control circuit design CMOS, high voltage PMOS transistors (HVPMOS), NPN transistors, JFETs, Zener and Schottky diodes are available on the same chip. Thus, the designer has at hand a wide range of devices which allows an optimum solution for many circuit applications.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115373910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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