Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307309
S. Fang, S. Murakawa, J. Mcvittie
Plasma nonuniformity can lead to surface charging and damaging currents through thin oxides. In poly-Si etching, surface currents across the wafer prevent damage until just before endpoint when current collected in halo regions around the mask can lead to gate charging and excessive tunneling current through the oxide. During overetching, additional damage is minimal because of the small collection area. This model is supported by plasma measurements, SPICE simulations, and etching damage results.<>
{"title":"A new model for thin oxide degradation from wafer charging in plasma etching","authors":"S. Fang, S. Murakawa, J. Mcvittie","doi":"10.1109/IEDM.1992.307309","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307309","url":null,"abstract":"Plasma nonuniformity can lead to surface charging and damaging currents through thin oxides. In poly-Si etching, surface currents across the wafer prevent damage until just before endpoint when current collected in halo regions around the mask can lead to gate charging and excessive tunneling current through the oxide. During overetching, additional damage is minimal because of the small collection area. This model is supported by plasma measurements, SPICE simulations, and etching damage results.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121583363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307532
K. F. Lee, R. Yan, D. Jeon, Y. Kim, D. Tennant, E. Westerwick, K. Early, G. Chin, M. Morris, R. Johnson, T. M. Liu, R. Kistler, A. Voshchenkov, R. Swartz, A. Ourmazd
We report a record 51 GHz f/sub T/ for 0.1 mu m gate length pMOSFETs. Maximum transconductance observed was 330 mS/mm, subthreshold slope was 87 mV/decade. We have also obtained gate sheet resistance of 4-5 Omega / Square Operator at 0.1 mu m gate length using platinum silicide. To reduce the overlap capacitance due to a relatively deep junction, a two-step sidewall process was implemented.<>
{"title":"0.1 mu m p-channel MOSFETs with 51 GHz f/sub T/","authors":"K. F. Lee, R. Yan, D. Jeon, Y. Kim, D. Tennant, E. Westerwick, K. Early, G. Chin, M. Morris, R. Johnson, T. M. Liu, R. Kistler, A. Voshchenkov, R. Swartz, A. Ourmazd","doi":"10.1109/IEDM.1992.307532","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307532","url":null,"abstract":"We report a record 51 GHz f/sub T/ for 0.1 mu m gate length pMOSFETs. Maximum transconductance observed was 330 mS/mm, subthreshold slope was 87 mV/decade. We have also obtained gate sheet resistance of 4-5 Omega / Square Operator at 0.1 mu m gate length using platinum silicide. To reduce the overlap capacitance due to a relatively deep junction, a two-step sidewall process was implemented.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126265184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307590
P. Francis, A. Terao, B. Gentinne, D. Flandre, J. Colinge
This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300 degrees C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers.<>
{"title":"SOI technology for high-temperature applications","authors":"P. Francis, A. Terao, B. Gentinne, D. Flandre, J. Colinge","doi":"10.1109/IEDM.1992.307590","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307590","url":null,"abstract":"This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300 degrees C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127937854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307353
J.S.T. Huang
A new AC symmetric power device structure, called the bilateral emitter switched thyristor (BEST) is described. The use of concentric geometries for unit cells results in a compact and area efficient design. The symmetry of the device provides an additional MOS gate to facilitate turn-offs and to extend the controllable current range. The measured turn-off time is less than one microsecond.<>
{"title":"The bilateral emitter switched thyristor (BEST)","authors":"J.S.T. Huang","doi":"10.1109/IEDM.1992.307353","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307353","url":null,"abstract":"A new AC symmetric power device structure, called the bilateral emitter switched thyristor (BEST) is described. The use of concentric geometries for unit cells results in a compact and area efficient design. The symmetry of the device provides an additional MOS gate to facilitate turn-offs and to extend the controllable current range. The measured turn-off time is less than one microsecond.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131983472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307498
J. Pfiester, M. Woo, J. Fitch, J. Schmidt
A new Reverse Elevated Source/Drain (RESD) CMOS process has been developed as part of a deep submicron CMOS technology featuring ultra-shallow source/drain junctions with reversed (with respect to epi formation) phosphorus LDD implantation. This new structure utilizes disposable nitride spacers to define the selective silicon offset from the gate edge prior to LDD implantation. Since the LDD junctions are not exposed to the high temperature prebake and deposition conditions, shallow phosphorus junctions provide improved short-channel behavior while maintaining good hot-carrier protection.<>
{"title":"Reverse Elevated Source/Drain (RESD) MOSFET for deep submicron CMOS","authors":"J. Pfiester, M. Woo, J. Fitch, J. Schmidt","doi":"10.1109/IEDM.1992.307498","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307498","url":null,"abstract":"A new Reverse Elevated Source/Drain (RESD) CMOS process has been developed as part of a deep submicron CMOS technology featuring ultra-shallow source/drain junctions with reversed (with respect to epi formation) phosphorus LDD implantation. This new structure utilizes disposable nitride spacers to define the selective silicon offset from the gate edge prior to LDD implantation. Since the LDD junctions are not exposed to the high temperature prebake and deposition conditions, shallow phosphorus junctions provide improved short-channel behavior while maintaining good hot-carrier protection.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132132733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307392
R. Montgomery, A. Feygenson, P. Smith, R. D. Yadvish, R. Hamm, H. Temkin
We have built a broadband bipolar transimpedance preamplifier exhibiting an effective transimpedance gain of 39 dB Omega with 1.5 dB/sub p-p/ ripple. Using InP/InGaAs composite collector heterojunction bipolar transistors (HBTs) with an f/sub T/ of 120 GHz and f/sub max/ equal to 59 GHz, a 28 GHz circuit bandwidth was demonstrated. The circuit is compact measuring 975*675 mu m/sup 2/. A low power dissipation of only 48.6 mW was achieved for a single supply voltage of 2.7 V.<>
{"title":"A 28 GHz transimpedance preamplifier with inductive bandwidth enhancement","authors":"R. Montgomery, A. Feygenson, P. Smith, R. D. Yadvish, R. Hamm, H. Temkin","doi":"10.1109/IEDM.1992.307392","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307392","url":null,"abstract":"We have built a broadband bipolar transimpedance preamplifier exhibiting an effective transimpedance gain of 39 dB Omega with 1.5 dB/sub p-p/ ripple. Using InP/InGaAs composite collector heterojunction bipolar transistors (HBTs) with an f/sub T/ of 120 GHz and f/sub max/ equal to 59 GHz, a 28 GHz circuit bandwidth was demonstrated. The circuit is compact measuring 975*675 mu m/sup 2/. A low power dissipation of only 48.6 mW was achieved for a single supply voltage of 2.7 V.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130395262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307412
M. Beiley, S. Wong
A membrane probe card designed for high speed, high pin count testing has been fabricated with conventional IC technology on a silicon wafer and its functionality demonstrated. A novel method of breaking down interfacial oxide, as a replacement for mechanical scrubbing, is proposed and demonstrated. The probe card can consistently provide contact resistance of <2 Omega , has greatly reduced parasitics, is capable of elevated temperature testing, and offers controlled impedance striplines of 50 Omega to the probe tips.<>
{"title":"Micro-machined array probe card","authors":"M. Beiley, S. Wong","doi":"10.1109/IEDM.1992.307412","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307412","url":null,"abstract":"A membrane probe card designed for high speed, high pin count testing has been fabricated with conventional IC technology on a silicon wafer and its functionality demonstrated. A novel method of breaking down interfacial oxide, as a replacement for mechanical scrubbing, is proposed and demonstrated. The probe card can consistently provide contact resistance of <2 Omega , has greatly reduced parasitics, is capable of elevated temperature testing, and offers controlled impedance striplines of 50 Omega to the probe tips.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128877558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307310
Y. Lee, L. Yau, R. Chau, E. Hansen, B. Sabi, S. Hui, P. Moon, G. Vandentop
We simulated plasma etch induced gate charging by using a Fowler-Nordheim (F-N) stress, and compared the resulting degradation with end-of-line (EOL) antenna transistors in a triple-layer metal CMOS technology. Our studies show good agreement between the effects of F-N current stress and plasma processing induced device deterioration very well. This is also the first known work to explain the effects of in-process plasma charging on p-channel hot-electron reliability.<>
{"title":"Correlation of plasma process induced charging with Fowler-Nordheim stress in p- and n-channel transistors","authors":"Y. Lee, L. Yau, R. Chau, E. Hansen, B. Sabi, S. Hui, P. Moon, G. Vandentop","doi":"10.1109/IEDM.1992.307310","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307310","url":null,"abstract":"We simulated plasma etch induced gate charging by using a Fowler-Nordheim (F-N) stress, and compared the resulting degradation with end-of-line (EOL) antenna transistors in a triple-layer metal CMOS technology. Our studies show good agreement between the effects of F-N current stress and plasma processing induced device deterioration very well. This is also the first known work to explain the effects of in-process plasma charging on p-channel hot-electron reliability.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307425
T. Usuki, M. Takatsu, M. Saito, M. Okada, N. Yokoyama
We developed a simulator for mesoscopic electron wave devices using algorithm for solving the two dimensional (2D) Schrodinger equation. The algorithm has the following features: applicability to any potential structure, accuracy of solution, and simplicity of treatment even under magnetic fields. We describe the calculation methods and analysis of mesoscopic phenomena using our simulation. We also demonstrate its feasibility by comparing numerical results with our recent experimental results.<>
{"title":"New algorithm simulation for mesoscopic electron wave devices employing high mobility 2D electron gas","authors":"T. Usuki, M. Takatsu, M. Saito, M. Okada, N. Yokoyama","doi":"10.1109/IEDM.1992.307425","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307425","url":null,"abstract":"We developed a simulator for mesoscopic electron wave devices using algorithm for solving the two dimensional (2D) Schrodinger equation. The algorithm has the following features: applicability to any potential structure, accuracy of solution, and simplicity of treatment even under magnetic fields. We describe the calculation methods and analysis of mesoscopic phenomena using our simulation. We also demonstrate its feasibility by comparing numerical results with our recent experimental results.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114682748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307323
T. Temofonte, T. Braggins, P. Emtage, M. Bevan, R. Thomas, H. Nathanson, J. Halvis, R. Shiskowski, T. Wilson, D. Mccann
An all-silicon LWIR staring focal plane technology is described which has the potential of exceptionally high uniformity and resolution, 77K operation, and a demonstrated electronic tunability of the cut-off wavelength. p/sup +/np homojunction internal barrier detectors have quantum efficiencies of over 5% from 4.5 to 9.5 mu m and 0.2% at 12 mu m, exceeding the performance of all other internal photoemission detectors. Imagery (using a 8-11.5 mu m passband filter) with 128*128 p/sup +/np detector arrays bonded to silicon p-channel CMOS multiplexers was successfully demonstrated.<>
{"title":"All-silicon internal barrier detectors: a voltage-tunable LWIR staring focal plane technology","authors":"T. Temofonte, T. Braggins, P. Emtage, M. Bevan, R. Thomas, H. Nathanson, J. Halvis, R. Shiskowski, T. Wilson, D. Mccann","doi":"10.1109/IEDM.1992.307323","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307323","url":null,"abstract":"An all-silicon LWIR staring focal plane technology is described which has the potential of exceptionally high uniformity and resolution, 77K operation, and a demonstrated electronic tunability of the cut-off wavelength. p/sup +/np homojunction internal barrier detectors have quantum efficiencies of over 5% from 4.5 to 9.5 mu m and 0.2% at 12 mu m, exceeding the performance of all other internal photoemission detectors. Imagery (using a 8-11.5 mu m passband filter) with 128*128 p/sup +/np detector arrays bonded to silicon p-channel CMOS multiplexers was successfully demonstrated.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114894888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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