Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307452
M. Okamura, K. Kimura, S. Shirai, N. Yamauchi
We have designed, fabricated, and characterized a 32*32 two-dimensional photodetector array using amorphous silicon (a-Si) pin photodiodes and polysilicon (poly-Si) TFTs integrated on a transparent substrate. This work demonstrates the feasibility of a light-transmitting two-dimensional photodetector array for use in parallel optoelectronic systems such as free-space photonic switching systems.<>
{"title":"A 32*32 two-dimensional photodetector array using a-Si pin photodiodes and poly-Si TFTs integrated on a transparent substrate","authors":"M. Okamura, K. Kimura, S. Shirai, N. Yamauchi","doi":"10.1109/IEDM.1992.307452","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307452","url":null,"abstract":"We have designed, fabricated, and characterized a 32*32 two-dimensional photodetector array using amorphous silicon (a-Si) pin photodiodes and polysilicon (poly-Si) TFTs integrated on a transparent substrate. This work demonstrates the feasibility of a light-transmitting two-dimensional photodetector array for use in parallel optoelectronic systems such as free-space photonic switching systems.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307519
R. Moazzami, P. Maniar, R. Jones, A. C. Campbell, C. Mogab
This paper describes an investigation of thickness scaling of sol gel-derived ferroelectric lead zirconate titanate (PZT) thin films that demonstrates the highest charge storage capacity (220 fC/ mu m/sup 2/ for a 1.5 V voltage swing) ever reported, low leakage current density (<10-7 A/cm/sup 2/ at 0.75 V for V/sub DD//2 operation), and good dielectric integrity. V/sub DD//2 operation is also shown to be viable with these ferroelectric films since no fatigue is observed after 10/sup 11/ polarization reversals. These PZT films hold promise as an alternative to the conventional trench and stacked capacitor cell technologies employing SiO/sub 2//Si/sub 3/N/sub 4/ dielectrics which demand extremely severe geometries and exceedingly complex processes to meet the charge storage specifications of gigabit-scale DRAM's.<>
{"title":"Ultra-high charge storage capacity ferroelectric lead zirconate titanate thin films for gigabit-scale DRAM's","authors":"R. Moazzami, P. Maniar, R. Jones, A. C. Campbell, C. Mogab","doi":"10.1109/IEDM.1992.307519","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307519","url":null,"abstract":"This paper describes an investigation of thickness scaling of sol gel-derived ferroelectric lead zirconate titanate (PZT) thin films that demonstrates the highest charge storage capacity (220 fC/ mu m/sup 2/ for a 1.5 V voltage swing) ever reported, low leakage current density (<10-7 A/cm/sup 2/ at 0.75 V for V/sub DD//2 operation), and good dielectric integrity. V/sub DD//2 operation is also shown to be viable with these ferroelectric films since no fatigue is observed after 10/sup 11/ polarization reversals. These PZT films hold promise as an alternative to the conventional trench and stacked capacitor cell technologies employing SiO/sub 2//Si/sub 3/N/sub 4/ dielectrics which demand extremely severe geometries and exceedingly complex processes to meet the charge storage specifications of gigabit-scale DRAM's.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115149334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307503
P. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, S. Sawada
A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (>
提出并开发了一种新的埋沟道PMOSFET结构，该结构通过在主N+多晶硅栅电极旁边形成P+多晶硅侧壁间隔层来实现深亚微米应用。通过使用这种新的器件结构，0.3 μ m PMOSFET的电流可驱动性提高了约40%。电流可驱动性的显著增加可以归因于寄生电阻的降低，这是由于在两个P+多晶硅侧壁间隔层下形成的P型反转层。由于N+多晶硅栅极与P+多晶硅衬垫的功函数不同，P+多晶硅衬垫下的硅表面总是比沟道更倒转。因此，寄生电阻总是远低于通道电阻。此外，这些诱导逆温层作为超浅结(>
{"title":"High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions","authors":"P. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, S. Sawada","doi":"10.1109/IEDM.1992.307503","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307503","url":null,"abstract":"A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (<or=100AA), which are self aligned to the P+ poly-Si spacers. Further reduction in the short-channel effects can be expected.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307348
A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai
Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<>
{"title":"Prospects of high voltage power ICs on thin SOI","authors":"A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai","doi":"10.1109/IEDM.1992.307348","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307348","url":null,"abstract":"Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120848272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307458
S. Takagi, A. Toriumi
The carrier transport properties under high field have been studied in Si MOSFETs experimentally from the following two points of view; velocity saturation and impact ionization. The electron and hole velocities in the inversion-layer were measured as a function of tangential electric field using high-resistive gate MOSFETs. It has been found that the saturation velocity is dependent on the surface carrier concentration. The impact ionization rate was studied as a parameter of the length of the pinch-off region in MOSFETs. The suppression of the ionization rate and the enhancement of anisotropic impact ionization have been simultaneously observed at 81 K in the MOSFETs with the shorter length of pinch-off region. The non-stationary transport of hot carriers in the pinch-off region is responsible for these phenomena.<>
{"title":"New experimental findings on hot carrier transport under velocity saturation regime in Si MOSFETs","authors":"S. Takagi, A. Toriumi","doi":"10.1109/IEDM.1992.307458","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307458","url":null,"abstract":"The carrier transport properties under high field have been studied in Si MOSFETs experimentally from the following two points of view; velocity saturation and impact ionization. The electron and hole velocities in the inversion-layer were measured as a function of tangential electric field using high-resistive gate MOSFETs. It has been found that the saturation velocity is dependent on the surface carrier concentration. The impact ionization rate was studied as a parameter of the length of the pinch-off region in MOSFETs. The suppression of the ionization rate and the enhancement of anisotropic impact ionization have been simultaneously observed at 81 K in the MOSFETs with the shorter length of pinch-off region. The non-stationary transport of hot carriers in the pinch-off region is responsible for these phenomena.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307395
H. Ishii, T. Shibata, H. Kosaka, T. Ohmi
This paper describes the design and architecture of a neural network having a hardware-learning capability, in which a functional transistor called neuron MOSFET (neuMOS or vMOS) is utilized as a key element. In order to implement learning algorithm on the chip, a new hardware-oriented backpropagation learning algorithm has been developed by modifying and simplifying the original backpropagation algorithm. In addition, a six-transistor synapse cell which is free from standby power dissipation and is capable of representing both positive and negative weights (excitatory and inhibitory synapse functions) under a single 5 V power supply has been developed for use on a self-learning chip.<>
{"title":"Hardware-backpropagation learning of neuron MOS neural networks","authors":"H. Ishii, T. Shibata, H. Kosaka, T. Ohmi","doi":"10.1109/IEDM.1992.307395","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307395","url":null,"abstract":"This paper describes the design and architecture of a neural network having a hardware-learning capability, in which a functional transistor called neuron MOSFET (neuMOS or vMOS) is utilized as a key element. In order to implement learning algorithm on the chip, a new hardware-oriented backpropagation learning algorithm has been developed by modifying and simplifying the original backpropagation algorithm. In addition, a six-transistor synapse cell which is free from standby power dissipation and is capable of representing both positive and negative weights (excitatory and inhibitory synapse functions) under a single 5 V power supply has been developed for use on a self-learning chip.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130562109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307380
Jiang Liu, J. Hren, C. Sune, G. W. Jones, H. Gray
The behavior of electron emission from pyramid-shaped silicon field emitters has been studied by direct imaging of electron emission as well as by emission current-voltage measurement. Oxide covered silicon emitter surfaces have resulted in structureless emission patterns. The electron emitting angle is found to vary significantly with the extraction voltage or the emission current. Experimental measurement and analysis of emission images under moderate operating conditions showed that resulted final emitting angles are under 13 degrees while initial electron emitting angles from the emitter could be as high as 18 degrees .<>
{"title":"Field emission imaging study of silicon field emitters","authors":"Jiang Liu, J. Hren, C. Sune, G. W. Jones, H. Gray","doi":"10.1109/IEDM.1992.307380","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307380","url":null,"abstract":"The behavior of electron emission from pyramid-shaped silicon field emitters has been studied by direct imaging of electron emission as well as by emission current-voltage measurement. Oxide covered silicon emitter surfaces have resulted in structureless emission patterns. The electron emitting angle is found to vary significantly with the extraction voltage or the emission current. Experimental measurement and analysis of emission images under moderate operating conditions showed that resulted final emitting angles are under 13 degrees while initial electron emitting angles from the emitter could be as high as 18 degrees .<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307525
L. Manchanda, R. Storz, R. Yan, K. F. Lee, E. Westerwick
We report the first clear observation of the onset of impact ionization at 0.6V and 0.8V in O.1 mu m Si devices operating at 170K and 300K, respectively. These onset voltages were directly extracted from experimental bell-shaped substrate currents constituting clear evidence of impact ionization below the band gap of silicon. At low temperatures we observe simultaneous reductions in the threshold voltage for impact ionization, and the impact ionization current. These results suggest the operation of possible new mechanisms in addition to the usual carrier/carrier and carrier/optical phonon interactions.<>
我们报道了在0.1 μ m Si器件中，分别在170K和300K下，在0.6V和0.8V下撞击电离的首次清晰观察。这些起始电压直接从实验钟形衬底电流中提取，构成硅带隙以下冲击电离的明确证据。在低温下，我们观察到冲击电离的阈值电压和冲击电离电流同时降低。这些结果表明，除了通常的载流子/载流子和载流子/光学声子相互作用之外，还存在可能的新机制。
{"title":"Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 mu m Si MOSFETs","authors":"L. Manchanda, R. Storz, R. Yan, K. F. Lee, E. Westerwick","doi":"10.1109/IEDM.1992.307525","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307525","url":null,"abstract":"We report the first clear observation of the onset of impact ionization at 0.6V and 0.8V in O.1 mu m Si devices operating at 170K and 300K, respectively. These onset voltages were directly extracted from experimental bell-shaped substrate currents constituting clear evidence of impact ionization below the band gap of silicon. At low temperatures we observe simultaneous reductions in the threshold voltage for impact ionization, and the impact ionization current. These results suggest the operation of possible new mechanisms in addition to the usual carrier/carrier and carrier/optical phonon interactions.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307451
N. Kato, T. Yamada, S. Yamada, T. Nakamura, T. Hamano
The degradation of polysilicon thin film transistors was investigated under DC stress. There was a strong relationship between increase of threshold voltage and power consumption under stressing. The channel was found to reach high temperature by Joule heat because of poor thermal conductivity of the quartz substrate. It is shown that this temperature rise accelerates the degradation caused by gate stress.<>
{"title":"Degradation mechanism of polysilicon TFTs under DC stress","authors":"N. Kato, T. Yamada, S. Yamada, T. Nakamura, T. Hamano","doi":"10.1109/IEDM.1992.307451","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307451","url":null,"abstract":"The degradation of polysilicon thin film transistors was investigated under DC stress. There was a strong relationship between increase of threshold voltage and power consumption under stressing. The channel was found to reach high temperature by Joule heat because of poor thermal conductivity of the quartz substrate. It is shown that this temperature rise accelerates the degradation caused by gate stress.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307459
W. Hansch
The components of a simulation tool for a self-consistent calculation of DC hot electron device degradation are discussed. The tool is based on the drift diffusion approximation including one of its generalizations. It includes carrier injection into the gate oxide, trapping and detrapping of oxide charges and interface states, and their feed back onto the device field.<>
{"title":"Modeling hot carrier reliability of MOSFET: what is necessary and what is possible?","authors":"W. Hansch","doi":"10.1109/IEDM.1992.307459","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307459","url":null,"abstract":"The components of a simulation tool for a self-consistent calculation of DC hot electron device degradation are discussed. The tool is based on the drift diffusion approximation including one of its generalizations. It includes carrier injection into the gate oxide, trapping and detrapping of oxide charges and interface states, and their feed back onto the device field.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124951378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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