Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307503
P. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, S. Sawada
A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (>
提出并开发了一种新的埋沟道PMOSFET结构，该结构通过在主N+多晶硅栅电极旁边形成P+多晶硅侧壁间隔层来实现深亚微米应用。通过使用这种新的器件结构，0.3 μ m PMOSFET的电流可驱动性提高了约40%。电流可驱动性的显著增加可以归因于寄生电阻的降低，这是由于在两个P+多晶硅侧壁间隔层下形成的P型反转层。由于N+多晶硅栅极与P+多晶硅衬垫的功函数不同，P+多晶硅衬垫下的硅表面总是比沟道更倒转。因此，寄生电阻总是远低于通道电阻。此外，这些诱导逆温层作为超浅结(>
{"title":"High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions","authors":"P. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, S. Sawada","doi":"10.1109/IEDM.1992.307503","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307503","url":null,"abstract":"A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (<or=100AA), which are self aligned to the P+ poly-Si spacers. Further reduction in the short-channel effects can be expected.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307375
J. Hwang, G. Pollack
Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<>
{"title":"Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS","authors":"J. Hwang, G. Pollack","doi":"10.1109/IEDM.1992.307375","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307375","url":null,"abstract":"Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307478
T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<>
{"title":"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs","authors":"T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio","doi":"10.1109/IEDM.1992.307478","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307478","url":null,"abstract":"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307483
J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<>
{"title":"A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs","authors":"J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch","doi":"10.1109/IEDM.1992.307483","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307483","url":null,"abstract":"An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125151009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307380
Jiang Liu, J. Hren, C. Sune, G. W. Jones, H. Gray
The behavior of electron emission from pyramid-shaped silicon field emitters has been studied by direct imaging of electron emission as well as by emission current-voltage measurement. Oxide covered silicon emitter surfaces have resulted in structureless emission patterns. The electron emitting angle is found to vary significantly with the extraction voltage or the emission current. Experimental measurement and analysis of emission images under moderate operating conditions showed that resulted final emitting angles are under 13 degrees while initial electron emitting angles from the emitter could be as high as 18 degrees .<>
{"title":"Field emission imaging study of silicon field emitters","authors":"Jiang Liu, J. Hren, C. Sune, G. W. Jones, H. Gray","doi":"10.1109/IEDM.1992.307380","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307380","url":null,"abstract":"The behavior of electron emission from pyramid-shaped silicon field emitters has been studied by direct imaging of electron emission as well as by emission current-voltage measurement. Oxide covered silicon emitter surfaces have resulted in structureless emission patterns. The electron emitting angle is found to vary significantly with the extraction voltage or the emission current. Experimental measurement and analysis of emission images under moderate operating conditions showed that resulted final emitting angles are under 13 degrees while initial electron emitting angles from the emitter could be as high as 18 degrees .<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307525
L. Manchanda, R. Storz, R. Yan, K. F. Lee, E. Westerwick
We report the first clear observation of the onset of impact ionization at 0.6V and 0.8V in O.1 mu m Si devices operating at 170K and 300K, respectively. These onset voltages were directly extracted from experimental bell-shaped substrate currents constituting clear evidence of impact ionization below the band gap of silicon. At low temperatures we observe simultaneous reductions in the threshold voltage for impact ionization, and the impact ionization current. These results suggest the operation of possible new mechanisms in addition to the usual carrier/carrier and carrier/optical phonon interactions.<>
我们报道了在0.1 μ m Si器件中，分别在170K和300K下，在0.6V和0.8V下撞击电离的首次清晰观察。这些起始电压直接从实验钟形衬底电流中提取，构成硅带隙以下冲击电离的明确证据。在低温下，我们观察到冲击电离的阈值电压和冲击电离电流同时降低。这些结果表明，除了通常的载流子/载流子和载流子/光学声子相互作用之外，还存在可能的新机制。
{"title":"Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 mu m Si MOSFETs","authors":"L. Manchanda, R. Storz, R. Yan, K. F. Lee, E. Westerwick","doi":"10.1109/IEDM.1992.307525","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307525","url":null,"abstract":"We report the first clear observation of the onset of impact ionization at 0.6V and 0.8V in O.1 mu m Si devices operating at 170K and 300K, respectively. These onset voltages were directly extracted from experimental bell-shaped substrate currents constituting clear evidence of impact ionization below the band gap of silicon. At low temperatures we observe simultaneous reductions in the threshold voltage for impact ionization, and the impact ionization current. These results suggest the operation of possible new mechanisms in addition to the usual carrier/carrier and carrier/optical phonon interactions.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307451
N. Kato, T. Yamada, S. Yamada, T. Nakamura, T. Hamano
The degradation of polysilicon thin film transistors was investigated under DC stress. There was a strong relationship between increase of threshold voltage and power consumption under stressing. The channel was found to reach high temperature by Joule heat because of poor thermal conductivity of the quartz substrate. It is shown that this temperature rise accelerates the degradation caused by gate stress.<>
{"title":"Degradation mechanism of polysilicon TFTs under DC stress","authors":"N. Kato, T. Yamada, S. Yamada, T. Nakamura, T. Hamano","doi":"10.1109/IEDM.1992.307451","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307451","url":null,"abstract":"The degradation of polysilicon thin film transistors was investigated under DC stress. There was a strong relationship between increase of threshold voltage and power consumption under stressing. The channel was found to reach high temperature by Joule heat because of poor thermal conductivity of the quartz substrate. It is shown that this temperature rise accelerates the degradation caused by gate stress.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307458
S. Takagi, A. Toriumi
The carrier transport properties under high field have been studied in Si MOSFETs experimentally from the following two points of view; velocity saturation and impact ionization. The electron and hole velocities in the inversion-layer were measured as a function of tangential electric field using high-resistive gate MOSFETs. It has been found that the saturation velocity is dependent on the surface carrier concentration. The impact ionization rate was studied as a parameter of the length of the pinch-off region in MOSFETs. The suppression of the ionization rate and the enhancement of anisotropic impact ionization have been simultaneously observed at 81 K in the MOSFETs with the shorter length of pinch-off region. The non-stationary transport of hot carriers in the pinch-off region is responsible for these phenomena.<>
{"title":"New experimental findings on hot carrier transport under velocity saturation regime in Si MOSFETs","authors":"S. Takagi, A. Toriumi","doi":"10.1109/IEDM.1992.307458","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307458","url":null,"abstract":"The carrier transport properties under high field have been studied in Si MOSFETs experimentally from the following two points of view; velocity saturation and impact ionization. The electron and hole velocities in the inversion-layer were measured as a function of tangential electric field using high-resistive gate MOSFETs. It has been found that the saturation velocity is dependent on the surface carrier concentration. The impact ionization rate was studied as a parameter of the length of the pinch-off region in MOSFETs. The suppression of the ionization rate and the enhancement of anisotropic impact ionization have been simultaneously observed at 81 K in the MOSFETs with the shorter length of pinch-off region. The non-stationary transport of hot carriers in the pinch-off region is responsible for these phenomena.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307395
H. Ishii, T. Shibata, H. Kosaka, T. Ohmi
This paper describes the design and architecture of a neural network having a hardware-learning capability, in which a functional transistor called neuron MOSFET (neuMOS or vMOS) is utilized as a key element. In order to implement learning algorithm on the chip, a new hardware-oriented backpropagation learning algorithm has been developed by modifying and simplifying the original backpropagation algorithm. In addition, a six-transistor synapse cell which is free from standby power dissipation and is capable of representing both positive and negative weights (excitatory and inhibitory synapse functions) under a single 5 V power supply has been developed for use on a self-learning chip.<>
{"title":"Hardware-backpropagation learning of neuron MOS neural networks","authors":"H. Ishii, T. Shibata, H. Kosaka, T. Ohmi","doi":"10.1109/IEDM.1992.307395","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307395","url":null,"abstract":"This paper describes the design and architecture of a neural network having a hardware-learning capability, in which a functional transistor called neuron MOSFET (neuMOS or vMOS) is utilized as a key element. In order to implement learning algorithm on the chip, a new hardware-oriented backpropagation learning algorithm has been developed by modifying and simplifying the original backpropagation algorithm. In addition, a six-transistor synapse cell which is free from standby power dissipation and is capable of representing both positive and negative weights (excitatory and inhibitory synapse functions) under a single 5 V power supply has been developed for use on a self-learning chip.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130562109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307484
C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy
A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<>
{"title":"High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures","authors":"C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy","doi":"10.1109/IEDM.1992.307484","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307484","url":null,"abstract":"A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"83 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122624318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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