Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791747
La Violette, Figarols François, Pic Nicolas, Vitrani Thomas
The semiconductor industry is a highly demanding industry in terms of quality and cleanliness of the production environment. Indeed, metallic contamination is to be avoided because harmful for the chips. The goal of this study is to share experiences of metal contaminations on bare silicon wafers and how complementary metrology methods can be used to detect low levels of metals and find the root cause. It illustrates the difficulty to choose between different techniques to detect a problem and the dependency of thermal treatment to detect a contaminant by lifetime techniques.
{"title":"Complementary metrology techniques to detect low levels of metallic contaminations on bare silicon wafers","authors":"La Violette, Figarols François, Pic Nicolas, Vitrani Thomas","doi":"10.1109/ASMC.2019.8791747","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791747","url":null,"abstract":"The semiconductor industry is a highly demanding industry in terms of quality and cleanliness of the production environment. Indeed, metallic contamination is to be avoided because harmful for the chips. The goal of this study is to share experiences of metal contaminations on bare silicon wafers and how complementary metrology methods can be used to detect low levels of metals and find the root cause. It illustrates the difficulty to choose between different techniques to detect a problem and the dependency of thermal treatment to detect a contaminant by lifetime techniques.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131343846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791833
C. Schuermyer, Steve Palosh, P. Babighian, Yan Pan
The increasing challenges with relying on Physical Failure Analysis and inline inspection for ramping the yield are the reason that Volume Scan Diagnostics Analysis (VSDA) has become a mainstream methodology that supplements traditional yield learning. Because scan diagnostics are inherently noisy, the results often require expert knowledge to manually select the location that has the highest likelihood of being correct. In this paper, Failure Mechanism Analysis (FMA) applies the technique of Bayesian Machine Learning in a yield analysis system that can empirically estimate sources of yield loss using physical diagnostic information.
{"title":"Application of Bayesian Machine Learning To Create A Low-Cost Silicon Failure Mechanism Pareto","authors":"C. Schuermyer, Steve Palosh, P. Babighian, Yan Pan","doi":"10.1109/ASMC.2019.8791833","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791833","url":null,"abstract":"The increasing challenges with relying on Physical Failure Analysis and inline inspection for ramping the yield are the reason that Volume Scan Diagnostics Analysis (VSDA) has become a mainstream methodology that supplements traditional yield learning. Because scan diagnostics are inherently noisy, the results often require expert knowledge to manually select the location that has the highest likelihood of being correct. In this paper, Failure Mechanism Analysis (FMA) applies the technique of Bayesian Machine Learning in a yield analysis system that can empirically estimate sources of yield loss using physical diagnostic information.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132813963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791759
R. Hafer, Hong Lin, Brian Yueh-Ling Hsieh
For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped to production. An in-line monitor was needed but could not be dependent on kerf structures to monitor within-reticle variation, since these monitored only narrow-gate within-wafer and wafer-to-wafer variation. So, a within reticle inspection using Electron Beam Inspection (EBI) was used to characterize the within-reticle and within-wafer variation of the wide-gate structures.
{"title":"Electron Beam Inspection: Within Die and Within- Wafer monitoring of RMG CMP","authors":"R. Hafer, Hong Lin, Brian Yueh-Ling Hsieh","doi":"10.1109/ASMC.2019.8791759","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791759","url":null,"abstract":"For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped to production. An in-line monitor was needed but could not be dependent on kerf structures to monitor within-reticle variation, since these monitored only narrow-gate within-wafer and wafer-to-wafer variation. So, a within reticle inspection using Electron Beam Inspection (EBI) was used to characterize the within-reticle and within-wafer variation of the wide-gate structures.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791800
S. Grover, Philip Thompson
Photolithography is one of the most critical operations in semiconductor manufacturing. Due to increasing complexity and stricter limits on CD control, rework routes exist that involve plasma-based resist ash, wet clean and send back again to coat, expose and develop. Yield loss was observed on rework of metal layer wafers where the critical dimensions were out of control on inspection post lithography. The cause of the yield loss was primarily due to formation of Al2Cu precipitates due to heat cycling of 0.5wt.% Cu below 293°C. This paper describes the development of a metal-layer photo rework scheme that involved a reduction of amount of temperature cycling steps in a dry strip chamber and changing process temperature from 270°C to 300°C (from precipitation to anneal region of Al2Cu) to significantly improve die yield on reworked wafers between 90-130nm technology nodes.
{"title":"Optimization of Metal Photo Rework Dry Strip Scheme for Yield Improvement : YE: Yield Enhancement/Learning","authors":"S. Grover, Philip Thompson","doi":"10.1109/ASMC.2019.8791800","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791800","url":null,"abstract":"Photolithography is one of the most critical operations in semiconductor manufacturing. Due to increasing complexity and stricter limits on CD control, rework routes exist that involve plasma-based resist ash, wet clean and send back again to coat, expose and develop. Yield loss was observed on rework of metal layer wafers where the critical dimensions were out of control on inspection post lithography. The cause of the yield loss was primarily due to formation of Al2Cu precipitates due to heat cycling of 0.5wt.% Cu below 293°C. This paper describes the development of a metal-layer photo rework scheme that involved a reduction of amount of temperature cycling steps in a dry strip chamber and changing process temperature from 270°C to 300°C (from precipitation to anneal region of Al2Cu) to significantly improve die yield on reworked wafers between 90-130nm technology nodes.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127296119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791744
D. Tucker, R. Edmonds, C. Chamberlain
Bump processing is a very common, cost-effective packaging technique which requires thick (>1 µm) AlCu top metal deposition. Use of this thicker metal has led to numerous process integration and defect inspection challenges. Several problems lurk at the edges of the multidimensional process window for this thick metal module. They include inducing soft shorts through metal spires or metal residuals, enhancing copper precipitates, and the anomalies generated from these precipitates. These anomalies lead to challenges obtaining useful defect inspection data and also adverse effects post fab bump processing [1]. Bump photo processing often experiences severe alignment problems due to inability to discern alignment marks. The primary cause for alignment fails is the copper precipitate anomalies. There are additional variables discussed as well in deposition and etch processes.In this paper, we detail this multi-variable fab integration problem initiated by challenges with thick metallization processing and outline the ways to minimize the negative effects.
{"title":"Resolving Integration Issues from Bump Metal Processing","authors":"D. Tucker, R. Edmonds, C. Chamberlain","doi":"10.1109/ASMC.2019.8791744","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791744","url":null,"abstract":"Bump processing is a very common, cost-effective packaging technique which requires thick (>1 µm) AlCu top metal deposition. Use of this thicker metal has led to numerous process integration and defect inspection challenges. Several problems lurk at the edges of the multidimensional process window for this thick metal module. They include inducing soft shorts through metal spires or metal residuals, enhancing copper precipitates, and the anomalies generated from these precipitates. These anomalies lead to challenges obtaining useful defect inspection data and also adverse effects post fab bump processing [1]. Bump photo processing often experiences severe alignment problems due to inability to discern alignment marks. The primary cause for alignment fails is the copper precipitate anomalies. There are additional variables discussed as well in deposition and etch processes.In this paper, we detail this multi-variable fab integration problem initiated by challenges with thick metallization processing and outline the ways to minimize the negative effects.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126019426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791762
Nathaniel Mowell, B. Sheumaker, Timothy Han, Joe Chaung, Shail P. Sanghavi, Y. Khopkar, F. Levitov, Brandon Bielec, D. Salvador, Kareem Naguib, Vu Nguyen
Precise control over the lithography process is vital to high volume manufacturing in the semiconductor industry. As integrated circuit design continues to move to smaller and smaller nodes, with increasingly intricate architectures, the number of lithography steps and their importance to the overall process grows. Current advances in Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) are driving these increases. As the number of lithography steps increases it becomes critical to have effective monitoring of both the lithography process and tool health. In this paper we present the current methodology for lithography Photo Track Monitoring (PTM) using Inspection, Review, and Classification to allow for excursion and tool health monitoring.This PTM qualification process is advantageous over other methodologies for evaluating lithography performance due to its similarity to production processing. PTM adds a new line of defense and captures a new signal that can be directly correlated to on-product defectivity more effectively than previous dry or coat- only qualification processes. The data generated provides feedback on material and tool issues lending it to be more useful for determining root cause of process, hardware or photo chemical concerns. PTM gives the opportunity to evaluate and determine level of risk without utilizing production wafers.After processing through the lithography track and scanner, PTM wafers are inspected on a high Numerical Aperture, normal illumination, Deep Ultraviolet laser-based inspection platform. A sampling of defect locations, per wafer, are reviewed on Defect Review Scanning Electron Microscope (DR SEM) and classified using Automatic Defect Classification (ADC). Control limits are set for the process based on statistical data trends over time allowing for Statistical Process Control (SPC) charts to be generated (Figure 1).The excursion wafers and, by correlation, lithography excursions are identified based on the SPC methodologies. Inaccurate inspection data, labeled as inspection tool excursions, can cause true lithography-related excursions to be missed. Therefore, stable and reliable inspection data is crucial. Through recipe stabilization we have been able to achieve long term stability.The effectiveness of this PTM inspection flow is highlighted in the case of a stepper striping defect caused by a fiber on the immersion hood assembly. Other lithography monitoring methodologies, track monitors and scanner particle checks, did not show this defect, emphasizing the usefulness of the PTM detection method. The PTM failing on the SPC chart, thus flagged as an excursion and prompting investigation, helped to reduce exposure of product wafers. The product wafers that did process prior to the PTM failure showed an identical striping signature proving a direct correlation of PTM to product. This correlation allowed for PTM wafers to be used to run partitions within the tool to identify
{"title":"Criticality of Photo Track Monitoring for Lithography Defect Control","authors":"Nathaniel Mowell, B. Sheumaker, Timothy Han, Joe Chaung, Shail P. Sanghavi, Y. Khopkar, F. Levitov, Brandon Bielec, D. Salvador, Kareem Naguib, Vu Nguyen","doi":"10.1109/ASMC.2019.8791762","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791762","url":null,"abstract":"Precise control over the lithography process is vital to high volume manufacturing in the semiconductor industry. As integrated circuit design continues to move to smaller and smaller nodes, with increasingly intricate architectures, the number of lithography steps and their importance to the overall process grows. Current advances in Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) are driving these increases. As the number of lithography steps increases it becomes critical to have effective monitoring of both the lithography process and tool health. In this paper we present the current methodology for lithography Photo Track Monitoring (PTM) using Inspection, Review, and Classification to allow for excursion and tool health monitoring.This PTM qualification process is advantageous over other methodologies for evaluating lithography performance due to its similarity to production processing. PTM adds a new line of defense and captures a new signal that can be directly correlated to on-product defectivity more effectively than previous dry or coat- only qualification processes. The data generated provides feedback on material and tool issues lending it to be more useful for determining root cause of process, hardware or photo chemical concerns. PTM gives the opportunity to evaluate and determine level of risk without utilizing production wafers.After processing through the lithography track and scanner, PTM wafers are inspected on a high Numerical Aperture, normal illumination, Deep Ultraviolet laser-based inspection platform. A sampling of defect locations, per wafer, are reviewed on Defect Review Scanning Electron Microscope (DR SEM) and classified using Automatic Defect Classification (ADC). Control limits are set for the process based on statistical data trends over time allowing for Statistical Process Control (SPC) charts to be generated (Figure 1).The excursion wafers and, by correlation, lithography excursions are identified based on the SPC methodologies. Inaccurate inspection data, labeled as inspection tool excursions, can cause true lithography-related excursions to be missed. Therefore, stable and reliable inspection data is crucial. Through recipe stabilization we have been able to achieve long term stability.The effectiveness of this PTM inspection flow is highlighted in the case of a stepper striping defect caused by a fiber on the immersion hood assembly. Other lithography monitoring methodologies, track monitors and scanner particle checks, did not show this defect, emphasizing the usefulness of the PTM detection method. The PTM failing on the SPC chart, thus flagged as an excursion and prompting investigation, helped to reduce exposure of product wafers. The product wafers that did process prior to the PTM failure showed an identical striping signature proving a direct correlation of PTM to product. This correlation allowed for PTM wafers to be used to run partitions within the tool to identify","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125277768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791760
T. Esposito, Jay K Shah, Abhinav Jain, F. Levitov, J. G. Sheridan, Shashi Shekhar, S. Jen, V. Aristov, Hoang Nguyen
Defect metrology for advanced FinFET devices faces a variety of challenges in terms of accurate classification of Defect Review Scanning Electron Microscopy (DR-SEM) images. As the Defect of Interest (DOI) size shrinks in proportion to the printed feature dimension, it is critical that these platforms adjust to continue to provide the best possible defect classification. This can be achieved most efficiently by introducing Computer-Aided Design (CAD) information into these platforms. In order to improve imaging of defects in DR-SEM, CAD data is used to enhance the alignment step, providing more accurate navigation to defects and allowing the magnification to scale according to the smaller defect size. We present a streamlined method to introduce this CAD based alignment step into the existing recipe management system on the DR-SEM platform. While decreasing image FOV is beneficial, the introduction of CAD information into Automatic Defect Classification (ADC) can provide valuable information on the defect’s location. Design Based ADC (DBA) achieves this by providing the means to differentiate the defect’s impact on device performance based on CAD data such as mask or process step. We present two case studies of DBA on multi- patterning and epi layers in the sub-1x FinFET process.
{"title":"Integration of Computer-Aided Design (CAD) Information into a Defect-Review SEM Platform and Design Based Automatic Defect Classification : DI: Defect Inspection and Reduction","authors":"T. Esposito, Jay K Shah, Abhinav Jain, F. Levitov, J. G. Sheridan, Shashi Shekhar, S. Jen, V. Aristov, Hoang Nguyen","doi":"10.1109/ASMC.2019.8791760","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791760","url":null,"abstract":"Defect metrology for advanced FinFET devices faces a variety of challenges in terms of accurate classification of Defect Review Scanning Electron Microscopy (DR-SEM) images. As the Defect of Interest (DOI) size shrinks in proportion to the printed feature dimension, it is critical that these platforms adjust to continue to provide the best possible defect classification. This can be achieved most efficiently by introducing Computer-Aided Design (CAD) information into these platforms. In order to improve imaging of defects in DR-SEM, CAD data is used to enhance the alignment step, providing more accurate navigation to defects and allowing the magnification to scale according to the smaller defect size. We present a streamlined method to introduce this CAD based alignment step into the existing recipe management system on the DR-SEM platform. While decreasing image FOV is beneficial, the introduction of CAD information into Automatic Defect Classification (ADC) can provide valuable information on the defect’s location. Design Based ADC (DBA) achieves this by providing the means to differentiate the defect’s impact on device performance based on CAD data such as mask or process step. We present two case studies of DBA on multi- patterning and epi layers in the sub-1x FinFET process.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"95 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123365259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791829
K. Erickson, Thuc M. Dinh, Eric Ellsworth, Hongxu Duan
Many of the advanced gas-phase processes used in state-of-the art microelectronic fabrication place higher demands on liquid vapor delivery solutions. Vaporization challenges include a diverse range of liquids with unique material properties, the use of liquids with low vapor pressure or the use of liquids with a small window between thermal decomposition and vaporization. The growing implementation of short pulse processing also creates a need for faster response times. The Performance Enhanced Turbo-VaporizerTM Liquid Delivery System presents a new alternative for liquid vaporization.
{"title":"Improved Liquid Source Vaporization for CVD & ALD Precursors","authors":"K. Erickson, Thuc M. Dinh, Eric Ellsworth, Hongxu Duan","doi":"10.1109/ASMC.2019.8791829","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791829","url":null,"abstract":"Many of the advanced gas-phase processes used in state-of-the art microelectronic fabrication place higher demands on liquid vapor delivery solutions. Vaporization challenges include a diverse range of liquids with unique material properties, the use of liquids with low vapor pressure or the use of liquids with a small window between thermal decomposition and vaporization. The growing implementation of short pulse processing also creates a need for faster response times. The Performance Enhanced Turbo-VaporizerTM Liquid Delivery System presents a new alternative for liquid vaporization.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123283204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791834
C. Hartig, A. Urbanowicz, D. Likhachev, Ines Altendorf, A. Reichel, M. Weisheit
The majority of scatterometric models used in production control assume constant optical properties of the materials included into the film stack. Only dimensional parameters are assumed as the degrees of freedom. This assumption negatively impacts model precision and accuracy (especially with the trend of scaling down the critical dimensions). In this work we focus on the modeling of Cu and TaN/Ta optical properties in back-end-of-line applications and consider the impact of Cu optical properties modifications in the trenches and as a substrate. We also consider the Cu transparency threshold when Cu acts as a substrate in the film stack. In the case of ultrathin Cu substrate the model output becomes invalid. Quite frequently this fact is not reflected in the goodness of fit. We show that accurate optical modeling of Cu is essential to achieve the required scatterometric model quality for automatic process control in microelectronic production. As a result, we obtain appreciably better matching with electrical data. Therefore, electrical performance can be predicted early in production flow. The modeling methodology presented here can be applied for all technology nodes and also other thin metals such as Co and Ru.
{"title":"Advanced optical modeling of thin metals for improved robustness and accuracy of scatterometric models","authors":"C. Hartig, A. Urbanowicz, D. Likhachev, Ines Altendorf, A. Reichel, M. Weisheit","doi":"10.1109/ASMC.2019.8791834","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791834","url":null,"abstract":"The majority of scatterometric models used in production control assume constant optical properties of the materials included into the film stack. Only dimensional parameters are assumed as the degrees of freedom. This assumption negatively impacts model precision and accuracy (especially with the trend of scaling down the critical dimensions). In this work we focus on the modeling of Cu and TaN/Ta optical properties in back-end-of-line applications and consider the impact of Cu optical properties modifications in the trenches and as a substrate. We also consider the Cu transparency threshold when Cu acts as a substrate in the film stack. In the case of ultrathin Cu substrate the model output becomes invalid. Quite frequently this fact is not reflected in the goodness of fit. We show that accurate optical modeling of Cu is essential to achieve the required scatterometric model quality for automatic process control in microelectronic production. As a result, we obtain appreciably better matching with electrical data. Therefore, electrical performance can be predicted early in production flow. The modeling methodology presented here can be applied for all technology nodes and also other thin metals such as Co and Ru.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129952852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791768
R. Jani, John Sukjin Kim, Minhwa Kim Jacoby, S. Rajendran, Shrikant Kashibhatla
Optimizing NF3 cleaning is crucial in minimizing defects seen in the process. In this paper, we took a different approach to maximize particle reduction using both conventional and non- conventional endpointing methods. Cleaning indicators, typically monitored during cleaning recipe, were also monitored during deposition. Implementation of additional purging significantly reduced remnants of cleaning byproducts during deposition. Our additional testing with reduction and dilution of NF3 flow showed improvements in cleaning efficiency. In this paper, we show that optimization of NF3 cleaning recipe using methods in addition to cleaning time optimization can reduce defects seen in the process.
{"title":"Application of Residual Gas Analyzer(RGA) for Particle Reduction in ALD Oxide : DI: Defect Inspection and Reduction","authors":"R. Jani, John Sukjin Kim, Minhwa Kim Jacoby, S. Rajendran, Shrikant Kashibhatla","doi":"10.1109/ASMC.2019.8791768","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791768","url":null,"abstract":"Optimizing NF3 cleaning is crucial in minimizing defects seen in the process. In this paper, we took a different approach to maximize particle reduction using both conventional and non- conventional endpointing methods. Cleaning indicators, typically monitored during cleaning recipe, were also monitored during deposition. Implementation of additional purging significantly reduced remnants of cleaning byproducts during deposition. Our additional testing with reduction and dilution of NF3 flow showed improvements in cleaning efficiency. In this paper, we show that optimization of NF3 cleaning recipe using methods in addition to cleaning time optimization can reduce defects seen in the process.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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