Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791799
G. Padron-Wells, Michael VanOverloop, Jun‐Seok Yeo, Avun Abit, Kevin T. Finneran, Lenore Mclaughlin, Ryan Greuter
Fluorine saturated Yttrium based coatings have been developed to generate highly stable electrical, mechanical and chemical interfaces that minimize defect generation in reactive plasma environments utilized in the manufacturing process of advanced ULSI microchips. In this study, single-layer YF3 (YF) coatings are compared to the current dual-layer coatings DLC (Y2O3/YF3) option. The performance of the YF interface compared to that of dual-layer DLC is discussed. The results show that the electrical, mechanical and chemical properties of YF based functional coating are not detrimentally affected when exposed to harsh halide enriched environments and thereby are suitable to be applied as protective layers on anodized surfaces to prevent extreme surface degradation due to Fluorine/Oxygen radical interactions. The achieved thermodynamic stability on YF based films is attributed to the higher enthalpy of dissociation of the Y-F bond compared to that of Y-O at the base of the dual-layer coating. Likewise, due to Fluorine electronegativity, it is shown that YF films undergo less interface volume expansion due to O replacement as traditionally observed in the Y2O3 base of the DLC coating. It is understood that volume expansion leads to interface cracks and weak points that generate particle defects. Ultimately, these YF films can be reliably employed on anodized etch reactor surfaces to improve defect as well as process limited yield (PLY) baselines on advanced ULSI technology nodes. Our work is focused on early evaluation and adoption of YF coatings to improve the development and manufacturing of advanced ULSI circuits.
{"title":"Fluorine Saturated Yttrium (YF) Based Coatings for Advanced Semiconductor ULSI Manufacturing","authors":"G. Padron-Wells, Michael VanOverloop, Jun‐Seok Yeo, Avun Abit, Kevin T. Finneran, Lenore Mclaughlin, Ryan Greuter","doi":"10.1109/ASMC.2019.8791799","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791799","url":null,"abstract":"Fluorine saturated Yttrium based coatings have been developed to generate highly stable electrical, mechanical and chemical interfaces that minimize defect generation in reactive plasma environments utilized in the manufacturing process of advanced ULSI microchips. In this study, single-layer YF3 (YF) coatings are compared to the current dual-layer coatings DLC (Y2O3/YF3) option. The performance of the YF interface compared to that of dual-layer DLC is discussed. The results show that the electrical, mechanical and chemical properties of YF based functional coating are not detrimentally affected when exposed to harsh halide enriched environments and thereby are suitable to be applied as protective layers on anodized surfaces to prevent extreme surface degradation due to Fluorine/Oxygen radical interactions. The achieved thermodynamic stability on YF based films is attributed to the higher enthalpy of dissociation of the Y-F bond compared to that of Y-O at the base of the dual-layer coating. Likewise, due to Fluorine electronegativity, it is shown that YF films undergo less interface volume expansion due to O replacement as traditionally observed in the Y2O3 base of the DLC coating. It is understood that volume expansion leads to interface cracks and weak points that generate particle defects. Ultimately, these YF films can be reliably employed on anodized etch reactor surfaces to improve defect as well as process limited yield (PLY) baselines on advanced ULSI technology nodes. Our work is focused on early evaluation and adoption of YF coatings to improve the development and manufacturing of advanced ULSI circuits.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791780
J. Warner, Kelly Orgeron
Semiconductor product cost and quality are significantly impacted by in-line inspection cycle times and on- board process sensors. There have been considerable software and hardware developments that have helped achieve our present day metrics but those are continuously being challenged. These developments have been through the OEM and manufacturing client joint development cycle which can be months or years long. To continue innovation and reduce the development cycle, a decentralized network for fast sensor integration and data management needs to be implemented.
{"title":"Decentralized network for next generation sensor integration and edge computing","authors":"J. Warner, Kelly Orgeron","doi":"10.1109/ASMC.2019.8791780","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791780","url":null,"abstract":"Semiconductor product cost and quality are significantly impacted by in-line inspection cycle times and on- board process sensors. There have been considerable software and hardware developments that have helped achieve our present day metrics but those are continuously being challenged. These developments have been through the OEM and manufacturing client joint development cycle which can be months or years long. To continue innovation and reduce the development cycle, a decentralized network for fast sensor integration and data management needs to be implemented.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128442679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791826
E. Ramanathan, V. Katragadda, A. Gasasira, M. Muthee, J. Riendeau, M. Hatzistergos, J. Mody, Kok Hin (Rick) Teo, Justin Clements, Jian-xiong Qiu, Qiushi Wang, Petrov Nicolai, Vincent Liao, Jung Tae Hwang, R. Krom, Vandana Venkatasubramanian, Colin Bombardier, Shafaat Ahmed, C. Montgomery, Owen E. Brown, Lloyd Smith, Alan Cusick, Edwin Soler, Bill Evans
Inline electrical testing in a semiconductor fabrication line is a very common method to monitor the line performance and to be able to detect any issue for the tested wafers. This helps to detect the problems much earlier. Detecting issues earlier not only stops the affected wafer from processing further, but it would be able to highlight an upstream process issue stopping other incoming wafers. Fundamental issues like high probe contact resistance (CRES) during test affects the measurement data integrity of critical device parameters. This also impacts the learning cycles as well as mean time to detect process / drift issues. Extensive data collection and experiments were able to conclude that the presence of copper oxide is the root cause of high CRES. Adhesion to different constructs explains variations seen in different designs.
{"title":"Study of Probe Contact Resistance Impact on Inline Testing with Different Bond Pad Design in BEOL","authors":"E. Ramanathan, V. Katragadda, A. Gasasira, M. Muthee, J. Riendeau, M. Hatzistergos, J. Mody, Kok Hin (Rick) Teo, Justin Clements, Jian-xiong Qiu, Qiushi Wang, Petrov Nicolai, Vincent Liao, Jung Tae Hwang, R. Krom, Vandana Venkatasubramanian, Colin Bombardier, Shafaat Ahmed, C. Montgomery, Owen E. Brown, Lloyd Smith, Alan Cusick, Edwin Soler, Bill Evans","doi":"10.1109/ASMC.2019.8791826","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791826","url":null,"abstract":"Inline electrical testing in a semiconductor fabrication line is a very common method to monitor the line performance and to be able to detect any issue for the tested wafers. This helps to detect the problems much earlier. Detecting issues earlier not only stops the affected wafer from processing further, but it would be able to highlight an upstream process issue stopping other incoming wafers. Fundamental issues like high probe contact resistance (CRES) during test affects the measurement data integrity of critical device parameters. This also impacts the learning cycles as well as mean time to detect process / drift issues. Extensive data collection and experiments were able to conclude that the presence of copper oxide is the root cause of high CRES. Adhesion to different constructs explains variations seen in different designs.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791757
M. Mehendale, J. Chen, J. Dai, R. Mair, M. Kotelyanskii, P. Mukundhan, T. Murray
The continuing shift to 3D integration requires formation of electrical interconnects between multiple vertically stacked Si devices to enable high speed, high bandwidth connections. Microbumps and through silicon vias (TSV) enable the high-density interconnects for die-to-die and die-to-wafer stacking for different applications. In this paper, we present acoustic metrology techniques for the measurement of multi-layer microbumps. One of the techniques, PULSE™ technology, is a very well-established mature solution for metal film thickness measurements. Repeatability and accuracy of the measurements more than adequately meets the process requirements. We also present a second nondestructive acoustic metrology for measuring taller copper pillars (> 30µm).
{"title":"Acoustic Metrology for Fine Pitch Microbumps in 3DIC","authors":"M. Mehendale, J. Chen, J. Dai, R. Mair, M. Kotelyanskii, P. Mukundhan, T. Murray","doi":"10.1109/ASMC.2019.8791757","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791757","url":null,"abstract":"The continuing shift to 3D integration requires formation of electrical interconnects between multiple vertically stacked Si devices to enable high speed, high bandwidth connections. Microbumps and through silicon vias (TSV) enable the high-density interconnects for die-to-die and die-to-wafer stacking for different applications. In this paper, we present acoustic metrology techniques for the measurement of multi-layer microbumps. One of the techniques, PULSE™ technology, is a very well-established mature solution for metal film thickness measurements. Repeatability and accuracy of the measurements more than adequately meets the process requirements. We also present a second nondestructive acoustic metrology for measuring taller copper pillars (> 30µm).","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124335193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791822
Yoshiyuki Seike, Hiroyuki Matsuoka, Shingo Matsuki, Taishi Segawa, Yoshinori Kobayashi, K. Miyachi, T. Mori
The cleaning processes of the electrical devices with pure water spray have a problem electrostatic discharge (ESD). In this report, the occurrence factors of ESD by measuring the amount of generated electric charge with flying droplets from a single-fluid spray in a Faraday cage have been indicated. Moreover, to prevent ESD, a prototype induction charging element was applied was installed at the position just after the injection. In the case of a straight jet at 5 MPa, generation charge of approximately 30% was suppressed by applying +10 kV of the induction charging element.
{"title":"Electrostatic discharge prevention in ultra-pure water spray cleaning aimed at CFM","authors":"Yoshiyuki Seike, Hiroyuki Matsuoka, Shingo Matsuki, Taishi Segawa, Yoshinori Kobayashi, K. Miyachi, T. Mori","doi":"10.1109/ASMC.2019.8791822","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791822","url":null,"abstract":"The cleaning processes of the electrical devices with pure water spray have a problem electrostatic discharge (ESD). In this report, the occurrence factors of ESD by measuring the amount of generated electric charge with flying droplets from a single-fluid spray in a Faraday cage have been indicated. Moreover, to prevent ESD, a prototype induction charging element was applied was installed at the position just after the injection. In the case of a straight jet at 5 MPa, generation charge of approximately 30% was suppressed by applying +10 kV of the induction charging element.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116201935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791807
T. Ning, CH Huang, J. Jensen, H. Chan, V. Wong
Wafer fabrication process data were analyzed in this paper using both linear and nonlinear bispectral analyses to examine the behavior of harmonics in the frequency domain. We used the spectral analyses to characterize and quantify the dynamic behavior of signal harmonics in the frequency domain. We focused on the measurements collected from three particular processing parameters during wafer processing. The data were divided into consecutive short segments to provide time-stamped behavior of the harmonic distributions. We also applied the nonlinear bispectral analysis to show that quadratic phase coupling interactions between the fundamental frequency and its harmonics exist, which contributes largely to the generation of multiple harmonics. Our results find that process measurements of the examined parameters exhibit a progressive change in time where the harmonic frequencies gradually reduced.
{"title":"Harmonic Analysis of Wafer Fabrication Data in the Frequency Domain : Topic: Advanced Process Control","authors":"T. Ning, CH Huang, J. Jensen, H. Chan, V. Wong","doi":"10.1109/ASMC.2019.8791807","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791807","url":null,"abstract":"Wafer fabrication process data were analyzed in this paper using both linear and nonlinear bispectral analyses to examine the behavior of harmonics in the frequency domain. We used the spectral analyses to characterize and quantify the dynamic behavior of signal harmonics in the frequency domain. We focused on the measurements collected from three particular processing parameters during wafer processing. The data were divided into consecutive short segments to provide time-stamped behavior of the harmonic distributions. We also applied the nonlinear bispectral analysis to show that quadratic phase coupling interactions between the fundamental frequency and its harmonics exist, which contributes largely to the generation of multiple harmonics. Our results find that process measurements of the examined parameters exhibit a progressive change in time where the harmonic frequencies gradually reduced.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130565598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791782
Qilin Chan, M. Ellefson, B. Mader, L. Zazzera, A. Simpson, D. Muradian, Jaimie Stomberg, U. Lagudu
This work describes advanced metrology based on Single Particle Inductively Coupled Plasma Mass Spectrometry (sp- ICP-MS) used in chemical mechanical planarization (CMP) process development. sp-ICP-MS was used to measure concentrations and sizes of ceria nanoparticles before and after CMP of silicon dioxide. Changes in the particle size distribution show a shift to lower median particle size after polishing, and an increase in the number of smaller particles. This result is consistent with previous reports which showed significant in- process reduction of the average ceria particle size after polishing. These new results are important because they demonstrate the application of sp-ICP-MS in the development of advanced CMP processes.
{"title":"Single Particle Inductively Coupled Plasma Mass Spectrometry Metrology for Advanced Semiconductor CMP Process Development","authors":"Qilin Chan, M. Ellefson, B. Mader, L. Zazzera, A. Simpson, D. Muradian, Jaimie Stomberg, U. Lagudu","doi":"10.1109/ASMC.2019.8791782","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791782","url":null,"abstract":"This work describes advanced metrology based on Single Particle Inductively Coupled Plasma Mass Spectrometry (sp- ICP-MS) used in chemical mechanical planarization (CMP) process development. sp-ICP-MS was used to measure concentrations and sizes of ceria nanoparticles before and after CMP of silicon dioxide. Changes in the particle size distribution show a shift to lower median particle size after polishing, and an increase in the number of smaller particles. This result is consistent with previous reports which showed significant in- process reduction of the average ceria particle size after polishing. These new results are important because they demonstrate the application of sp-ICP-MS in the development of advanced CMP processes.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133779977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791798
J. S. Kim, Je Hyeok Ryu, Chiyoung Lee, Y. Lee, Byoung Hoon Kim
Industrial interest in NOx emissions from dry strip process using O2/N2 downstream plasma has been significantly increased. In this article, we compared strip performances and NOx emissions for recipes with different total gas flow rate and nitrogen ratio. When total gas flow rate and nitrogen ratio are lowered, NOx emissions were reduced and strip performances, such as strip rate, within-wafer uniformity, wafer-to-wafer uniformity, were achieved. For both qualitative and quantitative analysis, an optical emission spectroscope on the chamber and a portable gas analyzer on the dry pump were used, respectively. The results of both analyzes were well matched to demonstrate NOx emissions from the various recipes. In conclusion, > 12.3 μ/min of strip rate, < 5.1% of within-wafer uniformity, 1.4% of wafer-to-wafer uniformity, and 3,414 of NOx emissions can be achieved from the newly proposed recipe.
{"title":"Novel Oxygen-based Dry Strip Process Reducing NOx Emissions During Photoresist Removal","authors":"J. S. Kim, Je Hyeok Ryu, Chiyoung Lee, Y. Lee, Byoung Hoon Kim","doi":"10.1109/ASMC.2019.8791798","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791798","url":null,"abstract":"Industrial interest in NOx emissions from dry strip process using O2/N2 downstream plasma has been significantly increased. In this article, we compared strip performances and NOx emissions for recipes with different total gas flow rate and nitrogen ratio. When total gas flow rate and nitrogen ratio are lowered, NOx emissions were reduced and strip performances, such as strip rate, within-wafer uniformity, wafer-to-wafer uniformity, were achieved. For both qualitative and quantitative analysis, an optical emission spectroscope on the chamber and a portable gas analyzer on the dry pump were used, respectively. The results of both analyzes were well matched to demonstrate NOx emissions from the various recipes. In conclusion, > 12.3 μ/min of strip rate, < 5.1% of within-wafer uniformity, 1.4% of wafer-to-wafer uniformity, and 3,414 of NOx emissions can be achieved from the newly proposed recipe.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132479435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791805
Sanghyun Lee, Ankit Jain, M. Plihal, S. Paramasivam, Tai-Kam Ng, Erfan Soltanmohammadi, Ian Tolle, D. Salvador
Broadband plasma (BBP) optical defect inspection systems are widely used for process monitoring. The outputs of inspection include the defects of interest (DOI) for that process step. It is important to not only detect the DOI, but also to separate them from other types of defects that are non- relevant to the process itself, i.e., nuisance defects. The process of separating DOI from nuisance is called nuisance filtering [1], [2]. Typical nuisance filtering algorithms used on BBP systems are user-created decision trees leveraging defect attributes assigned during inspection. As design nodes shrink and pattern density increases, nuisance filtering is becoming more difficult, leading to increased recipe setup time. Further, due to the increased complexity of the decision trees, user to user variation can affect inspection performance. To solve this problem, an innovative nuisance filtering algorithm is required. The key elements for such an algorithm are consistency and improved performance compared to user-created decision trees. This paper compares traditional decision trees as well as novel machine learning approaches for nuisance filtering in inline defect inspection tools, named inLine Defect Organizer™ 2.0 (iDO™ 2.0). The study achieved improvements in increased DOI capture rate, reduced nuisance defects and faster recipe setup time.
{"title":"Machine Learning Approaches for Nuisance filtering in Inline Defect Inspection","authors":"Sanghyun Lee, Ankit Jain, M. Plihal, S. Paramasivam, Tai-Kam Ng, Erfan Soltanmohammadi, Ian Tolle, D. Salvador","doi":"10.1109/ASMC.2019.8791805","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791805","url":null,"abstract":"Broadband plasma (BBP) optical defect inspection systems are widely used for process monitoring. The outputs of inspection include the defects of interest (DOI) for that process step. It is important to not only detect the DOI, but also to separate them from other types of defects that are non- relevant to the process itself, i.e., nuisance defects. The process of separating DOI from nuisance is called nuisance filtering [1], [2]. Typical nuisance filtering algorithms used on BBP systems are user-created decision trees leveraging defect attributes assigned during inspection. As design nodes shrink and pattern density increases, nuisance filtering is becoming more difficult, leading to increased recipe setup time. Further, due to the increased complexity of the decision trees, user to user variation can affect inspection performance. To solve this problem, an innovative nuisance filtering algorithm is required. The key elements for such an algorithm are consistency and improved performance compared to user-created decision trees. This paper compares traditional decision trees as well as novel machine learning approaches for nuisance filtering in inline defect inspection tools, named inLine Defect Organizer™ 2.0 (iDO™ 2.0). The study achieved improvements in increased DOI capture rate, reduced nuisance defects and faster recipe setup time.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"94 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133454165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791827
K. Joseph, Samail Deyline, Mohd Faudzi Masturah
Defect density in wafer fabrication can be a significant source of yield loss and reliability risk especially as device feature size shrinks. Thus to identify the root cause of the defect and eliminate them effectively is very crucial. The mechanism of a defect density called polysilicon residues and the key processes that affect this defect are studied in the paper. This defect of interest was generated due to watermark formation on the hydrophobic polysilicon surface, the silicate precipitate from the watermark acts as an unwanted masking layer causing block etch to the subsequent polysilicon etch resulted in poly silicon residues. The watermark was found after the de-ionized water rinse step. Avoiding the wafer to be exposed to ambient air after the water rinse has been adopted as key solution to prevent the watermark formation and hence eliminating the polysilicon residues.
{"title":"Elimination of PolySilicon Residues Formation Induced by Watermark on Hydrophobic Surface","authors":"K. Joseph, Samail Deyline, Mohd Faudzi Masturah","doi":"10.1109/ASMC.2019.8791827","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791827","url":null,"abstract":"Defect density in wafer fabrication can be a significant source of yield loss and reliability risk especially as device feature size shrinks. Thus to identify the root cause of the defect and eliminate them effectively is very crucial. The mechanism of a defect density called polysilicon residues and the key processes that affect this defect are studied in the paper. This defect of interest was generated due to watermark formation on the hydrophobic polysilicon surface, the silicate precipitate from the watermark acts as an unwanted masking layer causing block etch to the subsequent polysilicon etch resulted in poly silicon residues. The watermark was found after the de-ionized water rinse step. Avoiding the wafer to be exposed to ambient air after the water rinse has been adopted as key solution to prevent the watermark formation and hence eliminating the polysilicon residues.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122501599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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