Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791770
Yao-An Chung, Chien-Cheng Lung, Yuan-Chieh Chiu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
The abnormal process issue, arcing, was met in recipe development of high aspect ratio (HAR) trench etching. The arcing mechanism is proposed by continuous growth of polymer upon hard-mask along pattern boundary during deep trench etching. It leads to excess charge trapped and high potential difference between polymer and substrate. Eventually, electrical field breakdown occurs and results in severe pattern damage. The arcing risk can be effectively monitored in advance by measuring the polymer thickness on bare-Si wafer. A critical thickness of polymer is observed because we seldom find out the occurrence of arcing on the wafer while the polymer thickness is less than 960nm. Low pressure, inert gas dilution and high ESC temperature provide the knobs to control the polymer thickness less than 960nm –the critical thickness, as well achieving acceptable vertical trench profile in HAR etching.
{"title":"Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching","authors":"Yao-An Chung, Chien-Cheng Lung, Yuan-Chieh Chiu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/ASMC.2019.8791770","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791770","url":null,"abstract":"The abnormal process issue, arcing, was met in recipe development of high aspect ratio (HAR) trench etching. The arcing mechanism is proposed by continuous growth of polymer upon hard-mask along pattern boundary during deep trench etching. It leads to excess charge trapped and high potential difference between polymer and substrate. Eventually, electrical field breakdown occurs and results in severe pattern damage. The arcing risk can be effectively monitored in advance by measuring the polymer thickness on bare-Si wafer. A critical thickness of polymer is observed because we seldom find out the occurrence of arcing on the wafer while the polymer thickness is less than 960nm. Low pressure, inert gas dilution and high ESC temperature provide the knobs to control the polymer thickness less than 960nm –the critical thickness, as well achieving acceptable vertical trench profile in HAR etching.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133528891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791795
Adam Chalupa, Eric Ritschdorff
We demonstrate the application of high-speed video analysis to Wet Etch and Cleans process and equipment improvements in a high-volume semiconductor manufacturing environment. Through high-temporal-resolution video usage, a method of analysis was developed for systematic defect reduction, yield improvement, and cost reduction efforts. Three case studies are presented showing utility of high-speed video analysis that led to defect origin isolation from faulty equipment, chemical usage reduction saving almost 30% in costs per year, and high-speed capture to analyze flow-controller dependent flow stabilizations.
{"title":"Using High-Speed Video Analysis for Defect Investigation and Process Improvement","authors":"Adam Chalupa, Eric Ritschdorff","doi":"10.1109/ASMC.2019.8791795","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791795","url":null,"abstract":"We demonstrate the application of high-speed video analysis to Wet Etch and Cleans process and equipment improvements in a high-volume semiconductor manufacturing environment. Through high-temporal-resolution video usage, a method of analysis was developed for systematic defect reduction, yield improvement, and cost reduction efforts. Three case studies are presented showing utility of high-speed video analysis that led to defect origin isolation from faulty equipment, chemical usage reduction saving almost 30% in costs per year, and high-speed capture to analyze flow-controller dependent flow stabilizations.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"97 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791778
Wen Bin Low, James Lai, Liang Chun Sung
40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.
{"title":"40nm Donut Scan Failed Induced by Active Drain/Source Stress Issue","authors":"Wen Bin Low, James Lai, Liang Chun Sung","doi":"10.1109/ASMC.2019.8791778","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791778","url":null,"abstract":"40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115672191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791774
Vikram Arjunwadkar, Nivedha Rajasekaran
For a semiconductor wafer fabrication factory, availability of equipment is a key fab performance metric for the periodic assessment of fab capacity. The current capacity model assumes an average of weekly actual availability for the equipment groups to evaluate the throughput of the equipment group for a given timeframe. This does not capture the cases of equipment groups that will have degradation in availability as they see more Work in Progress (WIP) coming through. This study proposes a new mathematical model to determine the availability of the equipment groups to be used in the capacity model based on the actual in-line utilization of the equipment group.
{"title":"Capturing Tool Availability in the Capacity Model based on Actual Utilization","authors":"Vikram Arjunwadkar, Nivedha Rajasekaran","doi":"10.1109/ASMC.2019.8791774","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791774","url":null,"abstract":"For a semiconductor wafer fabrication factory, availability of equipment is a key fab performance metric for the periodic assessment of fab capacity. The current capacity model assumes an average of weekly actual availability for the equipment groups to evaluate the throughput of the equipment group for a given timeframe. This does not capture the cases of equipment groups that will have degradation in availability as they see more Work in Progress (WIP) coming through. This study proposes a new mathematical model to determine the availability of the equipment groups to be used in the capacity model based on the actual in-line utilization of the equipment group.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124459607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791806
A. Chakraborty, Joshua T. Cook, R. Gipson
The design of high-performance gas filtration and purification products utilizing adsorption must account for the sensitivity of adsorption phenomena to the wide variety of process conditions and parameters which is difficult to know in advance for a particular design. Although building physical prototypes and performing physical testing can be done, it is usually at the expense of time-to-market, reduced number of design alternatives, the absence of true optimization, and financial cost. Therefore, there remains a standing need to develop a suitable parametric optimization tool to capture the effects of related process parameters on purifier performance. Virtual prototyping of gas purification products using Computational Fluid Dynamics (CFD) can complement that by simulating the required physics involved (fluid flow, heat and mass transfer, chemical kinetics, and thermodynamics). To this end, recent efforts demonstrated a novel modeling technique to predict and optimize chemical performances in gas purifiers under a wide range of process parameters. The optimization model is based on three different gas-solid adsorption systems (toluene/activated carbon, moisture/zeolite and CO2/zeolite). The models were first validated with experimental data which were then applied to optimize purifier performance. Based on the modeling data, a set of mathematical correlations was developed that can predict the effects of process parameters on adsorption performance. Using these correlations, a simplified optimization calculator was provided which effectively predicts the parametric effects on purifier performance without performing lengthy experiments or requiring designers to learn CFD.
{"title":"Parametric Optimization of Gas Purifiers: A Computational Fluid Dynamics (CFD) Modeling Approach","authors":"A. Chakraborty, Joshua T. Cook, R. Gipson","doi":"10.1109/ASMC.2019.8791806","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791806","url":null,"abstract":"The design of high-performance gas filtration and purification products utilizing adsorption must account for the sensitivity of adsorption phenomena to the wide variety of process conditions and parameters which is difficult to know in advance for a particular design. Although building physical prototypes and performing physical testing can be done, it is usually at the expense of time-to-market, reduced number of design alternatives, the absence of true optimization, and financial cost. Therefore, there remains a standing need to develop a suitable parametric optimization tool to capture the effects of related process parameters on purifier performance. Virtual prototyping of gas purification products using Computational Fluid Dynamics (CFD) can complement that by simulating the required physics involved (fluid flow, heat and mass transfer, chemical kinetics, and thermodynamics). To this end, recent efforts demonstrated a novel modeling technique to predict and optimize chemical performances in gas purifiers under a wide range of process parameters. The optimization model is based on three different gas-solid adsorption systems (toluene/activated carbon, moisture/zeolite and CO2/zeolite). The models were first validated with experimental data which were then applied to optimize purifier performance. Based on the modeling data, a set of mathematical correlations was developed that can predict the effects of process parameters on adsorption performance. Using these correlations, a simplified optimization calculator was provided which effectively predicts the parametric effects on purifier performance without performing lengthy experiments or requiring designers to learn CFD.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125215711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791824
Gregory M. Johnson, Baohua Niu, T. Lundquist, A. Rummel, M. Kemmler
Probing is increasingly utilized as a technique for the characterization of the local electrical properties of an integrated circuit, as well as the isolation of defects. Test structures and/or SRAM arrays were examined with the various probing modes available with a probing system. Test structures were examined using Electron Beam Absorbed Current (EBAC), Resistive Contrast Imaging (RCI), Electron Beam Induced Current, (EBIC), and EBIRCH (Electron Beam Induced Resistance CHange). The results demonstrate the utility of using each in an SRAM yield management scenario. EBAC is able to provide information about basic connectivity. RCI allows for the isolation of resistive spots along a conductor. EBIC provides for the imaging of depletion zones between PW and NW, even in a planar view. EBIRCH, being driven by two different mechanisms (thermal coefficient of resistivity and Seebeck effect) is able to provide two different kinds of analyses, depending on the conditions. EBIRCH precisely isolated which of a few fins in a multi-fin device are responsible for a short and showed the thermal relations between the elements of a pulldown device in an SRAM. The techniques together provide multiple forms of process feedback when used as part of an integrated yield management program involving analysis of via chains, SRAM parallel array test structures, and SRAMs.
{"title":"Distinguishing between electron-beam signals in probing of SRAM modules for yield management","authors":"Gregory M. Johnson, Baohua Niu, T. Lundquist, A. Rummel, M. Kemmler","doi":"10.1109/ASMC.2019.8791824","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791824","url":null,"abstract":"Probing is increasingly utilized as a technique for the characterization of the local electrical properties of an integrated circuit, as well as the isolation of defects. Test structures and/or SRAM arrays were examined with the various probing modes available with a probing system. Test structures were examined using Electron Beam Absorbed Current (EBAC), Resistive Contrast Imaging (RCI), Electron Beam Induced Current, (EBIC), and EBIRCH (Electron Beam Induced Resistance CHange). The results demonstrate the utility of using each in an SRAM yield management scenario. EBAC is able to provide information about basic connectivity. RCI allows for the isolation of resistive spots along a conductor. EBIC provides for the imaging of depletion zones between PW and NW, even in a planar view. EBIRCH, being driven by two different mechanisms (thermal coefficient of resistivity and Seebeck effect) is able to provide two different kinds of analyses, depending on the conditions. EBIRCH precisely isolated which of a few fins in a multi-fin device are responsible for a short and showed the thermal relations between the elements of a pulldown device in an SRAM. The techniques together provide multiple forms of process feedback when used as part of an integrated yield management program involving analysis of via chains, SRAM parallel array test structures, and SRAMs.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122993082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791751
J. G. Sheridan, Hsiao-Chi Peng, C. Huang, V. Aristov, Hoang Nguyen, Y. Khopkar, Abhinav Jain, Jay K Shah, F. Levitov
Photomask issues can result in shifted pattern defects printed on the wafer. In the case of sub-1x nm nodes, these pattern defects of interest (DOI) can be difficult for conventional optical inspections to detect. In this paper we present a case study of a new mask qualification for a MOL gate open (GO) contact mask layer. The new mask was introduced to compensate for a known open between trench silicide (TS) contact and GO. During qualification, a shift in the GO overlay was seen on one section of the wafer and suspected to be the cause of a TS-gate short. A Design of Experiments (DOE) was created to investigate if the issue was solely mask related or if it could be mitigated during processing (litho/etch). Physical mode e-beam inspection was used to monitor the DOE wafers, however the resolution of the e-beam inspection tool was not sufficient to conclusively classify the defects observed. A high resolution, high landing energy SEM defect review was introduced post e-beam inspection to better monitor the splits running as part of the DOE.
{"title":"Mask qualification of a shifted gate contact issue by physical e-beam inspection and high landing energy SEM review : DI: Defect Inspection and Reduction","authors":"J. G. Sheridan, Hsiao-Chi Peng, C. Huang, V. Aristov, Hoang Nguyen, Y. Khopkar, Abhinav Jain, Jay K Shah, F. Levitov","doi":"10.1109/ASMC.2019.8791751","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791751","url":null,"abstract":"Photomask issues can result in shifted pattern defects printed on the wafer. In the case of sub-1x nm nodes, these pattern defects of interest (DOI) can be difficult for conventional optical inspections to detect. In this paper we present a case study of a new mask qualification for a MOL gate open (GO) contact mask layer. The new mask was introduced to compensate for a known open between trench silicide (TS) contact and GO. During qualification, a shift in the GO overlay was seen on one section of the wafer and suspected to be the cause of a TS-gate short. A Design of Experiments (DOE) was created to investigate if the issue was solely mask related or if it could be mitigated during processing (litho/etch). Physical mode e-beam inspection was used to monitor the DOE wafers, however the resolution of the e-beam inspection tool was not sufficient to conclusively classify the defects observed. A high resolution, high landing energy SEM defect review was introduced post e-beam inspection to better monitor the splits running as part of the DOE.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791781
M. Murugesan, T. Fukushima, M. Koyanagi
A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.
{"title":"500 nm-sized Ni-TSVwith Aspect Ratio 20 for Future 3D-LSIs_A Low-Cost Electroless-Ni Plating Approach","authors":"M. Murugesan, T. Fukushima, M. Koyanagi","doi":"10.1109/ASMC.2019.8791781","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791781","url":null,"abstract":"A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"16 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791785
Weihong Gao, JeongHee Kim, Hsiao-Chi Peng, C. Huang, O. Patterson, yu-chi Su, Hsiang-Ting Yeh, Sean Starr-baier, Haokun Hu
A methodology for rapid process window characterization using families of voltage contrast (VC) test structures is described. While VC test structures have been in common use in the semiconductor industry for targeted applications for twenty years, we propose comprehensive application of VC test structures as a powerful tool for greatly accelerating semiconductor technology development. Test chips may be developed covering essentially all possible failure mechanisms. These chips include families of structures for monitoring both the critical process windows and the nominal failure rate. These structures are inspected in-line thereby providing the earliest possible feedback for split experiment evaluation, yield projection, and excursion detection. This paper reports on the application of this methodology to an advanced FinFET technology. Best methods for test structure layout, inspection setup, and binning strategy and reporting are described. Selected test structure designs and results are presented to illustrate these principles.
{"title":"Rapid In-line Process Window Characterization Using Voltage Contrast Test Structures for Advanced FinFET Technology Development","authors":"Weihong Gao, JeongHee Kim, Hsiao-Chi Peng, C. Huang, O. Patterson, yu-chi Su, Hsiang-Ting Yeh, Sean Starr-baier, Haokun Hu","doi":"10.1109/ASMC.2019.8791785","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791785","url":null,"abstract":"A methodology for rapid process window characterization using families of voltage contrast (VC) test structures is described. While VC test structures have been in common use in the semiconductor industry for targeted applications for twenty years, we propose comprehensive application of VC test structures as a powerful tool for greatly accelerating semiconductor technology development. Test chips may be developed covering essentially all possible failure mechanisms. These chips include families of structures for monitoring both the critical process windows and the nominal failure rate. These structures are inspected in-line thereby providing the earliest possible feedback for split experiment evaluation, yield projection, and excursion detection. This paper reports on the application of this methodology to an advanced FinFET technology. Best methods for test structure layout, inspection setup, and binning strategy and reporting are described. Selected test structure designs and results are presented to illustrate these principles.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"493 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114016163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791801
S. Matham, C. Durfee, B. Mendoza, D. Sadana, S. Bedell, J. Gaudiello, S. Teehan, Heungsoo Choi, Ankit Jain, M. Plihal
Historically, haze metrology on KLA-Tencor Surfscan® unpatterned wafer inspection systems is the preferred inline non-destructive method for ascertaining crystal quality of epitaxial deposited films. However, this metrology is limited to unpatterned blanket wafers. This paper describes a non- destructive inline optical methodology for measuring epitaxial quality of both blanket and patterned wafers using a novel fast turnaround machine learning method that can be applied to patterned and unpatterned substrates by utilizing the background noise obtained during broadband plasma optical defect inspection. This machine learning method is an innovative nuisance filtering algorithm used in inline defect inspection tools, named iDO™ 2.0 (inLine Defect Organizer™). The study showed a promising machine learning approach that repeatably measures low and high defect densities which are consistent with Secco etch data.
{"title":"High-throughput, nondestructive assessment of defects in patterned epitaxial films on silicon by machine learning-enabled broadband plasma optical measurements","authors":"S. Matham, C. Durfee, B. Mendoza, D. Sadana, S. Bedell, J. Gaudiello, S. Teehan, Heungsoo Choi, Ankit Jain, M. Plihal","doi":"10.1109/ASMC.2019.8791801","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791801","url":null,"abstract":"Historically, haze metrology on KLA-Tencor Surfscan® unpatterned wafer inspection systems is the preferred inline non-destructive method for ascertaining crystal quality of epitaxial deposited films. However, this metrology is limited to unpatterned blanket wafers. This paper describes a non- destructive inline optical methodology for measuring epitaxial quality of both blanket and patterned wafers using a novel fast turnaround machine learning method that can be applied to patterned and unpatterned substrates by utilizing the background noise obtained during broadband plasma optical defect inspection. This machine learning method is an innovative nuisance filtering algorithm used in inline defect inspection tools, named iDO™ 2.0 (inLine Defect Organizer™). The study showed a promising machine learning approach that repeatably measures low and high defect densities which are consistent with Secco etch data.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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