Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791773
R. van Roijen, Bryan N. Rhoads, A. Friedman, Aurelia Suwarno-Handayana, J. Ayala, Oh-jung Kwon, Michael Carbonell
We provide two examples of defects that caused real yield degradation on wafers, where the defects were not created during processing of the wafers. One is a case of a common non-process step unexpectedly causing a defect. The second is related to queue time, and shows that even in a modern highly controlled environment not all risks are always fully accounted for. We describe the mechanism behind the defects and provide specific solutions to the issues found. We also comment on the conditions that are most likely to make wafers susceptible to these defects and some guidelines that follow from these observations.
{"title":"Defects caused by Sources other than Processing","authors":"R. van Roijen, Bryan N. Rhoads, A. Friedman, Aurelia Suwarno-Handayana, J. Ayala, Oh-jung Kwon, Michael Carbonell","doi":"10.1109/ASMC.2019.8791773","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791773","url":null,"abstract":"We provide two examples of defects that caused real yield degradation on wafers, where the defects were not created during processing of the wafers. One is a case of a common non-process step unexpectedly causing a defect. The second is related to queue time, and shows that even in a modern highly controlled environment not all risks are always fully accounted for. We describe the mechanism behind the defects and provide specific solutions to the issues found. We also comment on the conditions that are most likely to make wafers susceptible to these defects and some guidelines that follow from these observations.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127692159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791776
F. Ujhelyi, A. Pongrácz, Á. Kun, J. Szívós, B. Bartal, B. Fodor, A. Bölcskei-Molnár, G. Nadudvari, J. Byrnes, L. Rubin
Photo-modulated Reflectivity Measurement (PMR) is an excellent technology for ion implantation dose and tilt angle monitoring of as-implanted pre-annealed production wafers. The SEMILAB PMR-3000 is a unit for in-line monitoring of ion implantation prior to the thermal annealing process step. The enhanced optical system ensures accurate measurement over the whole dose range without insensitive regions in the mid-dose range. Typical dose detectability is <0.5% (1 σ). The resolution of tilt angle detection can reach 0.1° (1 σ). This sensitivity to tilt angle fulfills the requirements of state of the art process control requirements.
{"title":"Mid-low energy implantation tilt angle monitoring with photomodulated reflectance measurement","authors":"F. Ujhelyi, A. Pongrácz, Á. Kun, J. Szívós, B. Bartal, B. Fodor, A. Bölcskei-Molnár, G. Nadudvari, J. Byrnes, L. Rubin","doi":"10.1109/ASMC.2019.8791776","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791776","url":null,"abstract":"Photo-modulated Reflectivity Measurement (PMR) is an excellent technology for ion implantation dose and tilt angle monitoring of as-implanted pre-annealed production wafers. The SEMILAB PMR-3000 is a unit for in-line monitoring of ion implantation prior to the thermal annealing process step. The enhanced optical system ensures accurate measurement over the whole dose range without insensitive regions in the mid-dose range. Typical dose detectability is <0.5% (1 σ). The resolution of tilt angle detection can reach 0.1° (1 σ). This sensitivity to tilt angle fulfills the requirements of state of the art process control requirements.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791794
J. Jeong, Jinwoo Park, Eunyoung Han, Jaungjoo Kim, Hong Kim
In this paper, a study on a behavior of waiting-time related defect which strongly depends on a wafer slot position in FOUP (Front Opening Unified Pod) was carried out. The occurrence of the waiting-time dependent defects in the processing tools was found to be affected by the flow pattern, moisture and process outgassing distribution in equipment EFEM (Equipment Front End Module) and FOUP. In order to control this problem, which also causes to deteriorate the production yield, it is essential to establish a system that is capable of monitoring the wafer-level waiting- time of each wafer in the processing tools. Optimizing the flow pattern of air which contains humidity and process outgassing or AMC (Airborne Molecular Contaminants), and N2 purge gas in EFEM and FOUP is required as well. Various types of load-port N2 gas purging system inside EFEM and FOUP were reviewed using CFD (Computational Fluid Dynamics) simulations and a fully charged N2 circulating EFEM exhibited the best defect control performance.
{"title":"Control of Wafer Slot-Dependent Outgassing Defects during Semiconductor Manufacture Processes","authors":"J. Jeong, Jinwoo Park, Eunyoung Han, Jaungjoo Kim, Hong Kim","doi":"10.1109/ASMC.2019.8791794","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791794","url":null,"abstract":"In this paper, a study on a behavior of waiting-time related defect which strongly depends on a wafer slot position in FOUP (Front Opening Unified Pod) was carried out. The occurrence of the waiting-time dependent defects in the processing tools was found to be affected by the flow pattern, moisture and process outgassing distribution in equipment EFEM (Equipment Front End Module) and FOUP. In order to control this problem, which also causes to deteriorate the production yield, it is essential to establish a system that is capable of monitoring the wafer-level waiting- time of each wafer in the processing tools. Optimizing the flow pattern of air which contains humidity and process outgassing or AMC (Airborne Molecular Contaminants), and N2 purge gas in EFEM and FOUP is required as well. Various types of load-port N2 gas purging system inside EFEM and FOUP were reviewed using CFD (Computational Fluid Dynamics) simulations and a fully charged N2 circulating EFEM exhibited the best defect control performance.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130389712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791815
Yuan-Fu Yang
The semiconductors are used as various precision components in many electronic products. Each layer must be inspected of defect after drawing and baking the mask pattern in wafer fabrication. Unfortunately, the defects come from various variations during the semiconductor manufacturing and cause massive losses to the companies' yield. If the defects could be identified and classified correctly, then the root of the fabrication problem can be recognized and eventually resolved.Automatic optical inspection (AOI) is used to visualize defect patterns and identify root causes of die failures. AOI can be replaced a large number of human inspections with high-speed and accurate inspection technology, to achieve consistency in the detection and shorten the inspection time, then improve product quality and competitiveness. The defect is judged from the feature in AOI, but the final goal is to determine if the defect is a true or a pseudo defect of the wafer. Then, we need to determine what defect type is. But the current AOI needs a subsequent final verification by the human to judge the type of defect.Machine learning (ML) techniques have been widely accepted and are well suited for such classification and identification problems. In this paper, we employ convolutional neural networks (CNN) and extreme gradient boosting (XGBoost) for wafer map retrieval tasks and the defect pattern classification. CNN is the most famous deep learning architecture. The recent surge of interest in CNN is due to the immense popularity and effectiveness of convnets. XGBoost is the most popular machine learning framework among data science practitioners, especially on Kaggle, which is a platform for data prediction competitions where researchers post their data and statisticians and data miners compete to produce the best models. CNN and XGBoost are compared with a random decision forests (RF), support vector machine (SVM), adaptive boosting (Adaboost), and the final results indicate a superior classification performance of the proposed method.Our experimental result demonstrates the success of CNN and extreme gradient boosting techniques for the identification of defect patterns in semiconductor wafers. The overall classification accuracy for the test dataset of CNN and extreme gradient boosting is 99.2%/98.1%. We demonstrate the success of this technique for the identification of defect patterns in semiconductor wafers. We believe this is the first time accurate computational classification in such task has been reported achieving accuracy above 99%.
{"title":"A Deep Learning Model for Identification of Defect Patterns in Semiconductor Wafer Map","authors":"Yuan-Fu Yang","doi":"10.1109/ASMC.2019.8791815","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791815","url":null,"abstract":"The semiconductors are used as various precision components in many electronic products. Each layer must be inspected of defect after drawing and baking the mask pattern in wafer fabrication. Unfortunately, the defects come from various variations during the semiconductor manufacturing and cause massive losses to the companies' yield. If the defects could be identified and classified correctly, then the root of the fabrication problem can be recognized and eventually resolved.Automatic optical inspection (AOI) is used to visualize defect patterns and identify root causes of die failures. AOI can be replaced a large number of human inspections with high-speed and accurate inspection technology, to achieve consistency in the detection and shorten the inspection time, then improve product quality and competitiveness. The defect is judged from the feature in AOI, but the final goal is to determine if the defect is a true or a pseudo defect of the wafer. Then, we need to determine what defect type is. But the current AOI needs a subsequent final verification by the human to judge the type of defect.Machine learning (ML) techniques have been widely accepted and are well suited for such classification and identification problems. In this paper, we employ convolutional neural networks (CNN) and extreme gradient boosting (XGBoost) for wafer map retrieval tasks and the defect pattern classification. CNN is the most famous deep learning architecture. The recent surge of interest in CNN is due to the immense popularity and effectiveness of convnets. XGBoost is the most popular machine learning framework among data science practitioners, especially on Kaggle, which is a platform for data prediction competitions where researchers post their data and statisticians and data miners compete to produce the best models. CNN and XGBoost are compared with a random decision forests (RF), support vector machine (SVM), adaptive boosting (Adaboost), and the final results indicate a superior classification performance of the proposed method.Our experimental result demonstrates the success of CNN and extreme gradient boosting techniques for the identification of defect patterns in semiconductor wafers. The overall classification accuracy for the test dataset of CNN and extreme gradient boosting is 99.2%/98.1%. We demonstrate the success of this technique for the identification of defect patterns in semiconductor wafers. We believe this is the first time accurate computational classification in such task has been reported achieving accuracy above 99%.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116539057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Foundry FAB manufactures a variety of semiconductor products with adverse mixture of process flows. For process control, it is a challenge to define some critical dimension measurement items target of each unique product characteristic before new tape out (NTO). After some wafers pilot run completed, a proper measurement target was defined. The engineers have to waste valuable resources for measurement retargeting and expense extra process time to validate these changes satisfied.As we know, the mask layout pattern density (PD) has highly correlated with measurement target. However, traditional regression model results can not satisfy advanced processes requirements. In this study, we proposed new factors, including local pattern density, line density and traditional global pattern density (GPD) into model. Furthermore, the regression model was refined with machine learning, k-NN (k-th Near Neighbor), to enhance the prediction accuracy for NTO measurement target. The simulation result showed average prediction accuracy come up to 85% above, compared with previous 61% only. Even some layers accuracy achieved 95% above.
代工FAB制造各种半导体产品与不利的混合工艺流程。对于过程控制来说，在新带出之前确定一些关键的尺寸测量项目是一个挑战。在完成一些晶圆试制后，确定了合适的测量目标。工程师不得不浪费宝贵的资源用于测量重新定位，并花费额外的过程时间来验证这些更改是否得到满足。众所周知，掩模布局模式密度(PD)与测量目标高度相关。然而，传统的回归模型结果已不能满足先进工艺的要求。本文在模型中引入了局部格局密度、线密度和传统的全局格局密度(GPD)等因子。在此基础上，利用机器学习k-NN (k-th Near Neighbor)对回归模型进行了改进，提高了对NTO测量目标的预测精度。仿真结果表明，平均预测精度达到85%以上，而以往的预测精度仅为61%。甚至有些层的准确率达到95%以上。
{"title":"The study on critical dimension target prediction for etch process : IE: Industrial Engineering","authors":"Chien-Cheng Wang, Kai-Ting Tseng, Chia-Jui Chuang, Richard, S.J. Chen, Yu-Hang Piao","doi":"10.1109/ASMC.2019.8791783","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791783","url":null,"abstract":"Foundry FAB manufactures a variety of semiconductor products with adverse mixture of process flows. For process control, it is a challenge to define some critical dimension measurement items target of each unique product characteristic before new tape out (NTO). After some wafers pilot run completed, a proper measurement target was defined. The engineers have to waste valuable resources for measurement retargeting and expense extra process time to validate these changes satisfied.As we know, the mask layout pattern density (PD) has highly correlated with measurement target. However, traditional regression model results can not satisfy advanced processes requirements. In this study, we proposed new factors, including local pattern density, line density and traditional global pattern density (GPD) into model. Furthermore, the regression model was refined with machine learning, k-NN (k-th Near Neighbor), to enhance the prediction accuracy for NTO measurement target. The simulation result showed average prediction accuracy come up to 85% above, compared with previous 61% only. Even some layers accuracy achieved 95% above.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134613265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791818
K. Hui, Leo Ke, S. Sheen
Typical solutions of Advanced Process Controls in semiconductor manufacturing are focused on the eliminations of target offsets for the process results of some device features. Normally the process models are square and of full ranks, thus enabling unique determinations of the adjustments of control inputs. As complexity of semiconductor devices evolves from planar to 3D structures, elementary controls of simple target offsets are no longer sufficient as concurrent controls of both target and uniformity have become essential. For the latter it may refer to within-wafer uniformity for variations of the same device feature over the entire wafer surface; or it may refer to the in-situ profiles of different features at the same spot. In either case, they result in largely underdetermined systems as the number of control inputs is finite and fewer than the possible number of all control outputs. Conventional APC solutions in semiconductor manufacturing are incapable of handling these situations. This paper presents an approach using multivariate optimal control techniques to achieve the desired performances.
{"title":"Advanced Process Controls of Underdetermined Systems of Feature Profiles in Semiconductor Manufacturing","authors":"K. Hui, Leo Ke, S. Sheen","doi":"10.1109/ASMC.2019.8791818","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791818","url":null,"abstract":"Typical solutions of Advanced Process Controls in semiconductor manufacturing are focused on the eliminations of target offsets for the process results of some device features. Normally the process models are square and of full ranks, thus enabling unique determinations of the adjustments of control inputs. As complexity of semiconductor devices evolves from planar to 3D structures, elementary controls of simple target offsets are no longer sufficient as concurrent controls of both target and uniformity have become essential. For the latter it may refer to within-wafer uniformity for variations of the same device feature over the entire wafer surface; or it may refer to the in-situ profiles of different features at the same spot. In either case, they result in largely underdetermined systems as the number of control inputs is finite and fewer than the possible number of all control outputs. Conventional APC solutions in semiconductor manufacturing are incapable of handling these situations. This paper presents an approach using multivariate optimal control techniques to achieve the desired performances.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130767454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791750
Yong-Yi Lin, F. Tsai, L. Hsu, H. Hsu, Chih-Yueh Li, Yu-Yuan Ke, Chih-Wei Huang, Jun- Ming Chen, Shao-Ju Chang, Tung-Ying Lee, E. Chen, Chao-Yu Cheng
Chemical mechanical planarization (CMP) has become one of the most critical processes in advanced integrated circuit manufacturing. The CMP process involves a complex physical and chemical reaction for film thickness removal and surface roughness improvement. The control of defects associated with CMP processes is critical to avoiding yield loss. As device critical dimensions keep shrinking, CMP defect control limits are getting stricter than in the past. In addition to controlling the total defect count, individual defect type counts also need to be controlled. In this paper, an automated defect classification algorithm, inLine Defect Organizer (iDO™), is used in conjunction with laser scattering inspection technology to classify scratch, ring pit and particle/residue defects generated by CMP processes with different shapes (concave, concave-convex mixed, and convex) on unpatterned monitor wafers. Using iDO, an extremely high value for the purity (>80%) of the classified defects can be achieved, enabling tracking of the variation in individual defect counts with different CMP process flows. This method can also be applied for inline monitoring to shorten the partition time of excursion wafers by 40% without scanning electron microscope (SEM) defect review. Furthermore, engineers can also easily investigate the defect formation mechanism based on the classified results. In this paper, the defect formation mechanism of scratch, ring pit and particle/residue defect types are discussed and proved by an iDO result. It is proven to be helpful for the CMP process optimization to minimize the killer defects.
{"title":"Fast and accurate defect classification for CMP process monitoring","authors":"Yong-Yi Lin, F. Tsai, L. Hsu, H. Hsu, Chih-Yueh Li, Yu-Yuan Ke, Chih-Wei Huang, Jun- Ming Chen, Shao-Ju Chang, Tung-Ying Lee, E. Chen, Chao-Yu Cheng","doi":"10.1109/ASMC.2019.8791750","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791750","url":null,"abstract":"Chemical mechanical planarization (CMP) has become one of the most critical processes in advanced integrated circuit manufacturing. The CMP process involves a complex physical and chemical reaction for film thickness removal and surface roughness improvement. The control of defects associated with CMP processes is critical to avoiding yield loss. As device critical dimensions keep shrinking, CMP defect control limits are getting stricter than in the past. In addition to controlling the total defect count, individual defect type counts also need to be controlled. In this paper, an automated defect classification algorithm, inLine Defect Organizer (iDO™), is used in conjunction with laser scattering inspection technology to classify scratch, ring pit and particle/residue defects generated by CMP processes with different shapes (concave, concave-convex mixed, and convex) on unpatterned monitor wafers. Using iDO, an extremely high value for the purity (>80%) of the classified defects can be achieved, enabling tracking of the variation in individual defect counts with different CMP process flows. This method can also be applied for inline monitoring to shorten the partition time of excursion wafers by 40% without scanning electron microscope (SEM) defect review. Furthermore, engineers can also easily investigate the defect formation mechanism based on the classified results. In this paper, the defect formation mechanism of scratch, ring pit and particle/residue defect types are discussed and proved by an iDO result. It is proven to be helpful for the CMP process optimization to minimize the killer defects.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"254 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113992306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791790
É. Le Quéré, S. Dauzére-Pérés, S. Astie, Cédric Maufront, Xavier Michallet, G. Bugnon, Nicolas Ferrandini
Semiconductor manufacturing is complex and driven by a very strict market in terms of quality, which is ensured by performing many control operations on lots. To reduce the cost of quality, we present a simple algorithm that dynamically cancels lot measurements, i.e. skips lots, that do not bring enough information. The industrial impacts of the algorithm and its implementation in a cloud-based architecture are discussed.
{"title":"Dynamic cloud-based computation for skipping lots in metrology : IE : Industrial Engineering","authors":"É. Le Quéré, S. Dauzére-Pérés, S. Astie, Cédric Maufront, Xavier Michallet, G. Bugnon, Nicolas Ferrandini","doi":"10.1109/ASMC.2019.8791790","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791790","url":null,"abstract":"Semiconductor manufacturing is complex and driven by a very strict market in terms of quality, which is ensured by performing many control operations on lots. To reduce the cost of quality, we present a simple algorithm that dynamically cancels lot measurements, i.e. skips lots, that do not bring enough information. The industrial impacts of the algorithm and its implementation in a cloud-based architecture are discussed.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791817
B. Greenwood, J. Kimball, S. Sridaran, K. Truong, A. Lee, S. Menon, J. Gambino, L. Jastrzebski, G. Nadudvari, L. Roszol, M. Nagy, G. Molnár, Z. Kiss, A. Pongrácz, J. Byrnes
A key part of 180nm Bipolar-CMOS-DMOS (BCD) technology is the use of PNP bipolar devices with high beta. Macro and Micro Photoluminescence Imaging (MacroPL, μPL) uses excitation of charge carriers in semiconductor by high intensity illumination, followed by observation of photons at longer wavelength generated from radiative recombination; both band to band and defect to band emissions were used. Use of Micro Photoluminescence Imaging allows rapid characterization and corrective actions for dislocations and other defects which suppress PNP beta.
{"title":"Implant Optimization for a 180nm BCD Technology","authors":"B. Greenwood, J. Kimball, S. Sridaran, K. Truong, A. Lee, S. Menon, J. Gambino, L. Jastrzebski, G. Nadudvari, L. Roszol, M. Nagy, G. Molnár, Z. Kiss, A. Pongrácz, J. Byrnes","doi":"10.1109/ASMC.2019.8791817","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791817","url":null,"abstract":"A key part of 180nm Bipolar-CMOS-DMOS (BCD) technology is the use of PNP bipolar devices with high beta. Macro and Micro Photoluminescence Imaging (MacroPL, μPL) uses excitation of charge carriers in semiconductor by high intensity illumination, followed by observation of photons at longer wavelength generated from radiative recombination; both band to band and defect to band emissions were used. Use of Micro Photoluminescence Imaging allows rapid characterization and corrective actions for dislocations and other defects which suppress PNP beta.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791832
Venkatesh Deenadayalan, P. Thomas, S. Preble
Silicon photonics is revolutionizing computing, communication and sensing systems. As a result, there is a growing need to teach integrated photonic design, fabrication, testing and packaging principles. The focus of this paper is on an improved fabrication process for silicon waveguides that are compatible with most university cleanrooms (i-line photolithography) Furthermore, we establish a simple process for integrating metal heaters to realize thermo-optic tuning of silicon photonic circuits. The process optimization was performed by running extensive etch tests with PEVCD TEOS and carbon hard masks. PECVD TEOS was prone to erosion, while carbon proved more resilient and was chosen as the best hard mask material. The Photolithography was improved by adjusting the coating thickness of the BARC and resist layer. Etch resistance of the photoresist was improved by a simple curing process. The passive component fabrication is followed by addition of metal heater to thermally tune the waveguides. This optimized fabrication process is executed in a CMOS compatible academic fabrication facility with 365 nm i-line lithography. The bi-layer metal lift off process has Nichrome alloy as the heater metal because of this high electrical resistivity along with less resistive molybdenum for contacts.
{"title":"Fabrication of Silicon photonic circuits with integrated thermo-optic heaters for education","authors":"Venkatesh Deenadayalan, P. Thomas, S. Preble","doi":"10.1109/ASMC.2019.8791832","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791832","url":null,"abstract":"Silicon photonics is revolutionizing computing, communication and sensing systems. As a result, there is a growing need to teach integrated photonic design, fabrication, testing and packaging principles. The focus of this paper is on an improved fabrication process for silicon waveguides that are compatible with most university cleanrooms (i-line photolithography) Furthermore, we establish a simple process for integrating metal heaters to realize thermo-optic tuning of silicon photonic circuits. The process optimization was performed by running extensive etch tests with PEVCD TEOS and carbon hard masks. PECVD TEOS was prone to erosion, while carbon proved more resilient and was chosen as the best hard mask material. The Photolithography was improved by adjusting the coating thickness of the BARC and resist layer. Etch resistance of the photoresist was improved by a simple curing process. The passive component fabrication is followed by addition of metal heater to thermally tune the waveguides. This optimized fabrication process is executed in a CMOS compatible academic fabrication facility with 365 nm i-line lithography. The bi-layer metal lift off process has Nichrome alloy as the heater metal because of this high electrical resistivity along with less resistive molybdenum for contacts.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133727352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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