Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791786
R. Mitra, Zhiyong Xie
Wafers at end-of-line showed yield loss. Data Science helped to correlate to numerous clean tools/chambers at a particular step sequence in Front End of Line (FEOL). Various models and mechanisms were established. The investigation and experiments conducted are reported in this paper.
{"title":"A Case Study of Yield Improvement in a FEOL Wet Clean Process","authors":"R. Mitra, Zhiyong Xie","doi":"10.1109/ASMC.2019.8791786","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791786","url":null,"abstract":"Wafers at end-of-line showed yield loss. Data Science helped to correlate to numerous clean tools/chambers at a particular step sequence in Front End of Line (FEOL). Various models and mechanisms were established. The investigation and experiments conducted are reported in this paper.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791775
B. H. Wood, Allison Hsu, Bob Shie
It is well understood that large particles and agglomerates in CMP (chemical mechanical planarization) slurries can generate defects on wafer which can result in yield loss. To minimize defects caused by large particles/agglomerates many fabs filter the slurry in the sub-fab’s SDS (slurry delivery system). It is less common to employ filtration at the Point of Use (POU), the POT (point of tool) or POD (point of dispense), to further mitigate large particles that form in the slurry loop during recirculation.A bench setup using a combination of filters, representing those that are commonly used in the SDS and POU systems, was used to simulate both single-pass and recirculation modes. Optical particle measurement data showed a reduction in LPC (large particle count) (>0.5 um) of 60% with improved SDS filtration, and an even more significant reduction (80-90%) with additional POU filtration, which should result in fewer defects on wafer.
{"title":"The Benefits of Multi-Stage Filtration for Improved CMP Slurry Large Particle Retention","authors":"B. H. Wood, Allison Hsu, Bob Shie","doi":"10.1109/ASMC.2019.8791775","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791775","url":null,"abstract":"It is well understood that large particles and agglomerates in CMP (chemical mechanical planarization) slurries can generate defects on wafer which can result in yield loss. To minimize defects caused by large particles/agglomerates many fabs filter the slurry in the sub-fab’s SDS (slurry delivery system). It is less common to employ filtration at the Point of Use (POU), the POT (point of tool) or POD (point of dispense), to further mitigate large particles that form in the slurry loop during recirculation.A bench setup using a combination of filters, representing those that are commonly used in the SDS and POU systems, was used to simulate both single-pass and recirculation modes. Optical particle measurement data showed a reduction in LPC (large particle count) (>0.5 um) of 60% with improved SDS filtration, and an even more significant reduction (80-90%) with additional POU filtration, which should result in fewer defects on wafer.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125205466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791821
L. Sheng, Wei Pan, Zdenek Axman, V. Bucek
Yield defects and reliability defects in wafer- manufacturing are often related. To vividly illustrate in detail the complementary incentives of yield and reliability, we have provided in this paper a case study of ensuring the defect detections. In addition, an extensive review was also provided for the first time from I-V characteristics of defects to stress test failures at product sort. Our broad and multidisciplinary efforts have safeguarded the defect detections in quality manufacturing.
{"title":"Complementary Incentives of Yield and Reliability for Ensuring Defect Detections in Wafer-Manufacturing","authors":"L. Sheng, Wei Pan, Zdenek Axman, V. Bucek","doi":"10.1109/ASMC.2019.8791821","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791821","url":null,"abstract":"Yield defects and reliability defects in wafer- manufacturing are often related. To vividly illustrate in detail the complementary incentives of yield and reliability, we have provided in this paper a case study of ensuring the defect detections. In addition, an extensive review was also provided for the first time from I-V characteristics of defects to stress test failures at product sort. Our broad and multidisciplinary efforts have safeguarded the defect detections in quality manufacturing.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791748
M. A. Haque, N. Mcfarlane, N. Lavrik, D. Hensley
We have implemented carbonized nanostructures on metalized silica substrates as a step towards their integration on CMOS chips. The substrates were metallized successively with Ti and Au to provide electrical contact to the carbonized structures. Polymeric structures have been formed using 3D printing based on 2-photon polymerization. Carbonization of the polymeric structures has been achieved through a sequence of two thermal annealing steps in oxidative and inert atmospheres, respectively. Carbonization has been verified by Raman spectroscopy. Scanning electron microscopy images confirm the formation of structures and their morphology on the substrate. Integration of the demonstrated carbon structures with CMOS circuitries offer great promise for electrochemical biosensors.
{"title":"Carbonized Polymer Nanostructures for Biosensing","authors":"M. A. Haque, N. Mcfarlane, N. Lavrik, D. Hensley","doi":"10.1109/ASMC.2019.8791748","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791748","url":null,"abstract":"We have implemented carbonized nanostructures on metalized silica substrates as a step towards their integration on CMOS chips. The substrates were metallized successively with Ti and Au to provide electrical contact to the carbonized structures. Polymeric structures have been formed using 3D printing based on 2-photon polymerization. Carbonization of the polymeric structures has been achieved through a sequence of two thermal annealing steps in oxidative and inert atmospheres, respectively. Carbonization has been verified by Raman spectroscopy. Scanning electron microscopy images confirm the formation of structures and their morphology on the substrate. Integration of the demonstrated carbon structures with CMOS circuitries offer great promise for electrochemical biosensors.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131695988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791835
M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen
The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.
{"title":"Line Edge Roughness due to Oxide Rie Process : Topic: AM","authors":"M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen","doi":"10.1109/ASMC.2019.8791835","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791835","url":null,"abstract":"The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791819
T. Ning, CH Huang, V. Wong, J. Jensen, H. Chan
Coherency analysis is adopted in this paper to examine the linear dependence between measurements of three processing parameters during wafer fabrication process. They are power, pressure and voltage measurements and three channels from optical emission spectrum data. The measurement data were divided into consecutive short data segments to provide time-stamped coherence signatures. Our results observe significant linear dependence appeared in multiple harmonic frequencies. The linear dependence appears in the beginning of the processing step and continues toward the end. The verified linear relationship between process parameters sheds the light for redundancy reduction and more compact data representation.
{"title":"Coherence Analysis of Wafer Process Measurements from Chamber and Optical Emission Spectrum : APC: Advanced Process Control","authors":"T. Ning, CH Huang, V. Wong, J. Jensen, H. Chan","doi":"10.1109/ASMC.2019.8791819","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791819","url":null,"abstract":"Coherency analysis is adopted in this paper to examine the linear dependence between measurements of three processing parameters during wafer fabrication process. They are power, pressure and voltage measurements and three channels from optical emission spectrum data. The measurement data were divided into consecutive short data segments to provide time-stamped coherence signatures. Our results observe significant linear dependence appeared in multiple harmonic frequencies. The linear dependence appears in the beginning of the processing step and continues toward the end. The verified linear relationship between process parameters sheds the light for redundancy reduction and more compact data representation.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134114653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791814
S. Chowdhury, YiFeng Wu, Likun Shen, Peter Smith, J. Gritters, L. McCarthy, R. Barr, P. Parikh, T. Hosoda, Y. Kotani, K. Imanishi, T. Ogino, K. Kiuchi, Y. Asai
This manuscript proves maturity of GaN-on-Si technology for the world’s first highly reliable 650V GaN HEMT [2],[3],[4],[5],[6],[7],[8] by demonstrating three years of manufacturing data of since ramp. This technology was initially developed in a pilot line in Transphorm Goleta, CA and then later ported into a Si-CMOS compatible 6-inch foundry at AFSW(Aizu Fujitsu Semiconductor Wafers Solution Ltd). Data set generated from over three thousand wafers worth of data spread over three generations of technology nodes covering multiple products and packages post qualification is presented Silicon manufacturing processes are employed including gold- free, and avoiding the use of evaporation/liftoff typical to compound semiconductors. Best practice of defect detection, failure analysis and process control methods from Si manufacturing industry have been employed to maintain and improve yield for this new technology. Probe yield and line yield for the GaN process now matches that of mature Si-CMOS process running in the same fabrication facility[1]. Wide bandgap high-speed and high- voltage GaN devices significantly reduce the system size and improve energy efficiency of power conversion in all areas of electricity conversion, ranging from PV inverters to electric vehicles. The results below demonstrates that GaN high volume production is now a reality.
本文通过展示自ramp以来三年的制造数据，证明了全球首款高可靠性650V GaN HEMT的GaN-on- si技术的成熟度[2]，[3]，[4]，[5]，[6]，[7]，[8]。这项技术最初是在加利福尼亚州transhorm Goleta的一条试验生产线上开发的，后来被移植到AFSW(Aizu Fujitsu Semiconductor wafer Solution Ltd)的Si-CMOS兼容6英寸代工厂。数据集来自超过3000片晶圆的数据，分布在三代技术节点上，涵盖了多种产品和封装的资格认证后，采用了无金的硅制造工艺，避免了化合物半导体典型的蒸发/提升工艺。采用了硅制造行业的缺陷检测、失效分析和过程控制方法的最佳实践来保持和提高这种新技术的良率。GaN工艺的探针良率和线良率现在与在同一制造设备中运行的成熟Si-CMOS工艺相匹配[1]。宽带隙高速高压GaN器件在从光伏逆变器到电动汽车的所有电力转换领域显著减小了系统尺寸并提高了电力转换的能源效率。下面的结果表明，氮化镓的大批量生产现在是现实。
{"title":"650 V Highly Reliable GaN HEMTs on Si Substrates over multiple generations: Expanding usage of a mature 150 mm Si Foundry","authors":"S. Chowdhury, YiFeng Wu, Likun Shen, Peter Smith, J. Gritters, L. McCarthy, R. Barr, P. Parikh, T. Hosoda, Y. Kotani, K. Imanishi, T. Ogino, K. Kiuchi, Y. Asai","doi":"10.1109/ASMC.2019.8791814","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791814","url":null,"abstract":"This manuscript proves maturity of GaN-on-Si technology for the world’s first highly reliable 650V GaN HEMT [2],[3],[4],[5],[6],[7],[8] by demonstrating three years of manufacturing data of since ramp. This technology was initially developed in a pilot line in Transphorm Goleta, CA and then later ported into a Si-CMOS compatible 6-inch foundry at AFSW(Aizu Fujitsu Semiconductor Wafers Solution Ltd). Data set generated from over three thousand wafers worth of data spread over three generations of technology nodes covering multiple products and packages post qualification is presented Silicon manufacturing processes are employed including gold- free, and avoiding the use of evaporation/liftoff typical to compound semiconductors. Best practice of defect detection, failure analysis and process control methods from Si manufacturing industry have been employed to maintain and improve yield for this new technology. Probe yield and line yield for the GaN process now matches that of mature Si-CMOS process running in the same fabrication facility[1]. Wide bandgap high-speed and high- voltage GaN devices significantly reduce the system size and improve energy efficiency of power conversion in all areas of electricity conversion, ranging from PV inverters to electric vehicles. The results below demonstrates that GaN high volume production is now a reality.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123951345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791810
D. Dixit, S. Dey, Taher Kagalwala, P. Timoney, Yudesh Ramnath, Alexander Elia, Ninad Paranjape, Nick Keller, A. Vaid
Optical scatterometry or optical critical dimension (OCD) is a well-known inline metrology technique in semiconductor manufacturing especially in advanced technology nodes. OCD metrology technique has high precision, throughput, accuracy, and process integrability. OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etcetera of the patterned structures after different manufacturing steps such as lithography, etch, deposition, chemical mechanical polishing (CMP), diffusion and others. However, use of OCD for characterizing patterning defects such as overlay and tilt is fairly limited. Precise measurement and control of these features is very important for reliable functionality of the device. This report is an overview of applications and benefits of using generalized ellipsometry or Mueller matrix spectroscopic ellipsometry based OCD for characterizing patterning defects like overlay and tilt in advanced nodes. Mueller matrix (MM) elements provides important additional information of complex anisotropic patterned structures as compared to conventional ellipsometry and reflectometry parameters. Also, due to patterning process errors such as, overlay and tilt, the complex patterned structures have induced structural asymmetry. The symmetric- antisymmetric properties associated with MM elements provide an excellent means of measuring asymmetry present in these complex nano-structures. This report provides details and insights of using appropriate approaches and strategies to characterize overlay and tilt present in patterned nano-structures of advanced semiconductor technology nodes.
{"title":"Characterization of Overlay and Tilt in Advanced Technology Nodes using Scatterometry","authors":"D. Dixit, S. Dey, Taher Kagalwala, P. Timoney, Yudesh Ramnath, Alexander Elia, Ninad Paranjape, Nick Keller, A. Vaid","doi":"10.1109/ASMC.2019.8791810","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791810","url":null,"abstract":"Optical scatterometry or optical critical dimension (OCD) is a well-known inline metrology technique in semiconductor manufacturing especially in advanced technology nodes. OCD metrology technique has high precision, throughput, accuracy, and process integrability. OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etcetera of the patterned structures after different manufacturing steps such as lithography, etch, deposition, chemical mechanical polishing (CMP), diffusion and others. However, use of OCD for characterizing patterning defects such as overlay and tilt is fairly limited. Precise measurement and control of these features is very important for reliable functionality of the device. This report is an overview of applications and benefits of using generalized ellipsometry or Mueller matrix spectroscopic ellipsometry based OCD for characterizing patterning defects like overlay and tilt in advanced nodes. Mueller matrix (MM) elements provides important additional information of complex anisotropic patterned structures as compared to conventional ellipsometry and reflectometry parameters. Also, due to patterning process errors such as, overlay and tilt, the complex patterned structures have induced structural asymmetry. The symmetric- antisymmetric properties associated with MM elements provide an excellent means of measuring asymmetry present in these complex nano-structures. This report provides details and insights of using appropriate approaches and strategies to characterize overlay and tilt present in patterned nano-structures of advanced semiconductor technology nodes.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791808
Bridget Boland, G. Denbeaux, E. Eisenbraun, M. Fancher
Equipment failure can cause problems within the semiconductor industry, including product loss or contamination and unscheduled maintenance. In this paper, we apply Weibull analysis on electrochemical sensor failure and suspension data from the last eight years. Further analysis is achieved through breaking down the sensor data by model and chemistry. Using the Weibull parameters calculated and applying them to a simple financial model, we determine which sensor would give the best return on investment (ROI). The results shown in this paper will demonstrate a method for analyzing equipment or component reliability to better determine preventative maintenance practices and equipment selection based on facility operation and costs. It can be applied to a variety of equipment in a fabrication or manufacturing facility to provide a way to better plan for reliability and cost savings.
{"title":"Sensor Reliability Assessment Model and Cost Analysis : ER: Equipment Reliability and Productivity Enhancements","authors":"Bridget Boland, G. Denbeaux, E. Eisenbraun, M. Fancher","doi":"10.1109/ASMC.2019.8791808","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791808","url":null,"abstract":"Equipment failure can cause problems within the semiconductor industry, including product loss or contamination and unscheduled maintenance. In this paper, we apply Weibull analysis on electrochemical sensor failure and suspension data from the last eight years. Further analysis is achieved through breaking down the sensor data by model and chemistry. Using the Weibull parameters calculated and applying them to a simple financial model, we determine which sensor would give the best return on investment (ROI). The results shown in this paper will demonstrate a method for analyzing equipment or component reliability to better determine preventative maintenance practices and equipment selection based on facility operation and costs. It can be applied to a variety of equipment in a fabrication or manufacturing facility to provide a way to better plan for reliability and cost savings.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791763
W. Xia, Minhwa Jacoby, H. Andagana, M. Gilliland
This work explored the formation of Copper Bridge (Cu BG) defects with wafer center signature which is one of the key defect types in VLSI IC device fabrication and can result in high yield loss. Defect transition analysis and transmission electron microscopy analysis revealed that the damage on the oxide layer induced by the litho rework led to the formation of Cu BG defects. Further partition and cliff tests suggested that the severity of the ashing and cleaning conditions in the litho rework process resulted in the damage of the oxide layer. DOE studies demonstrated that lowering the power in the ashing step along with reducing the cleaning duration can largely eliminate this defect source of yield loss.
{"title":"Copper Bridge Defects with Wafer Center Signature Induced by Litho Rework Process","authors":"W. Xia, Minhwa Jacoby, H. Andagana, M. Gilliland","doi":"10.1109/ASMC.2019.8791763","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791763","url":null,"abstract":"This work explored the formation of Copper Bridge (Cu BG) defects with wafer center signature which is one of the key defect types in VLSI IC device fabrication and can result in high yield loss. Defect transition analysis and transmission electron microscopy analysis revealed that the damage on the oxide layer induced by the litho rework led to the formation of Cu BG defects. Further partition and cliff tests suggested that the severity of the ashing and cleaning conditions in the litho rework process resulted in the damage of the oxide layer. DOE studies demonstrated that lowering the power in the ashing step along with reducing the cleaning duration can largely eliminate this defect source of yield loss.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127850030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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