Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791830
S. Keil, F. Lindner, G. Schneider, Tobias Jakubowitz
Automation and digitalization are important measures for semiconductor manufacturers to enhance key performance indicators, and to strengthen their competitiveness. However, concrete approaches for effectively planning this digitalization of production or production-support processes are missing. Therefore, this paper introduces the Planning for Digitalization (P4D) approach. P4D aggregates general planning approaches for digitalization in production, as well as concrete tools and methods. By evaluating and categorizing their use in different situations of digitalization processes, P4D allows a situation-specific and new combination of these approaches and methods. Its goal is a comprehensive and action guiding compendium that can easily be applied. In this paper, part of P4D is exemplarily evaluated at a production site of Infineon Technologies in Dresden, Germany.
自动化和数字化是半导体制造企业提升关键绩效指标、增强竞争力的重要举措。然而，目前还缺乏有效规划生产或生产支持过程数字化的具体方法。因此，本文介绍了数字化规划(Planning for Digitalization, P4D)方法。P4D集合了数字化生产的总体规划方法，以及具体的工具和方法。通过评估和分类它们在数字化过程的不同情况下的使用，P4D允许这些方法和方法的具体情况和新的组合。它的目标是一个全面和行动指导纲要，可以很容易地应用。本文在德国德累斯顿英飞凌技术的一个生产基地对部分P4D进行了实例评估。
{"title":"A Planning Approach for an Effective Digitalization of Processes in Mature Semiconductor Production Facilities","authors":"S. Keil, F. Lindner, G. Schneider, Tobias Jakubowitz","doi":"10.1109/ASMC.2019.8791830","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791830","url":null,"abstract":"Automation and digitalization are important measures for semiconductor manufacturers to enhance key performance indicators, and to strengthen their competitiveness. However, concrete approaches for effectively planning this digitalization of production or production-support processes are missing. Therefore, this paper introduces the Planning for Digitalization (P4D) approach. P4D aggregates general planning approaches for digitalization in production, as well as concrete tools and methods. By evaluating and categorizing their use in different situations of digitalization processes, P4D allows a situation-specific and new combination of these approaches and methods. Its goal is a comprehensive and action guiding compendium that can easily be applied. In this paper, part of P4D is exemplarily evaluated at a production site of Infineon Technologies in Dresden, Germany.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128531069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791766
W. Xia, David Anderson, Felix Lin, Jonathan Cohrs, Shazad Paracha, D. Mahato, Eric Ellis
Oxide Bridge (OX BG) with wafer center signature was found in the back-end-of-line (BEOL) section of IC fabrication. The defect resembled lifted photoresist (PR) pattern and was uncovered to be related with the weak points at the scribe lines surrounding the active die area. The PR lifting OX BG was significantly reduced through optimizing the focus margin as well as fixing the weak points at the scribe lines.
{"title":"Photoresist Lifting Induced Oxide Bridge Defects","authors":"W. Xia, David Anderson, Felix Lin, Jonathan Cohrs, Shazad Paracha, D. Mahato, Eric Ellis","doi":"10.1109/ASMC.2019.8791766","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791766","url":null,"abstract":"Oxide Bridge (OX BG) with wafer center signature was found in the back-end-of-line (BEOL) section of IC fabrication. The defect resembled lifted photoresist (PR) pattern and was uncovered to be related with the weak points at the scribe lines surrounding the active die area. The PR lifting OX BG was significantly reduced through optimizing the focus margin as well as fixing the weak points at the scribe lines.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124440743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791769
I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn
Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the "Early Testable Addressable Logic (ETAL)" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.
{"title":"Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development","authors":"I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn","doi":"10.1109/ASMC.2019.8791769","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791769","url":null,"abstract":"Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the \"Early Testable Addressable Logic (ETAL)\" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130345163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791765
Chien-Cheng Lung, Yao-An Chung, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
Silicon selective epitaxial growth (Si-SEG) plays an important role in 3D NAND memory because it switches on/off current in vertical channels (VC). In this study, a damaged layer containing carbon (C), fluorine (F), oxygen (O) impurities was detected after VC etch. It severely impacts the Si-SEG quality and results in large Si-SEG height variations. Novel ex situ or in situ halogen-containing plasma etch treatments (PETs) were developed in order to remove the damaged layer and impurities. A series of design of experiments (DOE) were also studied in order to optimize the PET recipe and minimize plasma damage by PET on the Si surface. Finally, optimized PET was shown to improve the crystallinity and height uniformity of Si-SEG.
{"title":"Pre-Epitaxial Plasma Etch Treatment for the Selective Epitaxial Growth of Silicon in High Aspect Ratio 3D NAND Memory","authors":"Chien-Cheng Lung, Yao-An Chung, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/ASMC.2019.8791765","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791765","url":null,"abstract":"Silicon selective epitaxial growth (Si-SEG) plays an important role in 3D NAND memory because it switches on/off current in vertical channels (VC). In this study, a damaged layer containing carbon (C), fluorine (F), oxygen (O) impurities was detected after VC etch. It severely impacts the Si-SEG quality and results in large Si-SEG height variations. Novel ex situ or in situ halogen-containing plasma etch treatments (PETs) were developed in order to remove the damaged layer and impurities. A series of design of experiments (DOE) were also studied in order to optimize the PET recipe and minimize plasma damage by PET on the Si surface. Finally, optimized PET was shown to improve the crystallinity and height uniformity of Si-SEG.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130975101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791811
F. Heider, Helfried Schwarzfurtner, Mario Lugger, Sang-Joon Cho, T. Trenkler
Roughness measurements on epitaxial layers before and after etching were done with an atomic force microscope (AFM) with sub-Angstrom repeatability. Furthermore, surface roughness was monitored with AFM after chemical mechanical polishing, before a wafer was bonded to another wafer. It was observed that measuring in non-contact mode reduces the tip wear and extends the life time of AFM tips. We also show that a resist recess in narrow trenches which cannot be measured with scatterometry is easily measured with a high-aspect-ratio tip on AFM. The offset between the AFMs in two different fabs is currently less than 5 nm, when a trench depth recipe is transferred from one tool to another.
{"title":"AFM Surface Roughness and Depth Measurement of Trenches with High Aspect Ratio","authors":"F. Heider, Helfried Schwarzfurtner, Mario Lugger, Sang-Joon Cho, T. Trenkler","doi":"10.1109/ASMC.2019.8791811","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791811","url":null,"abstract":"Roughness measurements on epitaxial layers before and after etching were done with an atomic force microscope (AFM) with sub-Angstrom repeatability. Furthermore, surface roughness was monitored with AFM after chemical mechanical polishing, before a wafer was bonded to another wafer. It was observed that measuring in non-contact mode reduces the tip wear and extends the life time of AFM tips. We also show that a resist recess in narrow trenches which cannot be measured with scatterometry is easily measured with a high-aspect-ratio tip on AFM. The offset between the AFMs in two different fabs is currently less than 5 nm, when a trench depth recipe is transferred from one tool to another.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"16 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791825
Jenny Bartholomäus, Swen Wunderlich, Z. Sasvári
In the semiconductor industry the reliability of devices is of paramount importance. Therefore, after removing the defective ones, one wants to detect irregularities in measurement data because corresponding devices have a higher risk of failure early in the product lifetime. Furthermore it would be desirable to consider multiple functional tests together due to existing dependencies. This paper presents a method to detect such suspicious devices where the screening is made on transformed measurement data. Additionally, a new dimensionality reduction is performed within the transformation so that the reduced and transformed data comprises only the informative content from the raw data. Therefore the complexity of the subsequent screening steps is simplified.
{"title":"Identification of Suspicious Semiconductor Devices Using Independent Component Analysis with Dimensionality Reduction","authors":"Jenny Bartholomäus, Swen Wunderlich, Z. Sasvári","doi":"10.1109/ASMC.2019.8791825","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791825","url":null,"abstract":"In the semiconductor industry the reliability of devices is of paramount importance. Therefore, after removing the defective ones, one wants to detect irregularities in measurement data because corresponding devices have a higher risk of failure early in the product lifetime. Furthermore it would be desirable to consider multiple functional tests together due to existing dependencies. This paper presents a method to detect such suspicious devices where the screening is made on transformed measurement data. Additionally, a new dimensionality reduction is performed within the transformation so that the reduced and transformed data comprises only the informative content from the raw data. Therefore the complexity of the subsequent screening steps is simplified.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124234205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791828
Sonal Singh, S. Khokale, Qian Xie, Panneerselvam Venkatachalam, Alexa Greer, A. Mathur, Ankit Jain
Semiconductor yield improvement and stability is becoming increasingly more difficult to achieve with decreasing technology nodes. There are many new sources, types, and mechanisms of process induced systematic defects, with a growing demand to identify and control those sources of hotspots that impact yield with the most comprehensive results, fastest time, and lowest cost. Previously there has been extensive characterization and publications on the techniques used for hotspot discovery, with little overall improvement to the flow and time to results needed to keep up with today’s fast paced development process which requires rapid results. We propose implementing new inspection and binning algorithms to the process window discovery methodology, to achieve improvements in time to results, process window qualification, and hotspot identification. These systematic defect discovery improvements enable lithography processes to be controlled and monitored more accurately and more precisely than ever before.
{"title":"Utilizing Single Scan and Enhanced Design-Based Binning Methodologies for Improved Process Window and Hotspot Discovery","authors":"Sonal Singh, S. Khokale, Qian Xie, Panneerselvam Venkatachalam, Alexa Greer, A. Mathur, Ankit Jain","doi":"10.1109/ASMC.2019.8791828","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791828","url":null,"abstract":"Semiconductor yield improvement and stability is becoming increasingly more difficult to achieve with decreasing technology nodes. There are many new sources, types, and mechanisms of process induced systematic defects, with a growing demand to identify and control those sources of hotspots that impact yield with the most comprehensive results, fastest time, and lowest cost. Previously there has been extensive characterization and publications on the techniques used for hotspot discovery, with little overall improvement to the flow and time to results needed to keep up with today’s fast paced development process which requires rapid results. We propose implementing new inspection and binning algorithms to the process window discovery methodology, to achieve improvements in time to results, process window qualification, and hotspot identification. These systematic defect discovery improvements enable lithography processes to be controlled and monitored more accurately and more precisely than ever before.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128404980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791823
Chen-Men Lin, Yun-Chung Tung, Shufen Lin, Steve Lin, Alex T. Cheng
Zero-defects is the target for automotive devices in semiconductor manufacturing fabs. The challenges created by 100% inline inspection wafer sampling and new lithography processes have resulted in a critical need for wafer inspection. We have several requirements for the inspection tools: high capture rate with very low nuisance defect rate, high throughput with high sensitivity, and efficient high-quality defect review images to increase productivity. This paper is based on several months of photolithography wafers inspection data results. Our goal with this investigation was to meet the high volume and high reliability requirement.
{"title":"Inline defect control for automotive memory devices in IC manufacturing","authors":"Chen-Men Lin, Yun-Chung Tung, Shufen Lin, Steve Lin, Alex T. Cheng","doi":"10.1109/ASMC.2019.8791823","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791823","url":null,"abstract":"Zero-defects is the target for automotive devices in semiconductor manufacturing fabs. The challenges created by 100% inline inspection wafer sampling and new lithography processes have resulted in a critical need for wafer inspection. We have several requirements for the inspection tools: high capture rate with very low nuisance defect rate, high throughput with high sensitivity, and efficient high-quality defect review images to increase productivity. This paper is based on several months of photolithography wafers inspection data results. Our goal with this investigation was to meet the high volume and high reliability requirement.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116334070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791767
Doug Suerich, Terry Young
Semiconductor cluster equipment adds an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum- atmospheric cycle. Such highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault-tolerant manner. Software engineers typically build schedulers using a set of manually- configured heuristics but this can be a labor-intensive process where small changes to the cluster configuration or process requirements can require large changes to the scheduler. Our motivation for this work was to investigate whether a machine learning approach to complex cluster scheduling could be developed more efficiently and at a lower cost than existing methods.
{"title":"Machine Learning for Optimized Scheduling in Complex Semiconductor Equipment","authors":"Doug Suerich, Terry Young","doi":"10.1109/ASMC.2019.8791767","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791767","url":null,"abstract":"Semiconductor cluster equipment adds an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum- atmospheric cycle. Such highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault-tolerant manner. Software engineers typically build schedulers using a set of manually- configured heuristics but this can be a labor-intensive process where small changes to the cluster configuration or process requirements can require large changes to the scheduler. Our motivation for this work was to investigate whether a machine learning approach to complex cluster scheduling could be developed more efficiently and at a lower cost than existing methods.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791791
M. Liebens, J. Slabbekoorn, A. Miller, E. Beyne, R. Yeoh, T. Krah, A. Vangal, S. Hiebert, A. Cross
Advanced wafer level packaging is moving into high volume mobile and consumer electronics markets. Drivers for new packaging and integration schemes are lower-cost processes and the high count of interconnects. The different functional parts of a high-performance package are designed with high-density interconnects requiring multiple fine-pitch redistribution layers (RDL) to route and fan-out the tight pitch interconnects to the package level. Currently, high-density fan-out packages are evolving toward 1µm line/space and even beyond. Reducing RDL line and space widths creates challenges for the different process steps that are used to produce RDL, therefore the need for accurate and precise inline process control. This paper will elaborate on the fundamental requirements for defectivity and metrology of fine- pitch RDL processing. Defect inspection and measurements are performed on wafers containing fine-pitch RDL. Based on the correlation between electrical yield results and inspection and measurement data, improvements for the smallest RDL line/space sizes are proposed and validated to meet the requirements for defectivity and metrology of fine-pitch RDL.
{"title":"What’s in Space – Exploration and Improvement of Line/Space Defect Inspection of Fine-Pitch Redistribution Layer for Fan-Out Wafer Level Packaging","authors":"M. Liebens, J. Slabbekoorn, A. Miller, E. Beyne, R. Yeoh, T. Krah, A. Vangal, S. Hiebert, A. Cross","doi":"10.1109/ASMC.2019.8791791","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791791","url":null,"abstract":"Advanced wafer level packaging is moving into high volume mobile and consumer electronics markets. Drivers for new packaging and integration schemes are lower-cost processes and the high count of interconnects. The different functional parts of a high-performance package are designed with high-density interconnects requiring multiple fine-pitch redistribution layers (RDL) to route and fan-out the tight pitch interconnects to the package level. Currently, high-density fan-out packages are evolving toward 1µm line/space and even beyond. Reducing RDL line and space widths creates challenges for the different process steps that are used to produce RDL, therefore the need for accurate and precise inline process control. This paper will elaborate on the fundamental requirements for defectivity and metrology of fine- pitch RDL processing. Defect inspection and measurements are performed on wafers containing fine-pitch RDL. Based on the correlation between electrical yield results and inspection and measurement data, improvements for the smallest RDL line/space sizes are proposed and validated to meet the requirements for defectivity and metrology of fine-pitch RDL.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123387102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：