Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783370
Poulami Jana, G. Maity, Himadri S. Mandal
A lifting domain reversible data hiding is presented here. A content based watermark is produced from selective $(4times 4)$ sized coefficient blocks of particular sub-band. One covert key is utilized to secure the watermark for access management which is specified by user. The secure watermark is implanted within same coefficient block $(4times 4)$. In receiver side the retrieval of original image is done by the authentic user's secure key. For real time application the ‘very large scale integration’ (VLSI) architecture of this proposed encoder is designed in hardware. Simulation of the encoder is done by ‘field programmable gate array’ (FPGA) kit. The experimentation is performed over a range of benchmark images. The results justify the supremacy of the method. The encoder module consumes only 59.20mW power when operated at 120.135MHz frequency in case of real time implementation.
{"title":"A Low Power Hardware Implementation of Lifting based Reversible Watermarking for Medical Image","authors":"Poulami Jana, G. Maity, Himadri S. Mandal","doi":"10.1109/DEVIC.2019.8783370","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783370","url":null,"abstract":"A lifting domain reversible data hiding is presented here. A content based watermark is produced from selective $(4times 4)$ sized coefficient blocks of particular sub-band. One covert key is utilized to secure the watermark for access management which is specified by user. The secure watermark is implanted within same coefficient block $(4times 4)$. In receiver side the retrieval of original image is done by the authentic user's secure key. For real time application the ‘very large scale integration’ (VLSI) architecture of this proposed encoder is designed in hardware. Simulation of the encoder is done by ‘field programmable gate array’ (FPGA) kit. The experimentation is performed over a range of benchmark images. The results justify the supremacy of the method. The encoder module consumes only 59.20mW power when operated at 120.135MHz frequency in case of real time implementation.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122874177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783725
Tara Prasanna Dash, S. Das, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti
The FinFET transistor is now considered the most probable successor of the bulk MOSFET transistor in the global race for miniaturization in the field of micro- and nanoelectronics. The development of integrated circuits using FinFETs is made possible only by the use of their compact models. These models must predict precisely the electrical behavior of these devices advanced technologies. In this work, we show an integrated approach for SPICE parameter extraction explicitly for nanoscale FinFETs, which is validated by comparisons with simulation results. We discuss in detail the platform necessary for the development of the model and automated SPICE parameter extraction. The predictive capability of TCAD to estimate the SPICE model parameters from process-based on the physical variations of process parameters has been examined.
{"title":"SPICE Parameter Extraction of Tri-Gate FinFETs-An Integrated Approach","authors":"Tara Prasanna Dash, S. Das, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783725","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783725","url":null,"abstract":"The FinFET transistor is now considered the most probable successor of the bulk MOSFET transistor in the global race for miniaturization in the field of micro- and nanoelectronics. The development of integrated circuits using FinFETs is made possible only by the use of their compact models. These models must predict precisely the electrical behavior of these devices advanced technologies. In this work, we show an integrated approach for SPICE parameter extraction explicitly for nanoscale FinFETs, which is validated by comparisons with simulation results. We discuss in detail the platform necessary for the development of the model and automated SPICE parameter extraction. The predictive capability of TCAD to estimate the SPICE model parameters from process-based on the physical variations of process parameters has been examined.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132605205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783914
P. Chakraborty, Ratul Ghosh, Anwesha Adhikary, A. Deyasi, A. Sarkar
Bandgap width within first Brillouin zone in metamaterial-based two-dimensional photonic crystal structure is analytically computed using plane wave expansion method. A wider range of negative refractive index is considered for simulation purpose within physically feasible limit whereas rectangular geometrical shape is taken into account for the analysis with TE mode of propagation. Artificial materials in presence of air holes are considered to achieve negative index, and results are compared with that obtained for conventional SiO2-air material system with equivalent dimensional configuration. Coordinates of two peak points, $hbox{`}Gammahbox{'}$ point and ‘X’, point are noted for all the DNG materials which give the indication of blueshift of the valence region with change of negative refractive index. Simulated findings speak in favor of multiple forbidden regions for some specific material systems which can be utilized to design photonic multi-channel filter in beyond THz region.
用平面波展开法解析计算了基于超材料的二维光子晶体结构中第一布里渊带的带隙宽度。在物理可行的范围内考虑了更宽的负折射率范围，而在用TE传播模式进行分析时则考虑了矩形几何形状。考虑存在气孔的人工材料达到负指标，并与具有等效尺寸结构的传统sio2 -空气材料体系的结果进行了比较。所有DNG材料的两个峰点，$hbox{'} Gammahbox{'}$点和' X '，点的坐标，给出了价区蓝移随负折射率变化的指示。模拟结果支持某些特定材料体系存在多禁区，可用于设计超太赫兹区域的光子多通道滤波器。
{"title":"Electromagnetic Bandgap Formation in Two-Dimensional Photonic Crystal Structure with DNG Materials under TE Mode","authors":"P. Chakraborty, Ratul Ghosh, Anwesha Adhikary, A. Deyasi, A. Sarkar","doi":"10.1109/DEVIC.2019.8783914","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783914","url":null,"abstract":"Bandgap width within first Brillouin zone in metamaterial-based two-dimensional photonic crystal structure is analytically computed using plane wave expansion method. A wider range of negative refractive index is considered for simulation purpose within physically feasible limit whereas rectangular geometrical shape is taken into account for the analysis with TE mode of propagation. Artificial materials in presence of air holes are considered to achieve negative index, and results are compared with that obtained for conventional SiO2-air material system with equivalent dimensional configuration. Coordinates of two peak points, $hbox{`}Gammahbox{'}$ point and ‘X’, point are noted for all the DNG materials which give the indication of blueshift of the valence region with change of negative refractive index. Simulated findings speak in favor of multiple forbidden regions for some specific material systems which can be utilized to design photonic multi-channel filter in beyond THz region.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125679307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783284
Pritha Banerjee, Priyanka Saha, Dinesh Kumar Dash, S. Sarkar
Gate work function engineered MOSFET coupled with the channel and dielectric engineering benefits has always been an important topic owing to their supreme immunity over Short Channel Effects (SCEs). In this paper, the analytical model of a Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET has been presented by solving the Poisson's equation in 2D and following parabolic potential approximation approach. The analytical results have been substantiated by ATLAS simulated data.
{"title":"Surface potential based Analytical Modeling of Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET","authors":"Pritha Banerjee, Priyanka Saha, Dinesh Kumar Dash, S. Sarkar","doi":"10.1109/DEVIC.2019.8783284","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783284","url":null,"abstract":"Gate work function engineered MOSFET coupled with the channel and dielectric engineering benefits has always been an important topic owing to their supreme immunity over Short Channel Effects (SCEs). In this paper, the analytical model of a Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET has been presented by solving the Poisson's equation in 2D and following parabolic potential approximation approach. The analytical results have been substantiated by ATLAS simulated data.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114583333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783341
Biswajit Baral, S. Biswal, S. Swain, S. K. Das, D. Nayak, Dhananjaya Tripathy
With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(mathrm{g}_{mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(mathrm{R}_{mathrm{o}mathrm{u}mathrm{t}})$, cut-off frequency $(mathrm{f}_{mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{d}})$, maximum frequency $(mathrm{f}_{max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.
{"title":"RF/Analog & Linearity performance analysis of a downscaled JL DG MOSFET on GaAs substrate for Analog/mixed signal SOC applications","authors":"Biswajit Baral, S. Biswal, S. Swain, S. K. Das, D. Nayak, Dhananjaya Tripathy","doi":"10.1109/DEVIC.2019.8783341","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783341","url":null,"abstract":"With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(mathrm{g}_{mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(mathrm{R}_{mathrm{o}mathrm{u}mathrm{t}})$, cut-off frequency $(mathrm{f}_{mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{d}})$, maximum frequency $(mathrm{f}_{max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121442913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783754
Shekhar Verma, S. Tripathi, Mohinder Bassi
The introduction of Field Effect Transistor (FinFET) Technology played a leading contender in today microelectronics. FinFET structure allows to scale the device at sub-nanometer. Short channel effects can be suppressed by formation of ultra-thin fin in FinFET device. In this paper we compared the performance of the 20nm FinFET device by using different dielectric materials. We have considered only n-channel FinFET device. Simulation carried on the electron mobility, potential distribution, energy band of hole and electron, on-off current ratio (Ion/Ioff) and power dissipation of device with respect to the applied gate voltage. Mobility enhancement and higher current ratio (Ion/Ioff) is observed in proposed FinFET device having high k-dielectric material at lower voltage. This designed can be useful for low power applications due to low power dissipation. In high k-dielectric material, 1.41% improvement is observed in potential voltage with respect to low k- dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 0.98% improvement is observed when $mathbf{V}_{mathbf{gs}}$ at high voltage. In high k- dielectric material 15% hike is observed in the energy conduction band as compared to low k-dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 14% hike is observed when $mathbf{v}_{mathbf{gs}}$ at high voltage.
{"title":"Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications","authors":"Shekhar Verma, S. Tripathi, Mohinder Bassi","doi":"10.1109/DEVIC.2019.8783754","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783754","url":null,"abstract":"The introduction of Field Effect Transistor (FinFET) Technology played a leading contender in today microelectronics. FinFET structure allows to scale the device at sub-nanometer. Short channel effects can be suppressed by formation of ultra-thin fin in FinFET device. In this paper we compared the performance of the 20nm FinFET device by using different dielectric materials. We have considered only n-channel FinFET device. Simulation carried on the electron mobility, potential distribution, energy band of hole and electron, on-off current ratio (Ion/Ioff) and power dissipation of device with respect to the applied gate voltage. Mobility enhancement and higher current ratio (Ion/Ioff) is observed in proposed FinFET device having high k-dielectric material at lower voltage. This designed can be useful for low power applications due to low power dissipation. In high k-dielectric material, 1.41% improvement is observed in potential voltage with respect to low k- dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 0.98% improvement is observed when $mathbf{V}_{mathbf{gs}}$ at high voltage. In high k- dielectric material 15% hike is observed in the energy conduction band as compared to low k-dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 14% hike is observed when $mathbf{v}_{mathbf{gs}}$ at high voltage.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783677
Bijoy Goswami, Debadipta Basak, A. Bhattacharya, Koelgeet Kaur, Sutanni Bhowmick, S. Sarkar
The analytical surface potential model of 22nm salient source Double Gate TFET (SS-DG-TFET) is presented in this paper. The surface potential is analyzed as the performance parameter along with an assessment of improved ON/ OFF current ratio. The variation of tunnel current is examined under same front and back gate bias together with identical oxide thickness. The source region has been extended symmetrically in both directions in order to enhance the conductivity of the channel region and it has been efficiently deployed in the proposed model. The execution of low power functionality and lower sub-threshold slope is also established in this model. The analytical results have been suitably validated using Silvaco, Atlas.
{"title":"Analytical Modeling and Simulation of Low Power Salient Source Double Gate TFET","authors":"Bijoy Goswami, Debadipta Basak, A. Bhattacharya, Koelgeet Kaur, Sutanni Bhowmick, S. Sarkar","doi":"10.1109/DEVIC.2019.8783677","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783677","url":null,"abstract":"The analytical surface potential model of 22nm salient source Double Gate TFET (SS-DG-TFET) is presented in this paper. The surface potential is analyzed as the performance parameter along with an assessment of improved ON/ OFF current ratio. The variation of tunnel current is examined under same front and back gate bias together with identical oxide thickness. The source region has been extended symmetrically in both directions in order to enhance the conductivity of the channel region and it has been efficiently deployed in the proposed model. The execution of low power functionality and lower sub-threshold slope is also established in this model. The analytical results have been suitably validated using Silvaco, Atlas.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130188227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783414
Maitraiyee Konar, R. Sahu, S. Kundu
This paper evaluates the performance of three operational amplifier (Op-Amp) based instrumentation amplifier (INA) topology using two variants of Op-Amp - one with a very high gain with respect to the other Op-Amp topology. The gain accuracy and common mode rejection ratio (CMRR) of the INA is improved with the use of the very high gain Op-Amp designed using a folded cascode amplifier. The CMRR of the INA using folded cascade Op-Amp is 114 dB which is 43 dB higher to that of INA using differential amplifier.
{"title":"Improvement of the Gain Accuracy of the Instrumentation Amplifier Using a Very High Gain Operational Amplifier","authors":"Maitraiyee Konar, R. Sahu, S. Kundu","doi":"10.1109/DEVIC.2019.8783414","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783414","url":null,"abstract":"This paper evaluates the performance of three operational amplifier (Op-Amp) based instrumentation amplifier (INA) topology using two variants of Op-Amp - one with a very high gain with respect to the other Op-Amp topology. The gain accuracy and common mode rejection ratio (CMRR) of the INA is improved with the use of the very high gain Op-Amp designed using a folded cascode amplifier. The CMRR of the INA using folded cascade Op-Amp is 114 dB which is 43 dB higher to that of INA using differential amplifier.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125277363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783691
S. Basak, Swaraj Banerjee
ELD with the help of Jaya Optimization Technique has been proved as one of the better options. Along with the cost curves or cost coefficients valve point effect has also very important impact in ELD. So in this paper, for ELD with valve point effect has been optimized with the help of Adaptive Jaya Optimization Technique. 13 thermal unit has been taken to get the optimal power output and optimal cost, which has been compared to the other optimization techniques' results. Advantage of this proposed optimization technique has been shown in the current work.
{"title":"Adaptive Jaya Optimization Technique for Economic Load Dispatch Considering Valve Point Effect","authors":"S. Basak, Swaraj Banerjee","doi":"10.1109/DEVIC.2019.8783691","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783691","url":null,"abstract":"ELD with the help of Jaya Optimization Technique has been proved as one of the better options. Along with the cost curves or cost coefficients valve point effect has also very important impact in ELD. So in this paper, for ELD with valve point effect has been optimized with the help of Adaptive Jaya Optimization Technique. 13 thermal unit has been taken to get the optimal power output and optimal cost, which has been compared to the other optimization techniques' results. Advantage of this proposed optimization technique has been shown in the current work.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121180130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/devic.2019.8783299
{"title":"Message from General Chair & Editor","authors":"","doi":"10.1109/devic.2019.8783299","DOIUrl":"https://doi.org/10.1109/devic.2019.8783299","url":null,"abstract":"","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131687331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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