Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549418
Zhang Lei, Zhao Xian-li, Wang Xing-hua, Qu Ruo-yuan
This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8v and with the direct current of 200uA. The tool Matlab is used to simulate the behavior system, while Cadence is used to design the circuit and the layout in 0.18 um CMOS (1.8v model) process. The modulator achieves 81dB dynamic range in 24-kHz signal bandwidth with OSR=128. And it consumes 0.8mW under 1.8v supply voltage.
本文提出了一种采用开关电容(SC)技术的低功耗二阶σ - δ调制器，用于0.18um CMOS工艺。无连续电流传输的SC技术是一种离散的低功率系统。设计了具有离散共模反馈和动态比较器的低功率运算放大器。这种新型放大器在1.8v的电源下工作，直流电为200uA。利用Matlab工具对系统行为进行仿真，利用Cadence在0.18 um CMOS (1.8v模型)工艺下进行电路设计和布局。该调制器在24khz信号带宽下实现81dB动态范围，OSR=128。电源电压为1.8v时，功耗为0.8mW。
{"title":"Two-order low-power sigma-delta modulator with SC techniques","authors":"Zhang Lei, Zhao Xian-li, Wang Xing-hua, Qu Ruo-yuan","doi":"10.1109/SMELEC.2010.5549418","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549418","url":null,"abstract":"This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8v and with the direct current of 200uA. The tool Matlab is used to simulate the behavior system, while Cadence is used to design the circuit and the layout in 0.18 um CMOS (1.8v model) process. The modulator achieves 81dB dynamic range in 24-kHz signal bandwidth with OSR=128. And it consumes 0.8mW under 1.8v supply voltage.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129478382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549386
Ying-Ju Chiu, Kuo-Fu Lee, Ying-Chieh Chen, Hui-Wen Cheng, Yiming Li, Tony Chiang, Kuen-Yu Huang, T. Hsieh
In this work, we for the first time optimize dynamic characteristic of amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuits for TFT-LCD panel. The rise time, fall time, power dissipation, and ripple voltage of the ASG driver circuit are optimized using simulation-based evolutionary method which integrates genetic algorithm and circuit simulation on the unified optimization framework [1]. Two different a-Si:H TFT ASG driver circuits are optimized, the first circuit consisting of 14 a-Si:H TFT devices is designed for the specification of the rise time < 1.5 µs, the fall time < 1.5 µs and the ripple voltage < 3 V with the minimization of total layout area. The second one with 8 a-Si:H TFTs is further optimized with the power dissipation < 2 mW. The results of this study successfully met the desired specification; consequently, it benefits manufacturing of TFT-LCD panel.
{"title":"Amorphous silicon thin-film transistor gate driver circuit design optimization using a simulation-based evolutionary technique","authors":"Ying-Ju Chiu, Kuo-Fu Lee, Ying-Chieh Chen, Hui-Wen Cheng, Yiming Li, Tony Chiang, Kuen-Yu Huang, T. Hsieh","doi":"10.1109/SMELEC.2010.5549386","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549386","url":null,"abstract":"In this work, we for the first time optimize dynamic characteristic of amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuits for TFT-LCD panel. The rise time, fall time, power dissipation, and ripple voltage of the ASG driver circuit are optimized using simulation-based evolutionary method which integrates genetic algorithm and circuit simulation on the unified optimization framework [1]. Two different a-Si:H TFT ASG driver circuits are optimized, the first circuit consisting of 14 a-Si:H TFT devices is designed for the specification of the rise time < 1.5 µs, the fall time < 1.5 µs and the ripple voltage < 3 V with the minimization of total layout area. The second one with 8 a-Si:H TFTs is further optimized with the power dissipation < 2 mW. The results of this study successfully met the desired specification; consequently, it benefits manufacturing of TFT-LCD panel.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549409
F. Abdullah, N. Nayan, M. M. Jamil, Norfauzi Kamsin
One of the fashionable stress test that has been practiced in CMOS VLSI recently is known as IDDQ scan test. It has competency to be exercised as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. Form the results obtained during the experiment, it shows that the IDD scan test can be applied effectively in triggering significant emission spot during anomalous logic transition.
{"title":"IDD scan test method for fault localization technique on CMOS VLSI failure analysis","authors":"F. Abdullah, N. Nayan, M. M. Jamil, Norfauzi Kamsin","doi":"10.1109/SMELEC.2010.5549409","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549409","url":null,"abstract":"One of the fashionable stress test that has been practiced in CMOS VLSI recently is known as IDDQ scan test. It has competency to be exercised as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. Form the results obtained during the experiment, it shows that the IDD scan test can be applied effectively in triggering significant emission spot during anomalous logic transition.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549538
H. Ahmataku, K. Kipli
Significant financial profits recognized by reducing the wafer edge exclusion ring in order to increase extra productive dies as well as enhance the yield of the edge-most region of the semiconductor wafer. A method to determine distance of structure from a wafer edge is implemented using software called HandiExclusion v.3 and template named HandieRad. The wafer is put onto the template to get H degree measurement. Program then convert the H degree to a distance measurement from the wafer edge. Scanning Electron Microscope (SEM) Tap-Center Technique used to move precisely at the target distance.
{"title":"A cost effective method to analyze wafer edge structure in high volume manufacturing for 200mm wafer fabs","authors":"H. Ahmataku, K. Kipli","doi":"10.1109/SMELEC.2010.5549538","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549538","url":null,"abstract":"Significant financial profits recognized by reducing the wafer edge exclusion ring in order to increase extra productive dies as well as enhance the yield of the edge-most region of the semiconductor wafer. A method to determine distance of structure from a wafer edge is implemented using software called HandiExclusion v.3 and template named HandieRad. The wafer is put onto the template to get H degree measurement. Program then convert the H degree to a distance measurement from the wafer edge. Scanning Electron Microscope (SEM) Tap-Center Technique used to move precisely at the target distance.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128242900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549372
A. Bahadorimehr, J. Yunas, B. Majlis
In this paper, we present a simple, rapid, and low-cost procedure for fabricating micro-nozzles and micro-diffusers using in microfluidic devices to control the flow of the fluid which pass through the microchannels. This procedure uses commercially accessible and typical materials, which is used in several applications in microelectronic labs. Glass is used as main substrate to get advantages of photo transparent specifications of this material. In this method a thick layer of positive photoresist on the glass substrate for fabrication of lens is utilized. A mild BOE solution with additional HCL is employed to achieve an excellent etching quality and a smoother etched surface. The depth of the surface can be reach to 100µm without PR damage effect after 1 hour of etching process. The aluminum evaporation process produces a thin layer of aluminum across the substrate which makes it as a block against passing the light. Dispensing SU-8 on Al layer and using UV back-exposure technique the tapered structured is fabricated as a mold for PDMS which can be used in different microfluidic applications. The simulation results shows that the focal length up to 800µm with the lens curvature of 150µm is achievable.
{"title":"Low cost procedure for fabrication of micro-nozzles and micro-diffusers","authors":"A. Bahadorimehr, J. Yunas, B. Majlis","doi":"10.1109/SMELEC.2010.5549372","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549372","url":null,"abstract":"In this paper, we present a simple, rapid, and low-cost procedure for fabricating micro-nozzles and micro-diffusers using in microfluidic devices to control the flow of the fluid which pass through the microchannels. This procedure uses commercially accessible and typical materials, which is used in several applications in microelectronic labs. Glass is used as main substrate to get advantages of photo transparent specifications of this material. In this method a thick layer of positive photoresist on the glass substrate for fabrication of lens is utilized. A mild BOE solution with additional HCL is employed to achieve an excellent etching quality and a smoother etched surface. The depth of the surface can be reach to 100µm without PR damage effect after 1 hour of etching process. The aluminum evaporation process produces a thin layer of aluminum across the substrate which makes it as a block against passing the light. Dispensing SU-8 on Al layer and using UV back-exposure technique the tapered structured is fabricated as a mold for PDMS which can be used in different microfluidic applications. The simulation results shows that the focal length up to 800µm with the lens curvature of 150µm is achievable.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125635431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549380
M. Bayat, H. Shamsi, M. Fouladian, Morteza Rahimi
A fully monolithic 5 GHz CMOS LC-VCO, designed in a 0.18 µm 1P6M CMOS technology, is presented in this paper. The tuning range of the VCO is from 4.1 GHz to 5.24 GHz, about 24%. The measured phase noise at 5-GHz is -115.8dBc/Hz at 1MHz offset from the carrier. It meets the requirements for IEEE 802.11a WLAN standard. The current dissipation of the VCO is 2mA from the 1.8V power supply.
{"title":"A 5-GHZ VCO for WLAN applications","authors":"M. Bayat, H. Shamsi, M. Fouladian, Morteza Rahimi","doi":"10.1109/SMELEC.2010.5549380","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549380","url":null,"abstract":"A fully monolithic 5 GHz CMOS LC-VCO, designed in a 0.18 µm 1P6M CMOS technology, is presented in this paper. The tuning range of the VCO is from 4.1 GHz to 5.24 GHz, about 24%. The measured phase noise at 5-GHz is -115.8dBc/Hz at 1MHz offset from the carrier. It meets the requirements for IEEE 802.11a WLAN standard. The current dissipation of the VCO is 2mA from the 1.8V power supply.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"3 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549480
A. Jarndal, Pouya Aflaki, F. Ghannouchi
In this paper, a large-signal model for GaN HEMT transistors for designing RF power amplifiers is presented. This model is relatively easy to construct and implement in CAD software since it requires only DC and S-parameter measurements. The modeling procedure is applied to a 4-W packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation to measured data under different classes of operation.
{"title":"Large-signal modeling of AlGaN/GaN HEMTs based on DC IV and S-parameter measurements","authors":"A. Jarndal, Pouya Aflaki, F. Ghannouchi","doi":"10.1109/SMELEC.2010.5549480","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549480","url":null,"abstract":"In this paper, a large-signal model for GaN HEMT transistors for designing RF power amplifiers is presented. This model is relatively easy to construct and implement in CAD software since it requires only DC and S-parameter measurements. The modeling procedure is applied to a 4-W packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation to measured data under different classes of operation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132201950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549471
T. Aziz, M. Salleh, M. Yahaya, K. Triyana, K. Fujita
This paper reports the influence of annealing treatment on the performance of organic solar cells. The structure of ITO/PEDOT:PSS/P3HT:PCBM/LiF/Al bulk heterojunction solar cells were fabricated and annealed with three different temperature of 50°C, 100°C and 150°C respectively. IV characteristic of the device found that the annealing treatment might optimize the solar cell performance. For optimum device performance, maximum temperature at 100°C give the short-circuit current density (Jsc) of 0.55 mA/cm2 and energy conversion efficiency (η) ca. 2%. The experimental and the physics behind the improvement will be discussed in this paper.
{"title":"Effect of annealing treatment on the performance of organic solar cell","authors":"T. Aziz, M. Salleh, M. Yahaya, K. Triyana, K. Fujita","doi":"10.1109/SMELEC.2010.5549471","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549471","url":null,"abstract":"This paper reports the influence of annealing treatment on the performance of organic solar cells. The structure of ITO/PEDOT:PSS/P3HT:PCBM/LiF/Al bulk heterojunction solar cells were fabricated and annealed with three different temperature of 50°C, 100°C and 150°C respectively. IV characteristic of the device found that the annealing treatment might optimize the solar cell performance. For optimum device performance, maximum temperature at 100°C give the short-circuit current density (Jsc) of 0.55 mA/cm2 and energy conversion efficiency (η) ca. 2%. The experimental and the physics behind the improvement will be discussed in this paper.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549575
P. Divya, I. Saad
A review on the integration of vertical impact ionization MOSFET (IMOS) with vertical tunnelling FET (TFET) has been presented in this paper. A comparison has been done on the lateral and vertical I-MOS and TFET device structures, highlighting the advantages and drawbacks of each device. Integration of I-MOS and TFET on a vertical scale is seen as one of the promising solutions, to continue the trend of scaling down the devices further, in the nanometer regime.
{"title":"Feasibility study of integrated vertical and lateral IMOS and TFET devices for nano-scale transistors","authors":"P. Divya, I. Saad","doi":"10.1109/SMELEC.2010.5549575","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549575","url":null,"abstract":"A review on the integration of vertical impact ionization MOSFET (IMOS) with vertical tunnelling FET (TFET) has been presented in this paper. A comparison has been done on the lateral and vertical I-MOS and TFET device structures, highlighting the advantages and drawbacks of each device. Integration of I-MOS and TFET on a vertical scale is seen as one of the promising solutions, to continue the trend of scaling down the devices further, in the nanometer regime.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"107 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131746663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549448
F. Arsyad, P. Arifin, M. Barmawi, M. Budiman, S. Sukirno, A. Supu
This paper reported the study of growth of AlxGa1−xN thin film on a-plane sapphire substrate using plasma assisted metal organic chemical vapor deposition (PA-MOCVD). We have successfully growth the Al content AlGaN alloys and investigated the influence of TMA/TMAl+TMGa flow rate ratio to their crystal structure and surface morphology. From S EM image and XRD measurement, the AlGaN films grown with TMA/TMAl+TMGa flow rate ratio of 20% have single crystal orientation, homogeneous and smoother surface morphology. From ED X microanalysis results, all of the AlGaN alloys have high Al content. The Al content of the AlGaN alloys with TMA/TMAl+TMGa flow rate ratio of 20%, 30%, and 40% is about x = 0.5, 0.6, and 0.65, respectively and grown at the growth temperature about of 700°C.
{"title":"Growth of AlxGa1−xN epitaxial thin film on sapphire substrate by plasma assisted metal organic chemical vapor deposition (PA-MOCVD)","authors":"F. Arsyad, P. Arifin, M. Barmawi, M. Budiman, S. Sukirno, A. Supu","doi":"10.1109/SMELEC.2010.5549448","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549448","url":null,"abstract":"This paper reported the study of growth of AlxGa1−xN thin film on a-plane sapphire substrate using plasma assisted metal organic chemical vapor deposition (PA-MOCVD). We have successfully growth the Al content AlGaN alloys and investigated the influence of TMA/TMAl+TMGa flow rate ratio to their crystal structure and surface morphology. From S EM image and XRD measurement, the AlGaN films grown with TMA/TMAl+TMGa flow rate ratio of 20% have single crystal orientation, homogeneous and smoother surface morphology. From ED X microanalysis results, all of the AlGaN alloys have high Al content. The Al content of the AlGaN alloys with TMA/TMAl+TMGa flow rate ratio of 20%, 30%, and 40% is about x = 0.5, 0.6, and 0.65, respectively and grown at the growth temperature about of 700°C.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133925257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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